Heterogeneous chip and equipment

Abstract

The invention discloses a heterogeneous chip and equipment. The heterogeneous chip comprises a packaging substrate, a plurality of functional core particles and power supply core particles. The plurality of functional core particles are respectively arranged on the packaging substrate. The power supply core particle is arranged on the packaging substrate, a plurality of power supply conversion circuits are arranged on the power supply core particle, and the plurality of power supply conversion circuits are connected with an external power supply through the same group of external pins and are respectively used for converting power supply signals input by the external power supply and outputting the converted power supply signals to the corresponding functional core particles. According to the embodiment of the invention, suitable power supply input can be provided for different functional core particles, the types of input power supplies of heterogeneous chips can be reduced, and the complexity of circuit board level design is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a heterogeneous chip and device. Background Art

[0002] As chip functions and design complexity increase, SOC (System on a Chip) chips will contain a large number of different IP modules, and different IP modules usually have different requirements for power supply voltage level, current size, and power quality. Conventional designs will use different power circuits on the circuit to meet different power requirements on the chip, and input them to various modules on the chip through chip pins. The problem with this solution is that the chip may require too many types of input power, which increases the complexity of circuit board level design. Summary of the invention

[0003] The embodiments of the present application provide a heterogeneous chip and device, which can reduce the types of input power supplies for the chip and reduce the complexity of circuit board-level design.

[0004] In a first aspect, an embodiment of the present application provides a heterogeneous chip, including:

[0005] Package substrate;

[0006] A plurality of functional core particles, wherein the plurality of functional core particles are respectively arranged on the packaging substrate;

[0007] A power chip is arranged on the packaging substrate, and a plurality of power conversion circuits are provided on the power chip. The plurality of power conversion circuits are connected to an external power supply through a same set of external pins and are respectively used to convert power signals input by the external power supply and output them to the corresponding functional chip.

[0008] In one embodiment, the functional coregrain includes a computing coregrain and an interface coregrain.

[0009] In one embodiment, each of the power conversion circuits includes a buck circuit, and the buck circuit is used to convert a high voltage input from the external pin into a low voltage.

[0010] In one embodiment, the step-down circuit includes a low dropout linear regulator.

[0011] In one embodiment, the step-down circuit includes a PWM controller and a switch tube of a Buck circuit, and the capacitor and inductor of the Buck circuit are arranged on the packaging substrate.

[0012] In one embodiment, the external pins include a voltage input pin and a ground pin;

[0013] The switch tube comprises a first end, a second end and a controlled end, the first end is connected to the voltage input pin, the second end is connected to one end of the inductor, and the controlled end is connected to the output end of the PWM controller;

[0014] The PWM controller comprises an input terminal, a ground terminal and the output terminal, wherein the input terminal is connected to the voltage input pin, and the ground terminal is connected to the ground pin;

[0015] The other end of the inductor is connected to one end of the capacitor, and the other end of the capacitor is connected to the ground terminal of the PWM controller;

[0016] Two ends of the capacitor are connected to the functional core particle respectively.

[0017] In one embodiment, the functional core particle includes an interface core particle, a power control circuit is provided between the interface core particle and the power core particle, and the interface core particle dynamically controls the power core particle through the power control circuit.

[0018] In one embodiment, the packaging substrate is provided with a plurality of pin contacts connected to the power chip in an area corresponding to the power chip;

[0019] The arrangement density of the plurality of pin contacts connected to the power chip is greater than the arrangement density of the pin contacts of the functional chip; or

[0020] The areas of the pin contacts connected to the power chip are larger than the areas of the pin contacts of the functional chip.

[0021] In one embodiment, the power chip is disposed on the top and / or bottom of the packaging substrate.

[0022] In a second aspect, an embodiment of the present application further provides a device, comprising the heterogeneous chip as described above.

[0023] In the embodiment of the present application, the independently designed power core particles and other functional core particles of the chip are packaged on the same packaging substrate to achieve heterogeneity of the power core particles and the functional core particles. The power core particles are provided with multiple power conversion circuits, which are connected to the external power supply through the same set of external pins and are respectively used to convert the power signal input by the external power supply and output it to the corresponding functional core particles, thereby providing suitable power input for different functional core particles, reducing the types of input power supplies of heterogeneous chips, and reducing the complexity of circuit board level design. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the power supply of the heterogeneous chip according to an embodiment of the present application.

[0025] Figure 2 This is a schematic diagram of power supply for a heterogeneous chip according to another embodiment of the present application.

[0026] Figure 3 This is a schematic diagram of a heterogeneous chip according to an embodiment of the present application, wherein a power chip is disposed on top of a packaging substrate.

[0027] Figure 4 This is a schematic diagram of a heterogeneous chip according to another embodiment of the present application, wherein a power chip is disposed on top of a packaging substrate.

[0028] Figure 5 This is a schematic diagram of a heterogeneous chip according to another embodiment of the present application, wherein the power chip is disposed at the bottom of the package substrate.

[0029] Figure 6 Schematic diagram of the arrangement of pin contacts on the packaging substrate of an embodiment of the present application.

[0030] Figure 7 This is a schematic diagram of the arrangement of pin contacts on a packaging substrate according to another embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] As chip functions and design complexity increase, SOC chips will contain a large number of different IP modules, and different IP modules usually have different requirements for power supply voltage level, current size, and power quality. Conventional designs will use different power circuits on the circuit to meet different power requirements on the chip, and input them to various modules on the chip through chip pins. The problem with this solution is that the chip may require too many types of input power, which increases the complexity of circuit board level design.

[0033] To this end, the embodiments of the present application provide a heterogeneous chip solution to solve the technical problem that there are too many types of chip input power supplies, which increases the complexity of circuit board-level design.

[0034] See also Figures 1 to 7 , an embodiment of the present application discloses a heterogeneous chip.

[0035] The heterogeneous chip includes: a package substrate (Substrate) 10, a plurality of functional core particles 20 and a power core particle 30. The plurality of functional core particles 20 are respectively arranged on the package substrate 10. The power core particles 30 are arranged on the package substrate 10, and a plurality of power conversion circuits 31 are arranged on the power core particles 30. The plurality of power conversion circuits 31 are connected to an external power supply (not shown) through the same set of external pins and are respectively used to convert the power signal input by the external power supply and output it to the corresponding functional core particles 20.

[0036] In the embodiment of the present application, the independently designed power core 30 and other functional cores 20 of the chip are packaged on the same packaging substrate 10, so as to realize the heterogeneity of the power core 30 and the functional core 20. A plurality of power conversion circuits 31 are provided on the power core 30, and the plurality of power conversion circuits 31 are connected to the external power supply through the same set of external pins and are respectively used to convert the power signal input by the external power supply and output it to the corresponding functional core 20, thereby providing suitable power input for different functional cores 20 (the power supply of each functional core 20 is solved on the chip), which can reduce the types of input power of the heterogeneous chip (can be reduced to one or a few), and reduce the complexity of the circuit board level design.

[0037] Specifically, the functional chip 20 includes a computing chip 21 (CCD) and an interface chip 22 (IO Die). The package substrate 10 is provided with a plurality of connection pins corresponding to each computing chip 21 and each interface chip 22.

[0038] When the functional chip 20 is an interface chip 22, a power control circuit 19 can be provided between the interface chip 22 and the power chip 30. The interface chip 22 dynamically controls the power chip 30 through the power control circuit 19. The power control signal transmitted through the power control circuit 19 can be a standard low-speed interface signal, such as I2C, SMBus, etc.

[0039] The external pins of the heterogeneous chip may include a voltage input pin Vin and a ground pin GND. The external pins are disposed on the package substrate 10 .

[0040] exist Figure 1In the example, the power chip 30 can be connected to the external power supply only through a set of external pins, that is, each power conversion circuit 31 on the power chip 30 is connected to the external power supply through the same set of external pins. However, the power chip 30 is not limited to being connected to the external power supply only through a set of external pins. When the power chip 30 can be connected to the external power supply through more than one set of external pins, it is not excluded that a power conversion circuit 31 can be connected to more than one set of external pins at the same time (for example, it is connected to the same set of external pins as one of the aforementioned multiple power conversion circuits 31 and also connected to another set of external pins). In addition, the power chip 30 can be provided with other power conversion circuits 31 in addition to the aforementioned multiple power conversion circuits 31. Other power conversion circuits 31 can be connected to the external power supply through external pins other than the aforementioned same set of external pins, and the external power supplies can be the same or different.

[0041] It should be noted that the power supply relationship between each power conversion circuit and each functional core can be set as needed. For example, some power conversion circuits have a one-to-one correspondence with some functional cores, or at least two power conversion circuits can be connected to the same functional core, or there are some power conversion circuits that can be connected to more than one functional core, and so on.

[0042] It should be noted that the power conversion circuit 31 provided on the power chip 30 is not limited to being a complete power conversion circuit, but may also be a part of a complete power conversion circuit. For example, in order to facilitate the production of a standardized power chip 30, a partial component 32 of the complete power conversion circuit may be provided on the package substrate 10 (such as the capacitor and inductor of the Buck circuit), so that the power chip 30 can be adapted to more different chips.

[0043] It should be noted that one power chip 30 may be disposed on the packaging substrate 10 , or more than one power chip 30 may be disposed on the packaging substrate 10 , and different power chips 30 may be connected to the same external pin or to different external pins.

[0044] The ports of the power conversion circuit 31 can be connected correspondingly via the circuits on the packaging substrate 10 .

[0045] The power chip 30 may be a standard module developed by the enterprise itself, or a standard module of a general solution provided by an IP design company.

[0046] Specifically, each power conversion circuit 31 includes a step-down circuit, which is used to convert a high voltage input from an external pin into a low voltage. Different step-down circuits can provide the voltage required by the corresponding functional core 20. Of course, this is not limited to this.

[0047] Since each power conversion circuit 31 on the power chip 30 includes a step-down circuit, the high-voltage power input through the external pin is converted by different step-down circuits and provided to the corresponding functional chip 20, which can reduce the current input from the outside of the chip, making it easier to meet the requirements of the maximum current upper limit of a single pin of the chip, which is conducive to reducing the number of external pins. In addition, the chip can provide more different low-power power supplies to the corresponding functional chip 20 when there is one or a few input voltages, and can reduce the requirements for voltage accuracy.

[0048] Specifically, the step-down circuit includes a low dropout linear regulator (LDO) 33 .

[0049] Specifically, the input end of the low voltage difference linear regulator 33 is connected to the voltage input pin Vin, the ground end is connected to the ground pin GND, and the output end and the ground end are respectively connected to the functional core particle 20 to supply power to the functional core particle 20. It can be understood that the ports of the low voltage difference linear regulator 33 can be correspondingly connected through the lines on the packaging substrate 10.

[0050] Specifically, the step-down circuit includes a PWM controller 34 and a switch tube M of a Buck circuit, that is, the PWM controller 34 and the switch tube M of the Buck circuit are arranged in the power chip 30 .

[0051] Pulse-Width Modulation (PWM) is a technology that uses the digital output of a microprocessor to control an analog circuit. The PWM in the embodiment of the present application refers to using the PWM technology to perform voltage regulation control on a power supply.

[0052] Specifically, the capacitor C and the inductor L of the Buck circuit are arranged on the package substrate 10. By arranging the capacitor C and the inductor L of the Buck circuit on the package substrate 10, rather than arranging the entire Buck circuit on the power chip 30, the capacitor C and the inductor L can be specifically arranged on the package substrate 10 based on the power supply requirements of different functional chips 20, which is conducive to the large-scale production of more universal power chips 30 and improves the scope of use of the power chips 30.

[0053] For the PWM circuit, it can operate at a higher switching frequency, which can reduce the size of the inductor L / capacitor C on the package substrate 10 and is beneficial to reducing the overall size of the power chip 30 .

[0054] Of course, when the PWM controller 34 and the switch tube M are provided on the power chip 30 , it is not limited to disposing the corresponding capacitor C and inductor L on the packaging substrate 10 . For example, the complete Buck circuit can also be disposed on the power chip 30 .

[0055] More specifically, the switch tube M includes a first end, a second end and a controlled end, the first end is connected to the voltage input pin Vin, the second end is connected to one end of the inductor L, and the controlled end is connected to the output end of the PWM controller 34. The PWM controller 34 includes an input end, a ground end and an output end, the input end is connected to the voltage input pin Vin, and the ground end is connected to the ground pin GND. The other end of the inductor L is connected to one end of the capacitor C, and the other end of the capacitor C is connected to the ground end of the PWM controller 34. The two ends of the capacitor C are respectively connected to the functional core particle 20.

[0056] It is understandable that the above description is merely an example of a Buck circuit and is not limited thereto.

[0057] More specifically, the switch tube M is a MOSFET, the first end is the source, the second end is the drain, and the controlled end is the gate, that is, the source of the MOSFET is connected to the voltage input pin Vin, the drain is connected to one end of the inductor L, and the gate is connected to the output end of the PWM controller 34.

[0058] More specifically, the step-down circuit further includes a diode D of the Buck circuit. The cathode of the diode D is connected to the second end of the switch tube M, and the anode of the diode is connected to the ground terminal of the PWM controller 34.

[0059] It is understandable that the step-down circuit is not limited to the above-mentioned LDO, Buck circuit PWM controller 34 and switch tube M, but can also be other forms of step-down circuits. In addition, the power conversion circuit 31 is not limited to a step-down circuit.

[0060] Specifically, the packaging substrate 10 is arranged with a plurality of pin contacts 11 connected to the power chip 30 in the area corresponding to the power chip 30, and the pin contacts include power pin contacts and ground pin contacts. The arrangement density of the plurality of pin contacts 11 connected to the power chip 30 is greater than the arrangement density of the pin contacts 12 of the functional chip 20 (e.g. Figure 6 or, the area of ​​the plurality of pin contacts 11 connected to the power chip 30 is larger than the area of ​​the pin contacts 12 of the functional chip 20 (as shown in FIG. Figure 7 As shown in FIG. 1 ). Since the area is set to correspond to the power pin and ground pin of the power chip 30, there is no need to consider the high performance requirements of the high-speed signal on the pin, so Figure 6 or Figure 7 The solution shown, that is, adopting a denser arrangement while keeping the area of ​​the pin contacts 11 unchanged, or making the pin contacts 11 have a larger area, both of which can achieve a larger current under the same packaging area.

[0061] Combination Figures 3 to 5Regarding the location of the power chip 30 , different numbers and types of power chips 30 may be located at different locations on the package substrate 10 according to different chip types.

[0062] Figure 3 A schematic diagram of a power chip 30 located on top of a package substrate 10 is provided. Figure 3 In the example shown in FIG. 1 , two power chips 30 are disposed on the top of the package substrate 10 .

[0063] As the compactness requirements of modern chip and package design become higher and higher, combined with different packaging production processes, the power chip 30 can be located on the top of the package substrate 10 (such as Figure 3 and Figure 4 ), or may be located at the bottom of the package substrate 10 (as shown Figure 5 As shown in the figure, power chips 30 can be provided on the top and bottom of the package substrate 10. The main factors to be considered in the design of this part are: 1. The power chip 30 is as close as possible to the part that needs its power supply; 2. The position selection needs to consider the heat dissipation requirements of the power chip 30 itself. The power chip 30 with high heat dissipation requirements can be cooled by the heat sink attached to the chip; 3. The position of the power chip 30 can meet the requirements of a more compact package design without affecting the wiring design of the high-speed signal and power plane on the package substrate 10.

[0064] An embodiment of the present application also discloses a device, including the heterogeneous chip as described above.

[0065] In the embodiment of the present application, the independently designed power core 30 and other functional cores 20 of the chip are packaged on the same packaging substrate 10, so as to realize the heterogeneity of the power core 30 and the functional core 20. A plurality of power conversion circuits 31 are provided on the power core 30, and the plurality of power conversion circuits 31 are connected to the external power supply through the same set of external pins and are respectively used to convert the power signal input by the external power supply and output it to the corresponding functional core 20, thereby providing suitable power input for different functional cores 20, reducing the types of input power supplies of the heterogeneous chip and reducing the complexity of the circuit board level design.

[0066] The above disclosure is only a preferred example of the present application and cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are all within the scope covered by the present application.

Claims

1. A heterogeneous chip, characterized in that: include: Package substrate; A plurality of functional core particles, wherein the plurality of functional core particles are respectively arranged on the packaging substrate; A power chip is arranged on the packaging substrate, and a plurality of power conversion circuits are provided on the power chip. The plurality of power conversion circuits are connected to an external power supply through a same set of external pins and are respectively used to convert power signals input by the external power supply and output them to the corresponding functional chip.

2. The heterogeneous chip according to claim 1, characterized in that: The functional core particles include computing core particles and interface core particles.

3. The heterogeneous chip according to claim 1, characterized in that: Each of the power conversion circuits includes a step-down circuit, and the step-down circuit is used to convert a high voltage input from the external pin into a low voltage.

4. The heterogeneous chip according to claim 3, characterized in that: The step-down circuit includes a low voltage drop linear regulator.

5. The heterogeneous chip according to claim 3, characterized in that: The step-down circuit includes a PWM controller and a switch tube of a Buck circuit, and the capacitor and inductor of the Buck circuit are arranged on the packaging substrate.

6. The heterogeneous chip according to claim 5, characterized in that: The external pins include a voltage input pin and a ground pin; The switch tube comprises a first end, a second end and a controlled end, the first end is connected to the voltage input pin, the second end is connected to one end of the inductor, and the controlled end is connected to the output end of the PWM controller; The PWM controller comprises an input terminal, a ground terminal and the output terminal, wherein the input terminal is connected to the voltage input pin, and the ground terminal is connected to the ground pin; The other end of the inductor is connected to one end of the capacitor, and the other end of the capacitor is connected to the ground terminal of the PWM controller; Two ends of the capacitor are connected to the functional core particle respectively.

7. The heterogeneous chip according to claim 1, characterized in that: The functional core particle includes an interface core particle. A power control circuit is provided between the interface core particle and the power core particle. The interface core particle dynamically controls the power core particle through the power control circuit.

8. The heterogeneous chip according to claim 1, characterized in that: The packaging substrate is provided with a plurality of pin contacts connected to the power chip in an area corresponding to the power chip; The arrangement density of the plurality of pin contacts connected to the power chip is greater than the arrangement density of the pin contacts of the functional chip; or The areas of the pin contacts connected to the power chip are larger than the areas of the pin contacts of the functional chip.

9. The heterogeneous chip according to claim 1, characterized in that: The power chip is disposed on the top and / or bottom of the packaging substrate.

10. A device, characterized in that: Comprising a heterogeneous chip as described in any one of claims 1 to 9.

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