Driving interface design applied to micro-dot matrix light source

Abstract

The invention is suitable for the technical field of micro-dot matrix light sources, and provides a driving interface design applied to a micro-dot matrix light source, and a driving interface device applied to the micro-dot matrix light source, which comprises a circuit board, a chip, a data line, a driving interface, the micro-dot matrix light source and a driving interface system, the circuit board is suitable for receiving and transmitting data; the chip is arranged in the circuit board, and the chip is suitable for processing data; the data line is connected with a driving interface and is suitable for transmitting data processed by the chip; the driving interface is connected with the micro-dot matrix light source, and the driving interface is suitable for stably transmitting processed data to the micro-dot matrix light source; the micro-dot matrix light source is suitable for providing a display function. The device solves the problems of low transmission rate, small transmission bandwidth, weak anti-interference capability, numerous pins and complex wiring, and achieves the effects of improving the data transmission rate, improving the resolution and the frame rate, reducing the power consumption, prolonging the endurance time and reducing the chip cost.

Description

Technical Field

[0001] The present invention relates to the technical field of micro dot matrix light source, and more specifically, to the design of a driving interface applied to a micro dot matrix light source. Background Art

[0002] Traditional micro-dot matrix light sources usually use the parallel interface VGA to communicate with external devices, which is difficult to meet the requirements of high-speed transmission, low power consumption, anti-interference, high compatibility, etc. With the gradual standardization of the MIPI-DSI interface standard, it has been widely used in more and more mobile electronic devices and micro-dot matrix light sources.

[0003] At present, the traditional VGA communication interface has obvious limitations. Its main application scope is concentrated in relatively low-resolution scenes such as 720P, and it is difficult to adapt to high-resolution application requirements such as 4K. In addition, the previous parallel communication interface mostly adopts the LVCMOS33 interface level standard. When the bus is in the maximum bandwidth working state, due to the characteristics of the standard itself and the complexity of signal interaction during parallel transmission, the video stream signal is very susceptible to external interference. This interference not only affects the quality of video transmission, which is manifested as noise, flickering and even signal interruption on the screen, but also has an adverse effect on the internal CMOS driver chip, because when interfered, the CMOS driver chip needs to constantly adjust the working state to maintain signal transmission, which leads to increased power consumption, and then the chip temperature is too high, resulting in decreased stability. On the other hand, it is necessary to pass data to the micro-dot matrix light source in RGB888 pixel format. The pins must not only meet 24-bit data storage, but also receive row and column addressing signals, which adds many difficulties to the PCB circuit board packaging of the micro-dot matrix light source chip.

[0004] Therefore, a driving interface design for micro-dot matrix light source is proposed to solve the problems of low transmission rate, small transmission bandwidth, weak anti-interference ability, numerous pins and complex wiring. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a driving interface design for a micro-dot matrix light source that improves data transmission rate, improves resolution and frame rate, reduces power consumption, extends battery life, and reduces chip costs.

[0006] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a driving interface device applied to a micro-dot matrix light source, comprising a circuit board, a chip, a data line, a driving interface, a micro-dot matrix light source and a driving interface system; the circuit board is suitable for receiving and transmitting data; the chip is arranged inside the circuit board, and the chip is suitable for processing data; the data line is connected to the driving interface, and is suitable for transmitting data processed by the chip; the driving interface is connected to the micro-dot matrix light source, and the driving interface is suitable for stably transmitting the processed data to the micro-dot matrix light source; the micro-dot matrix light source is suitable for providing a display function; the driving interface system comprises a physical layer unit, a channel management layer unit, a bottom layer protocol layer unit, and an application layer unit. and IIC configuration module; the physical layer unit is suitable for receiving external data and converting it into universal data; the physical layer unit includes a data channel control module and a clock channel control module; the channel management layer unit is suitable for detecting errors and data recovery; the channel management layer unit includes a high-speed receiving module, a low-power receiving module, and a data fusion module; the bottom layer protocol layer unit is suitable for decoding and verifying data; the bottom layer protocol layer unit includes a data packet decoding module and an ECC verification module; the application layer unit is connected to the micro-dot matrix light source and communicates; the IIC configuration module is interconnected with the physical layer unit, the channel management layer unit, the bottom layer protocol layer unit, and the application layer unit.

[0007] By adopting the above technical solution and the MIPI driver interface, the high-speed data transmission mode is supported based on the MIPI protocol itself, and four channels are opened with a total bandwidth of up to 20Gbps. When the frame rate is adjusted, a variety of resolution configurations can be achieved, which improves the backward compatibility and makes the product more adaptable.

[0008] The working method of the driving interface device applied to the micro-dot matrix light source uses the driving interface device applied to the micro-dot matrix light source as described below, and includes the following steps: S1. The physical layer unit receives MIPI-DSI normal data and clock data from an external device, and converts them into a data format used inside the chip. The internally used data is divided into high-speed data and low-speed data, and the data is synchronously transmitted to the channel management layer unit for processing; S2, the data in the universal format enters the channel management layer unit, detects the relevant synchronization errors, transmits the errors to the bottom protocol layer unit, performs serial-to-parallel conversion on the serial data, performs data recovery, and ensures the integrity of data transmission; S3, the data from the channel management layer unit flows into the underlying protocol layer unit, and all kinds of data are correctly decoded, including high-speed data and low-speed commands, while supporting ECC checking and error correction for the received data, and synchronously transmitting the correctly decoded data to the application layer unit for processing; S4. Finally, the application layer unit is entered. The application layer unit is directly connected to the display terminal for communication, and the decoded data is converted and transmitted to the micro-dot matrix light source for display.

[0009] By adopting the above technical solution and MIPI-DSI high-speed serial transmission method, compared with the previous stacked pins to achieve row and column addressing and pixel assignment operations, the encapsulation of protocol layer frames has greatly reduced the number of required signal lines and pins on the circuit board, thereby speeding up the packaging of the circuit board.

[0010] The present invention is further configured that the data used internally in S1 is divided into high-speed data and low-speed data, and the specific method is configured as follows: S11, when the system is reset or powered on, both the clock channel and the data channel will enter the initialization state; after the initialization is completed, if a low power switching signal is detected, it will switch to the low power state; At this time, the clock channel and the data channel receive signals at the same time, and different data are processed differently, that is, S1111 is executed on the data of the clock channel, and S1121 is executed on the data of the data channel.

[0011] The present invention is further configured that, in S11, signals are simultaneously received according to the clock channel and the data channel, and different data are processed differently, that is, S1111 is executed on the data of the clock channel, and the specific method is configured as follows: S1111, when in the low power state, if an ultra-low power wait signal is detected, the clock channel will jump into the ultra-low power wait state, and if a high speed is detected, it will jump to the high speed state; S1112, when in the high-speed state, if the limit transmission signal is received, the clock channel switches to the high-speed clock state. This state uses a counter to count. After the counting is completed, it jumps to the high-speed clock end state; if a low-power switching is detected, it returns to the low-power state and reports an error; S1113, when the high-speed clock ends, low power consumption switching is detected, and the low power consumption state is directly entered; S1114, in the ultra-low power waiting state, if a limit transmission signal is received at this time, the ultra-low power state is entered; if the ultra-low power waiting is detected in the ultra-low power state, the ultra-low power state is exited; S1115. When exiting the ultra-low power consumption state, if a low power consumption switch is detected, directly jump to the low power consumption state.

[0012] The present invention is further configured that, in S11, signals are simultaneously received from the clock channel and the data channel, and different data are processed differently, that is, S1111 is executed on the data of the clock channel, and S1121 is executed on the data of the data channel. The specific method is configured as follows: S1121, when in the low power consumption state, if the FPGA detects a high-speed signal, the data channel switches to the high-speed data request state, and when a low power consumption switching signal is detected in this state, it returns to the low power consumption state; S1122, when in the high-speed state, if a limit transmission signal is received, the data channel switches to the high-speed transmission state, and if a low-power switching is detected, returns to the low-power state; S1123: When in the high-speed transmission state, after detecting the data transmission identifier, the state of transmitting data packets is entered, and until a signal or sequence of low-power switching or transmission end is detected, the state returns to the low-power state.

[0013] The present invention is further configured as follows: the high-speed receiving module is suitable for receiving high-speed data from a data channel, restoring the byte order, and detecting errors and transmitting them to the underlying protocol layer unit; the low-power receiving module is suitable for performing serial-to-parallel conversion for low-power serial data; and the data fusion module is suitable for performing serial-to-parallel conversion on serial data transmitted at high speed or low power consumption to restore data and ensure the integrity of data transmission.

[0014] The present invention is further configured as follows: the data packet decoding module receives and unifies the data transmitted at high speed and low power consumption, converts the two types of data into data of the same byte length and then caches them, and then parses the data to obtain specific information of the data; the ECC check module is suitable for comparing the check codes in the data packets.

[0015] The present invention is further configured as follows: the application layer unit includes a DPI data conversion module and a DBI data conversion module; the DPI data conversion module is suitable for converting DSI data into data conforming to the DPI format; the DBI data conversion module is suitable for converting DSI commands into DBI format output to implement read and write operations on the device.

[0016] The present invention is further configured as follows: the IIC configuration module is suitable for reading and writing registers, and configuring various MIPI-DSI parameter settings and transmission of command parameters to ensure successful handshake communication with the input end host.

[0017] The present invention is further configured such that: the chip adopts the low voltage differential pin LVDS level standard.

[0018] By adopting the above technical solution, the physical layer module receives four differential channels, whose signal level standard is one form of LVDS, and uses low voltage swing signal transmission (about 350mV), which significantly reduces power consumption compared to LVCMOS33. In addition, differential signal transmission has strong anti-interference ability against common mode noise, thereby improving signal transmission stability and reducing bit error rate.

[0019] In summary, the present application includes at least one of the following beneficial technical effects: 1. Adopt MIPI driver interface, support high-speed data transmission mode based on MIPI protocol itself, open four channels, and its total bandwidth can reach 20Gbps. When adjusting the frame rate, it can realize multiple resolution configurations, improve the backward compatibility, and make the product more adaptable.

[0020] 2. The physical layer module receives four differential channels, and its signal level standard is one form of LVDS, using low voltage swing signal transmission (about 350mV), which significantly reduces power consumption compared to LVCMOS33. Differential signal transmission has strong anti-interference ability to common mode noise, thereby improving signal transmission stability and reducing bit error rate.

[0021] 3. The MIPI-DSI high-speed serial transmission method is adopted. Compared with the previous stacked pins to realize row and column addressing and pixel assignment operations, the encapsulation of the protocol layer frame now greatly reduces the number of required signal lines and pins on the circuit board, and speeds up the circuit board packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic structural diagram of a driving interface device applied to a micro-dot matrix light source of the present invention; Figure 2 This is a diagram of the architecture of the driver interface in the present invention; Figure 3 It is a control logic diagram of the clock channel in the present invention; Figure 4 It is a control logic diagram of the data channel in the present invention; Figure 5 A circuit diagram of a low power consumption receiving module in the present invention; Figure 6 is a circuit diagram of a high-speed receiving module in the present invention; Figure 7 A circuit diagram of an ECC check module in the present invention; Figure 8 It is a state transition diagram of the data packet decoding module in the present invention; Fig. 9 It is the long packet format diagram of RGB888 in the present invention; Fig.10It is a timing diagram of the DBI interface in the present invention; Fig.11 It is a timing diagram of the IIC configuration in the present invention; Explanation of the accompanying drawings: 1. Circuit board; 2. Chip; 3. Data line; 4. Driving interface; 5. Micro-dot matrix light source. DETAILED DESCRIPTION

[0023] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meanings as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0025] See also Figure 1-10 , the present invention provides the following technical solutions: Embodiment 1: Traditional VGA communication interfaces are mostly used in low-resolution scenarios such as 720P, and cannot meet the requirements of high-resolution applications such as 4K. In addition, previous parallel communication interfaces mostly use the LVCMOS33 interface level standard. When the bus works at the maximum bandwidth, the video stream signal may be interfered with and the chip temperature may be too high.

[0026] See also Figure 1 , a driving interface device applied to a micro-dot matrix light source, comprising a circuit board 1, a chip 2, a data line 3, a driving interface 4, a micro-dot matrix light source 5 and a driving interface system; the circuit board 1 is suitable for receiving and transmitting data; the chip 2 is arranged inside the circuit board 1, and the chip 1 is suitable for processing data; the data line 3 is connected to the driving interface 4, and is suitable for transmitting data processed by the chip 2; the driving interface 4 is connected to the micro-dot matrix light source 5, and the driving interface is suitable for stably transmitting the processed data to the micro-dot matrix light source 5; the micro-dot matrix light source 5 is suitable for providing a display function; the chip 2 adopts the low voltage differential pin LVDS level standard; the data inside the chip 2 needs to be processed by the driving interface system, and the specific structure of the driving interface system is as follows: See also Figure 2The drive interface system includes a physical layer unit, a channel management layer unit, a bottom protocol layer unit, an application layer unit and an IIC configuration module; the physical layer unit is suitable for receiving external data and converting it into general data; the physical layer unit includes a data channel control module and a clock channel control module; the channel management layer unit is suitable for detecting errors and data recovery; the channel management layer unit includes a high-speed receiving module, a low-power receiving module, and a data fusion module. The high-speed receiving module is suitable for receiving high-speed data of the data channel and restoring the byte order, while detecting errors and transmitting them to the bottom protocol layer unit; the low-power receiving module is suitable for serial-to-parallel conversion for low-power serial data; the data fusion module is suitable for serial-to-parallel conversion of high-speed or low-power transmission serial data to recover data and ensure the integrity of data transmission; the bottom protocol layer unit is suitable for decoding and checking data; the bottom protocol layer unit includes a data packet decoding module and an ECC checking module The data packet decoding module receives and unifies the data transmitted at high speed and low power consumption, converts the two types of data into data of the same byte length and then caches them, and then parses the data to obtain specific data information; the ECC check module is suitable for comparing the check code in the data packet; the application layer unit is connected to the micro-dot matrix light source and communicates with it. The application layer unit includes a DPI data conversion module and a DBI data conversion module; the DPI data conversion module is suitable for converting DSI data into data that conforms to the DPI format; the DBI data conversion module is suitable for converting DSI commands into DBI format output to implement read and write operations on the device; the IIC configuration module is interconnected with the physical layer unit, the channel management layer unit, the underlying protocol layer unit, and the application layer unit. The IIC configuration module is suitable for reading and writing registers, and configuring various MIPI-DSI parameter settings and command parameter transmission to ensure successful handshake communication with the input host.

[0027] By adopting the MIPI driver interface, the MIPI protocol itself supports high-speed data transmission mode, and four channels are opened, with a total bandwidth of up to 20Gbps. When the frame rate is adjusted, multiple resolution configurations can be achieved, improving the backward compatibility and making the product more adaptable. On the other hand, the physical layer module receives four differential channels, and its signal level standard is one form of LVDS, using low voltage swing signal transmission (about 350mV), which significantly reduces power consumption compared to LVCMOS33. Differential signal transmission has strong anti-interference ability to common mode noise, thereby improving signal transmission stability and reducing bit error rate.

[0028] In the second embodiment, since the pixel format data of RGB888 is to be realized, the pins must satisfy the requirements of 24-bit data storage and receive row and column addressing signals, which adds many difficulties to the PCB packaging of the micro-dot matrix light source chip 2. Therefore, the packaging can only be realized by changing the data processing method. The specific method of the driving interface system is as follows: S1, the physical layer unit receives MIPI-DSI normal data and clock data from external devices, and converts them into the data format used inside chip 2, divides the internally used data into high-speed data and low-speed data, and synchronously transmits the data to the channel management layer unit for processing; S11, when the system is reset or powered on, both the clock channel and the data channel will enter the initialization state; after the initialization is completed, if a low power switching signal is detected, it will switch to the low power state; At this time, the clock channel and the data channel receive signals at the same time, and different data are processed differently, that is, S1111 is executed on the data of the clock channel, and S1121 is executed on the data of the data channel; S1111, when in the low power state, if an ultra-low power wait signal is detected, the clock channel will jump into the ultra-low power wait state, and if a high speed is detected, it will jump to the high speed state; S1112, when in high-speed state, if a limit transmission signal is received, the data channel switches to high-speed clock state, which uses a counter to count. After the count is completed, it jumps to the high-speed clock end state; if low-power switching is detected, it returns to the low-power state and reports an error; S1113, when the high-speed clock ends, low power consumption switching is detected, and the low power consumption state is directly entered; S1114, in the ultra-low power waiting state, if a limit transmission signal is received at this time, the ultra-low power state is entered; if the ultra-low power waiting is detected in the ultra-low power state, the ultra-low power state is exited; S1115, when exiting the ultra-low power consumption state, if a low power consumption switch is detected, directly jump to the low power consumption state; Among them, see Figure 3 , the specific control logic of the clock channel is as follows: Initialization state: that is, INIT state. After the system is reset or powered on, it enters this state. After waiting for a period of time, if the LP-11 state is detected, it will switch to STOP state next. Low power state: that is, STOP state, at this time, it enters the waiting state, and the bus is in LP-11; when the FPGA detects LP-10, it means that a request for ultra-low power mode has been received, and the state will jump to the ULPS_RQST state; if the FPGA detects LP-01, it means a high-speed mode request, and the state machine jumps to the HS_RQST state; High-speed state: HS_RQST state, indicating that a high-speed clock request is initiated at this time. If LP-00 is still detected, the state machine jumps to HS_CLK state; if LP-11 is detected, it returns to STOP state, and the timing error signal is pulled high; High-speed clock state: that is, HS_CLK state. When entering this state, the clock channel will turn on the high-speed clock, use the counter to count, and after a period of time, jump to the HS_EXIT state; High-speed clock end state: HS_EXIT state. In this state, LP-11 is detected and the system directly enters the STOP state. No response is given to other states. Ultra-low power waiting state: ULPS_RQST state. If LP-00 is received at this time, it will enter the ULPS state; Ultra-low power state: ULPS state, in which the clock channel runs at extremely low power consumption; if LP-10 is detected in this state, it will enter the ULPS_EXIE state; Exit ultra-low power state: ULPS_EXIT state. If LP-11 is detected at this time, it will jump directly to the STOP state; S1121, when in the low power consumption state, if a high-speed signal is detected, the data channel switches to the high-speed data request state, and when a low power consumption switching signal is detected in this state, returns to the low power consumption state; S1122, when in the high-speed state, if a limit transmission signal is received, the data channel switches to the high-speed transmission state, and if a low-power switching is detected, returns to the low-power state; S1123, when in the high-speed transmission state, after detecting the data transmission identifier, entering the data packet transmission state, until detecting the low-power switching or transmission end signal or sequence, then returning to the low-power state; Among them, see Figure 4 , the data channel control logic is as follows: Initialization state: that is, INIT state. After the system is reset or powered on, it enters this state. After waiting for a period of time, if LP-11 is detected, it will switch to STOP state next. Low power state: that is, STOP state, at this time it enters the waiting state, which is also a low power mode, and the bus is in LP-11; when the FPGA detects LP-01, it indicates a high-speed mode request, and the state jumps to the HS-RQST state; High-speed data request state: that is, HS-RQST state, indicating that a high-speed data request is initiated at this time. If LP-00 is still detected, the state machine jumps to HS-PRPR state; if LP-11 is detected, it returns to STOP state; High-speed state: HS-PRPR state, at this time, the data channel enters the high-speed transmission mode. After SoT is detected, it indicates the data transmission mark, and HST / HS-DESKEW is in the transmission data packet. If LP-11 or EoT transmission end sequence is detected at this time, the state returns to STOP; S2, the data in the universal format enters the channel management layer unit, detects the relevant synchronization errors, transmits the errors to the underlying protocol layer unit, converts the serial data into serial-to-parallel data, performs data recovery, and ensures the integrity of data transmission; The more specific steps of S2 are: S21. See Figure 5 After the low-power receiving module receives the esc_mode signal from the physical layer, it puts the data into the shift register, receives 8-bit data through the counter control, and then enters the command esc_cmd for decoding to obtain the corresponding control signal. If it is an LPDT command, lpdt_en is pulled high and rx_valid is output. If it is a ULPS, Trigger or other command, the corresponding enable control signal will be output. Others will output the error signal esc_cmd_err. S22, see Figure 6 The high-speed receiving module performs alternate sampling on the rising edge of the differential clock, receives 4-bit serial data respectively, and caches them in the shift register as hs_shift_p and hs_shift_n, and then alternately combines them to form 8-bit parallel data, realizing the conversion of the high-speed serial data received by the FPGA into parallel data output; S23, the data fusion module is responsible for receiving byte0, byte1, byte2, and byte3 transmitted by the host through four channels, and assigning them to the corresponding data channels in order. The FPGA receives and caches the received data byte by byte, and then merges the data of the four channels in order to restore the original data order; S3, the data from the channel management layer unit flows into the underlying protocol layer unit, and all kinds of data are correctly decoded, including high-speed data and low-speed commands, while supporting ECC check and error correction for the received data, and synchronously transmitting the correctly decoded data to the application layer unit for processing; The more specific steps of S3 are: S31, see Figure 7After the FPGA in the ECC check module receives the data packet, it also calculates the data parity_data composed of the first three bytes of the packet header to obtain the check code parity_bit_gen. Then, the ECC check code in the data packet is compared with the one calculated by the FPGA by performing an XOR operation to obtain ecc_err_detect. Then, the table is checked for judgment and correction based on the result. If the result is 0, it means that the data is correct. If it is the data in the error correction comparison table, it means that there is a 1-bit data error. The corresponding bit is inverted to get the correct result, and the ecc_err signal is pulled high. However, if the XOR result is different from any item in the table, it means that there are 2 bits or more errors. At this time, the ecc_multi_err signal is pulled high. In this way, 1-bit error correction and 2-bit data error detection are achieved; S32, see Figure 8 The data packet decoding module first receives the high-speed data and low-power transmission data synchronized into 32-bit data, caches it, and then parses it to obtain the data identifier, word length and ECC information; according to the Datatype information in the ID, it determines whether the data packet is a short packet or a long packet; if it is a long packet and the ECC check is correct, the state machine jumps to the next state; obtains the payload valid data and performs CRC calculation; if valid is valid, outputs the data; obtains the CRC data of the data packet PF; compares the calculated CRC with the CRC data at the end of the packet, if they are different, the state signal crc_err is set to 1, otherwise it is 0; S4, finally entering the application layer unit, the application layer unit directly connects with the display end to communicate, converts the decoded data and transmits it to the micro-dot matrix light source display; The more specific steps of S4 are: S41, see Fig. 9 , the DPI data conversion module needs to convert the DSI data into data that conforms to the DPI format, where the DSI image data is transmitted in the form of data packets, such as Figure 8 It is the transmission form of RGB888 type pixel data, which is generally transmitted in the format of a long packet, consisting of a packet header, packet data, and a packet tail; S42, see Fig.10 The DBI data conversion module mainly converts DSI commands into DBI format output to implement read and write operations on real devices; Fig. 9 In the DBI timing design, the circuit reset RESX signal is valid low, and the initial state of the CSX signal is high impedance. If the CSX signal is pulled low, it means that the chip select is valid; if the DCX signal is low at this time, it means that the current input command and data, if it is high, it means that it is data or parameter, and then according to the state of the WRX signal, if it is high, it is latched and input through DBI_I.

[0029] By adopting the MIPI-DSI high-speed serial transmission method, compared with the previous stacked pins to achieve row and column addressing and pixel assignment operations, the encapsulation of the protocol layer frame greatly reduces the number of required signal lines and pins on the circuit board 1, thereby speeding up the packaging of the circuit board 1.

[0030] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

Claims

1. A driving interface device for a micro dot matrix light source, the driving interface device is set based on the MIPI-DSI (Mobile Industry Processor Interface - Display Serial Interface) display interface protocol, characterized in that: It comprises a circuit board (1), a chip (2), a data line (3), a drive interface (4), a micro-dot matrix light source (5) and a drive interface system; The circuit board (1) is suitable for receiving and transmitting data; The chip (2) is arranged inside the circuit board (1), and the chip (1) is suitable for processing data; The data line (3) is connected to the drive interface (4) and is suitable for transmitting data processed by the chip (2); The driving interface (4) is connected to the micro-dot matrix light source (5), and the driving interface (4) is suitable for stably transmitting processed data to the micro-dot matrix light source (5); The micro-dot matrix light source (5) is suitable for providing a display function; The drive interface system includes a physical layer unit, a channel management layer unit, a bottom protocol layer unit, an application layer unit and an IIC configuration module; The physical layer unit is adapted to receive external data and convert it into general data; The physical layer unit includes a data channel control module and a clock channel control module; The channel management layer unit is suitable for error detection and data recovery; The channel management layer unit includes a high-speed receiving module, a low-power receiving module, and a data fusion module; The bottom protocol layer unit is suitable for decoding and verifying data; The bottom protocol layer unit includes a data packet decoding module and an ECC checking module; The application layer unit is connected to the micro dot matrix light source and communicates with it; The IIC configuration module is interconnected with the physical layer unit, the channel management layer unit, the bottom protocol layer unit, and the application layer unit.

2. A working method of a driving interface device applied to a micro-dot matrix light source, using the driving interface device applied to a micro-dot matrix light source as claimed in claim 1, characterized in that: The following steps are involved: S1. The physical layer unit receives MIPI-DSI normal data and clock data from an external device, and converts them into a data format used inside the chip. The internally used data is divided into high-speed data and low-speed data, and the data is synchronously transmitted to the channel management layer unit for processing; S2, the data in the universal format enters the channel management layer unit, detects the relevant synchronization errors, transmits the errors to the bottom protocol layer unit, performs serial-to-parallel conversion on the serial data, performs data recovery, and ensures the integrity of data transmission; S3, the data from the channel management layer unit flows into the underlying protocol layer unit, and all kinds of data are correctly decoded, including high-speed data and low-speed commands, while supporting ECC checking and error correction for the received data, and synchronously transmitting the correctly decoded data to the application layer unit for processing; S4. Finally, the application layer unit is entered. The application layer unit is directly connected to the display terminal for communication, and the decoded data is converted and transmitted to the micro-dot matrix light source for display.

3. The working method of the driving interface device applied to the micro-dot matrix light source according to claim 2, characterized in that: In the S1, the data used internally is divided into high-speed data and low-speed data, and the specific method is set as follows: S11, when the system is reset or powered on, both the clock channel and the data channel will enter the initialization state; after the initialization is completed, if a low power switching signal is detected, it will switch to the low power state; At this time, the clock channel and the data channel receive signals at the same time, and different data are processed differently, that is, S1111 is executed on the data of the clock channel, and S1121 is executed on the data of the data channel.

4. The working method of the driving interface device applied to the micro-dot matrix light source according to claim 3, characterized in that: In the S11, signals are simultaneously received from the clock channel and the data channel, and different data are processed differently, that is, S1111 is executed on the data of the clock channel, and the specific method is set as follows: S1111, when in the low power state, if an ultra-low power wait signal is detected, the clock channel will jump into the ultra-low power wait state, and if a high speed is detected, it will jump to the high speed state; S1112, when in the high-speed state, if the limit transmission signal is received, the clock channel switches to the high-speed clock state. This state uses a counter to count. After the counting is completed, it jumps to the high-speed clock end state; if a low-power switching is detected, it returns to the low-power state and reports an error; S1113, when the high-speed clock ends, low power consumption switching is detected, and the low power consumption state is directly entered; S1114, in the ultra-low power waiting state, if a limit transmission signal is received at this time, the ultra-low power state is entered; if the ultra-low power waiting is detected in the ultra-low power state, the ultra-low power state is exited; S1115. When exiting the ultra-low power consumption state, if a low power consumption switch is detected, directly jump to the low power consumption state.

5. The working method of the driving interface device applied to the micro-dot matrix light source according to claim 3, characterized in that: In S11, signals are simultaneously received from the clock channel and the data channel, and different data are processed differently, that is, S1111 is executed on the data of the clock channel, and S1121 is executed on the data of the data channel. The specific method is set as follows: S1121, when in the low power consumption state, if a high-speed signal is detected, the data channel switches to the high-speed data request state, and when a low power consumption switching signal is detected in this state, returns to the low power consumption state; S1122, when in the high-speed state, if a limit transmission signal is received, the data channel switches to the high-speed transmission state, and if a low-power switching is detected, returns to the low-power state; S1123: When in the high-speed transmission state, after detecting the data transmission identifier, the state of transmitting data packets is entered, and until a signal or sequence of low-power switching or transmission end is detected, the state returns to the low-power state.

6. The driving interface device for a micro-dot matrix light source according to claim 1, characterized in that: The high-speed receiving module is adapted to receive high-speed data from the data channel, restore the byte order, and detect errors for transmission to the underlying protocol layer unit; The low-power receiving module is suitable for performing serial-to-parallel conversion for low-power serial data; The data fusion module is suitable for performing serial-to-parallel conversion on serial data transmitted at high speed or low power consumption to restore data and ensure the integrity of data transmission.

7. The driving interface device for a micro-dot matrix light source according to claim 6, characterized in that: The data packet decoding module receives and unifies the data transmitted at high speed and low power consumption, converts the two data into data of the same byte length and caches them, and then parses the data to obtain specific information of the data; The ECC check module is suitable for comparing the check codes in the data packets.

8. The driving interface device for a micro-dot matrix light source according to claim 7, characterized in that: The application layer unit includes a DPI data conversion module and a DBI data conversion module; The DPI data conversion module is adapted to convert the DSI data into data in a DPI format; The DBI data conversion module is suitable for converting DSI commands into DBI format output to implement read and write operations on the device.

9. The driving interface device for a micro-dot matrix light source according to claim 8, characterized in that: The IIC configuration module is suitable for reading and writing registers, and configuring various MIPI-DSI parameter settings and transmission of command parameters to ensure successful handshake communication with the input host.

10. The driving interface device for a micro-dot matrix light source according to claim 9, characterized in that: The chip (2) adopts the low voltage differential pin LVDS level standard.

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