Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: a first substrate portion including a first insulating portion and a plurality of first wiring layers, each of the plurality of first wiring layers being disposed on or in the first insulating portion; a resin layer provided to cover a side surface of the first insulating portion; and a second substrate portion including a second insulating portion provided to cover each of an upper surface of the first insulating portion and an upper surface of the resin layer, and a second wiring layer provided on or in the second insulating portion.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0100479 filed on August 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Multi-chip packages including memory chips such as high bandwidth memory (HBM), processor chips such as central processing units (CPUs), graphic processing units (GPUs), and / or logic chips such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) have been used to process data that has been exponentially increasing due to the recent development of artificial intelligence (AI) technology. In order to mount various chips on a board, research has been conducted to more stably implement fine circuits on the board, prevent defects in the operation of manufacturing the board, and improve yield. Summary of the invention

[0004] An aspect of the present disclosure provides a printed circuit board on which electronic components such as chips are mounted, the printed circuit board being capable of preventing defects from occurring therein and the printed circuit board having an improved yield.

[0005] Another aspect of the present disclosure provides a printed circuit board having improved heat dissipation characteristics.

[0006] Another aspect of the present disclosure provides a method for manufacturing a printed circuit board having improved reliability.

[0007] According to one aspect of the present disclosure, a printed circuit board is provided, comprising: a first substrate portion, comprising a first insulating portion and a plurality of first wiring layers, each of the plurality of first wiring layers being arranged on the first insulating portion or in the first insulating portion; a resin layer, arranged to cover a side surface of the first insulating portion; and a second substrate portion, comprising a second insulating portion and a second wiring layer, the second insulating portion being arranged to cover each of an upper surface of the first insulating portion and an upper surface of the resin layer, and the second wiring layer being arranged on the second insulating portion or in the second insulating portion.

[0008] According to another aspect of the present disclosure, there is provided a printed circuit board, the printed circuit board comprising: a first substrate portion, comprising a first insulating portion and a first wiring layer disposed on or in the first insulating portion; a resin layer, disposed to cover a side surface of the first substrate portion; and a second substrate portion, comprising a second insulating portion and a second wiring layer, the second insulating portion being disposed on the first insulating portion and the resin layer, and the second wiring layer being disposed on or in the second insulating portion. The upper surface of the resin layer may be substantially coplanar with the upper surface of the first insulating portion.

[0009] According to another aspect of the present disclosure, there is provided a printed circuit board, the printed circuit board comprising: a first substrate portion, comprising a first insulating portion and a first wiring layer disposed on or in the first insulating portion; a resin layer, disposed to cover a side surface of the first substrate portion; a second substrate portion, comprising a second insulating portion and a second wiring layer, the second insulating portion being disposed on the first insulating portion and the resin layer, and the second wiring layer being disposed on or in the second insulating portion; and a third substrate portion, comprising a third insulating portion and a third wiring layer, the third insulating portion being disposed on the lower side of the first insulating portion, and the third wiring layer being disposed on or in the third insulating portion. The lower surface of the resin layer may be substantially coplanar with the lower surface of the lowermost first wiring layer among the first wiring layers.

[0010] According to example embodiments of the present disclosure, a printed circuit board having electronic components such as chips mounted thereon may prevent defects from occurring therein and may have an improved yield.

[0011] The printed circuit board may have improved heat dissipation characteristics.

[0012] The printed circuit board may have improved reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram illustrating an example of an electronic device system; Figure 2 is a schematic perspective view showing an example of an electronic device; Figure 3A and Figure 3B is a schematic cross-sectional view showing a printed circuit board according to an example; Figure 4A and Figure 4B is a schematic cross-sectional view showing a printed circuit board according to another example; Figure 5A and Figure 5B is a schematic cross-sectional view showing a printed circuit board according to still another example; and 6A to 6H is a schematic cross-sectional view illustrating a method for manufacturing a printed circuit board according to an example. DETAILED DESCRIPTION

[0014] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of components in the drawings may be exaggerated or reduced.

[0015] Electronic Devices Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0016] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. Such components may be connected to other electronic components to be described below via various signal lines 1090.

[0017] The chip-related components 1020 may include: a memory chip, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM) or a flash memory); an application processor chip, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor or a microcontroller; and a logic chip, such as an analog-to-digital converter or an application-specific integrated circuit (ASIC). However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips or electronic components.

[0018] The network-related components 1030 may include components compatible with or operating according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) Protocol, Fourth Generation Mobile Communication Technology (4G) Protocol, and Fifth Generation Mobile Communication Technology (5G) Protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or operating according to various other wireless standards or protocols or other wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0019] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0020] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0021] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a TV, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device for processing data.

[0022] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0023] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the electronic component 1120 may be the above-mentioned chip-related component (e.g., a component package 1121), but the present disclosure is not limited thereto. The component package 1121 may have the form of a printed circuit board on which electronic components (including active components and / or passive components) are surface-mounted. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0024] Printed Circuit Board Figure 3A and Figure 3B is a schematic cross-sectional view illustrating a printed circuit board according to an example.

[0025] Reference Figure 3A , a printed circuit board according to an example may include a first substrate portion 100, a second substrate portion 200, and a resin layer 500. The first substrate portion 100 may include a first insulating portion 110 and a plurality of first wiring layers 120, each of which is disposed on or in the first insulating portion 110, and the second substrate portion 200 may include a second insulating portion 210 and a second wiring layer 220 disposed on or in the second insulating portion 210.

[0026] The first substrate portion 100 may be a portion that implements a signal path of a printed circuit board, and the second substrate portion 200 may be a portion that connects the first substrate portion 100 and a component disposed on the printed circuit board to each other. The second substrate portion 200 may be a portion that implements a fine signal path, and when a component such as a semiconductor chip is mounted, the second substrate portion 200 may be a portion that functions as a buffer for a fine pad. That is, the second substrate portion 200 may be a portion for stably holding a component (such as a chip that is finer than the first substrate portion 100) and an electrical signal path.

[0027] The first insulating portion 110 of the first substrate portion 100 may include a plurality of insulating layers. More specifically, the first insulating portion 110 may include a core layer 111 disposed at a central portion thereof and a plurality of built-up insulating layers 112 disposed on the core layer 111. The first wiring layer 120 may be disposed on the core layer 111 and buried by the built-up insulating layer 112, or may be disposed on the built-up insulating layer 112 and buried by other built-up insulating layers 112. However, the present disclosure is not limited thereto, and the first substrate portion 100 may have a coreless board structure that does not include the core layer 111.

[0028] The core layer 111 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric exemplified by glass cloth) and these resins. The insulating material may be a photosensitive material and / or a non-photosensitive material. The insulating material may be a solder resist, Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), an insulating material such as resin coated copper (RCC), an insulating material such as copper clad laminate (CCL), etc., but the present disclosure is not limited thereto, and the insulating material may include other polymer materials. The insulating material may include a reinforcing material (such as an inorganic filler (such as silica) and glass fiber) and the above-mentioned resin. For example, a semi-cured sheet may be used, but the present disclosure is not limited thereto. In addition, in Figure 3A , the core layer 111 is shown as a single layer, but the present disclosure is not limited thereto, and a plurality of thin cores may be stacked to form the core layer 111 .

[0029] The stacked insulating layer 112 may include an insulating material. The insulating material of the stacked insulating layer 112 may be selected from a group of insulating materials that are the same as the insulating material of the core layer 111, but the present disclosure is not limited thereto. Any material that can be used as an insulating material for a printed circuit board may be selected. For example, the insulating material of the stacked insulating layer 112 may include a reinforcing material (such as an inorganic filler (such as silica) and glass fiber) and an insulating resin. Specifically, a semi-cured sheet may be used, but the present disclosure is not limited thereto, and the insulating material may include ABF. The stacked insulating layer 112 may include a plurality of insulating layers, and each of the stacked insulating layers 112 may include the same insulating material, but the present disclosure is not limited thereto, and a plurality of stacked insulating layers 112 may include different materials.

[0030] exist Figure 3A and Figure 3B , it is shown that two stacked insulating layers 112 are arranged on the upper side of the core layer 111, and three stacked insulating layers 112 are arranged on the lower side of the core layer 111. Such a configuration may be advantageous in preventing warping due to asymmetry in the operation of forming the second substrate portion 200 on the first substrate portion 100. However, the present disclosure is not necessarily limited thereto, and the number of stacked insulating layers 112 may be arranged symmetrically with respect to the core layer 111. In addition, the present disclosure is not limited thereto, and the number of stacked insulating layers 112 may vary depending on the purpose and design of the board, and may be unlimited.

[0031] The first substrate portion 100 of the printed circuit board according to the example may include a plurality of first wiring layers 120. A portion of the plurality of first wiring layers 120 may be disposed on the core layer 111, and the other portion may be disposed on the buildup insulating layer 112. The present disclosure is not limited thereto, and the first wiring layer 120 may not be disposed on the core layer 111, and the first wiring layer 120 may be disposed only on the buildup insulating layer 112. The number of the plurality of first wiring layers 120 of the first substrate portion 100 is not limited, and may correspond to the number of the buildup insulating layers 112.

[0032] Each of the plurality of first wiring layers 120 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the plurality of first wiring layers 120 may include a circuit pattern for a conventional signal path, and may perform various functions (such as having a function of mounting components thereon) according to its design. For example, the circuit pattern may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include a pattern for electrical connection of various signals (e.g., data signals) other than grounding, power, and the like. Each of the plurality of first wiring layers 120 may be formed using a plurality of circuit patterns, may be formed using a metal plate, or may be formed using a plurality of circuit patterns and a metal plate together.

[0033] Each of the plurality of first wiring layers 120 may be formed using one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) process, or a subtractive process, but the present disclosure is not limited thereto, and any method capable of forming a circuit pattern in a printed circuit board may be used without limitation. In addition, the plurality of first wiring layers 120 may be formed using different methods according to their purpose and design.

[0034] The first substrate portion 100 of the printed circuit board according to the example may include a plurality of first via layers 130 passing through at least a portion of the first insulating portion 110 to connect the plurality of first wiring layers 120 to each other. The plurality of first via layers 130 may include through vias 131 and build-up via layers 132. Passing through at least a portion of the first insulating portion 110 may mean passing through one build-up insulating layer 112 or the core layer 111 of the first insulating portion 110, or the first via layer 130 may be formed to pass through a plurality of build-up insulating layers 112 at a time or pass through the core layer 111 and at least one build-up insulating layer 112 at a time.

[0035] The through-hole 131 may include a metal layer formed on the wall surface of the through-hole passing through the core layer 111 and a plug portion filled in the space between the metal layers. The metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. The plug portion may be formed using an insulating material (e.g., ink). The metal layer may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both the sputtering layer and the electroless plating layer may be included. The through-hole 131 may perform various functions according to its design. For example, a ground via, a power via, a signal via, etc. may be included.

[0036] The plurality of stacked via layers 132 may include micro vias. The micro vias may be filled vias that fill the via holes, or may be conformal vias that are arranged along the wall surface of the via holes. The micro vias may be arranged in a stacked and / or staggered manner. Each of the plurality of stacked via layers 132 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the plurality of stacked via layers 132 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both the sputtering layer and the electroless plating layer may be included. The plurality of stacked via layers 132 may perform various functions according to the design of the corresponding layers. For example, ground vias, power vias, signal vias, etc. may be included.

[0037] As described above, the number of the stacked insulating layers 112 of the first insulating portion 110 and the number of the plurality of first wiring layers 120 may not be limited. Therefore, the number of layers of vias (components that pass through at least a portion of the first insulating portion 110 to connect the plurality of first wiring layers 120 to each other) may not be limited.

[0038] exist Figure 3A , the first substrate portion 100 is shown as including a first insulating portion 110, a first wiring layer 120 and a first via layer 130, but the present disclosure is not limited thereto, and the first substrate portion 100 may also include a cavity passing through at least a portion of the first insulating portion 110, and the first substrate portion 100 may also include technologies or components that can be used by those skilled in the art, such as the first substrate portion 100 may be a board with embedded electronic components, etc.

[0039] The second substrate portion 200 of the printed circuit board according to the example may include a second insulating portion 210 and a second wiring layer 220 disposed on or in the second insulating portion 210. When the second substrate portion 200 is disposed on the first substrate portion 100, the second insulating portion 210 may cover the upper surface of the first insulating portion 110, and the second insulating portion 210 may cover at least a portion of the first wiring layer 120. That is, the second insulating portion 210 may cover at least a portion of the uppermost first wiring layer 120 among the plurality of first wiring layers 120.

[0040] The second insulating portion 210 may include a plurality of insulating layers. Each of the plurality of insulating layers of the second insulating portion 210 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric exemplified by glass cloth) and these resins. The insulating material may be a photosensitive material and / or a non-photosensitive material. The insulating material may be a solder resist, ABF, FR-4, BT, an insulating material such as RCC, an insulating material such as CCL, etc., but the present disclosure is not limited thereto and may include other polymer materials. The insulating material may include a reinforcing material (such as an inorganic filler (such as silica) and glass fiber) and the above-mentioned resin. For example, a prepreg may be used, but the present disclosure is not limited thereto, and the insulating material may include ABF or a photosensitive material. The plurality of insulating layers of the second insulating portion 210 may include substantially the same insulating material, but the present disclosure is not limited thereto and may include different materials.

[0041] The second substrate portion 200 may include an insulating material that is more conducive to microfabrication than the first insulating portion 110 to achieve finer wiring than the wiring of the first substrate portion 100. For example, the content of the reinforcing material (such as inorganic filler and glass fiber) included in each insulating layer of the second insulating portion 210 may be greater than the content of the reinforcing material (such as inorganic filler and glass fiber) included in the buildup insulating layer 112 of the first insulating portion 110. The content of the reinforcing material (such as inorganic filler and glass fiber) in the insulating material of the second insulating portion 210 may be made greater than the content of the reinforcing material in the insulating material of the first insulating portion 110, thereby achieving an insulating layer that is conducive to microfabrication. However, the present disclosure is not necessarily limited thereto, and the second insulating portion 210 of the second substrate portion 200 and the first insulating portion 110 of the first substrate portion 100 may include substantially the same insulating material. In addition, the present disclosure is not limited thereto, and the second insulating portion 210 may include a photosensitive material, which may be more advantageous for microfabrication of forming wiring in the second insulating portion 210.

[0042] exist Figure 3A , the second insulating part 210 is illustrated as including four insulating layers, but the number of insulating layers of the second insulating part 210 is not limited thereto and may vary according to the purpose and design of the board and may be without limitation.

[0043] The second substrate portion 200 of the printed circuit board according to the example may include a plurality of second wiring layers 220. Each of the plurality of second wiring layers 220 may be disposed on the second insulating portion 210 or in the second insulating portion 210. The plurality of second wiring layers 220 may be disposed on one insulating layer of the second insulating portion 210 and buried in another insulating layer, or may be disposed on one insulating layer and exposed to the outside. The number of the plurality of second wiring layers 220 of the second substrate portion 200 is not limited, and may correspond to the number of insulating layers of the second insulating portion 210.

[0044] Each of the plurality of second wiring layers 220 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the plurality of second wiring layers 220 may include a circuit pattern for a conventional signal path, and may perform various functions (such as having a function of mounting components thereon) according to its design. For example, the circuit pattern may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include a pattern for electrical connection of various signals (e.g., a data signal) other than for grounding, power, and the like. Each of the plurality of second wiring layers 220 may be formed using a plurality of circuit patterns, may be formed using a metal plate, or may be formed using a plurality of circuit patterns and a metal plate together.

[0045] Each of the plurality of second wiring layers 220 may be formed using one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) process, or a subtractive process, but the present disclosure is not limited thereto, and any method capable of forming a circuit in a printed circuit board may be used without limitation. In addition, the plurality of second wiring layers 220 may be formed using different methods according to their purpose and design.

[0046] The second substrate portion 200 of the printed circuit board according to the example may include a plurality of second via layers 230 passing through at least a portion of the second insulating portion 210 to connect the plurality of second wiring layers 220 to each other. Passing through at least a portion of the second insulating portion 210 may mean passing through one insulating layer of the second insulating portion 210, or the second via layer 230 may be formed as a plurality of insulating layers passing through the second insulating portion 210 at one time. However, the present disclosure is not limited thereto, and one via layer among the plurality of second via layers 230 may pass through at least a portion of the second insulating portion 210 to connect the second wiring layer 220 disposed at the lowermost side of the second substrate portion 200 and the first wiring layer 120 disposed at the uppermost side of the first substrate portion 100 to each other.

[0047] The plurality of second via layers 230 may include micro vias. The micro vias may be filled vias that fill the via holes, or may be conformal vias that are arranged along the wall surface of the via holes. The micro vias may be arranged in a stacked and / or staggered manner. Each of the plurality of stacked via layers 132 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the plurality of second via layers 230 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both the sputtering layer and the electroless plating layer may be included. The plurality of second via layers 230 may perform various functions according to the design of the corresponding layers. For example, ground vias, power vias, signal vias, etc. may be included.

[0048] As described above, the number of insulating layers of the second insulating portion 210 and the number of the plurality of second wiring layers 220 may not be limited. Therefore, the number of layers of vias (components that pass through at least a portion of the second insulating portion 210 to connect the plurality of second wiring layers 220 to each other) may not be limited.

[0049] The wiring density of the second wiring layer 220 of the second substrate portion 200 may be higher than the wiring density of the first wiring layer of the first substrate portion 100. That is, the second wiring layer 220 may include wiring that is finer than the wiring of the first wiring layer 120. Higher wiring density may be based on a relative concept, and may mean, for example, that the average pitch of the wiring included in the second wiring layer 220 may be smaller than the average pitch of the wiring included in the first wiring layer 120. The pitch may be measured by photographing a cut section of a printed circuit board using a scanning microscope, and the average pitch may be the average value of the pitches between the wirings measured at any five points. In addition, the average interlayer insulation distance between the second wiring layers 220 may be smaller than the average interlayer insulation distance between the plurality of first wiring layers 120. The interlayer insulation distance may also be measured by photographing a cut section of a printed circuit board using a scanning microscope, and the average interlayer insulation distance may be the average value of the insulation distances between adjacent wiring layers measured at any five points. That is, the wiring included in the second wiring layer 220 may be a high-density fine wiring having a line width / space (L / S) smaller than the line width / space (L / S) of the wiring included in the first wiring layer 120. As a non-limiting example, the line width / space of the wiring included in the second wiring layer 220 may be about 2 μm / 2 μm, but the present disclosure is not limited thereto. Since the second wiring layer 220 of the second substrate portion 200 has a high wiring density, electronic components such as semiconductor chips may be efficiently mounted. That is, the second substrate portion 200 may be used as a redistribution layer of a semiconductor chip.

[0050] The printed circuit board according to the example may include a resin layer 500 disposed on a side surface of the first substrate portion 100. The resin layer 500 may be disposed to cover the side surface of the first insulating portion 110, and may be disposed on a lower surface of the second insulating portion 210. That is, the upper surface of the resin layer 500 may be covered by the second insulating portion 210. In other words, the second insulating portion 210 of the second substrate portion 200 may cover the upper surface of the first insulating portion 110 of the first substrate portion 100 and the upper surface of the resin layer 500.

[0051] After the first substrate portion 100 is completed, a resin layer 500 may be provided on the side surface of the first substrate portion 100, and the resin layer 500 may perform a function of supporting the first substrate portion 100. The second substrate portion 200 may be formed on the first substrate portion 100 and the resin layer 500, so that the above arrangement may be realized. After the first substrate portion 100 is completed, it may be determined whether there is a defect in the first substrate portion 100 before the resin layer 500 is bonded to the side surface of the first substrate portion 100, so that the defect rate of the printed circuit board may be reduced. In the case where the second substrate portion 200 is formed immediately after the first substrate portion 100 is formed, the defect in the printed circuit board may be a defect occurring in the first substrate portion 100 and / or a defect occurring in the second substrate portion 200. Therefore, realizing fine wiring on the first substrate portion 100 in which a defect has occurred (i.e., manufacturing the second substrate portion 200) may cause a waste of cost. In the printed circuit board according to the example, after the first substrate portion 100 is completed and it is determined whether there is a defect, the second substrate portion 200 may be formed using only the first substrate portion 100 in which the defect has occurred. Therefore, defects in the printed circuit board can be controlled by controlling defects in the second substrate part 200. That is, a situation in which defects occur in the printed circuit board due to the formation of a high-quality second substrate part 200 on a defective first substrate part 100 can be excluded. Therefore, in the case of manufacturing the printed circuit board according to the example in units of a single strip and then performing a singulation process, the first substrate part 100 can be manufactured first, and then the first substrate part 100 can be inserted into the jig J to fill the resin layer 500, thereby reducing the defect rate and minimizing the cost.

[0052] The resin layer 500 may include an organic material, and the organic material may include at least one of a thermal interface material (TIM), a bonding sheet, an epoxy molding compound (EMC), and an underfill resin, but the present disclosure is not limited thereto, and any material capable of bonding and fixing the first substrate portion 100 to the fixture J may be used without limitation. The bonding sheet may include an organic polymer material such as an epoxy resin, but is not limited thereto. When the resin layer 500 includes a TIM having excellent heat dissipation characteristics, the printed circuit board may have improved overall heat dissipation characteristics, and heat generated in an electronic component such as a semiconductor chip disposed on the second substrate portion 200 may be effectively dissipated to the outside.

[0053] The outermost portion of the side surface of the printed circuit board according to the example may include a resin layer 500. That is, the side surface of the resin layer 500 may be exposed to the outside of the printed circuit board. Relatively speaking, the first insulating portion 110 may be covered by the resin layer 500 so that the side surface of the first insulating portion 110 is not exposed to the outside of the printed circuit board. In addition, the side surface of the second insulating portion 210 may be substantially coplanar with the side surface of the resin layer 500. "Substantially coplanar" includes the concept of being roughly coplanar. In one example, the term "substantially" may refer to the concept of including slight differences caused by process errors or measurement errors. For example, "substantially coplanar" may include not only the case of "coplanarity", but also the case of having slight differences caused by process errors or measurement errors, which is understandable to those of ordinary skill in the art. When the second substrate part 200 is cut through the resin layer 500 for singulation after the second substrate part 200 is formed on the resin layer 500 in the manufacturing operation, the resin layer 500 may be arranged at the outermost side of the printed circuit board so that the side surface of the resin layer 500 may be coplanar with the side surface of the second insulating part 210 of the second substrate part 200. When the resin layer 500 has excellent heat dissipation characteristics, since the resin layer 500 is arranged at the outermost side of the printed circuit board, a more favorable heat dissipation effect can be obtained. The present disclosure is not limited to this, and the resin layer 500 may include a material with excellent rigidity to ensure the rigidity of the printed circuit board. The present disclosure is not limited to this, and the resin layer 500 can prevent the first insulating part 110 from scattering during the singulation process of the printed circuit board.

[0054] At least a portion of the second wiring layer 220 may be disposed on an upper region of the resin layer 500 (i.e., at least a portion of the second wiring layer 220 may overlap the resin layer 500 in the stacking direction of the printed circuit board). In the operation of manufacturing the printed circuit board, the resin layer 500 may be disposed on the side surface of the first substrate portion 100, and then the second substrate portion 200 may be formed on the first substrate portion 100 and the resin layer 500, so that the second substrate portion 200 may be formed to span the first substrate portion 100 and the resin layer 500. The area of ​​the second substrate portion 200 may be larger than the area of ​​the first substrate portion 100, and the difference in area may be an area corresponding to the area of ​​the resin layer 500. Therefore, the second wiring layer 220 of the second substrate portion 200 may be formed on a larger area, so that the area of ​​the second substrate portion 200 may be increased. The present disclosure is not limited thereto, and the second wiring layer 220 may be formed only in the first substrate portion 100. Here, the area may refer to an area observed in a cross section perpendicular to the stacking direction of the printed circuit board.

[0055] The printed circuit board according to the example may further include a third substrate portion 300 disposed at a lower side of the first insulating portion 110 of the first substrate portion 100. The third substrate portion 300 may include a third insulating portion 310 and a third wiring layer 320 disposed on or in the third insulating portion 310, and may include a third via layer 330 passing through at least a portion of the third insulating portion 310 to connect the third wiring layer 320 and the first wiring layer 120 to each other.

[0056] The third insulating portion 310 may include a material substantially the same as that of the second insulating portion 210. The third insulating portion 310 may be formed while forming the second insulating portion 210. Since the third insulating portion 310 is formed simultaneously with the second insulating portion 210, warpage occurring in an operation of manufacturing a printed circuit board according to an example may be controlled.

[0057] The third wiring layer 320 may be disposed at the lowermost side of the printed circuit board and may be used as a pad so that the printed circuit board is connected to other components, and the third via layer 330 may perform a function of connecting the third wiring layer 320 and the first wiring layer 120 to each other, but the present disclosure is not limited thereto. The third wiring layer 320 and / or the third via layer 330 may include a metal material, and the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or an alloy thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto.

[0058] A portion of the resin layer 500 may be buried in the third insulating portion 310. That is, the lower surface of the resin layer 500 may be covered by the third insulating portion, and a portion of the side surface of the resin layer 500 may be covered by the third insulating portion. Such a structure may be a structure according to an operation of manufacturing a printed circuit board, and will be described in detail below in a method for manufacturing a printed circuit board.

[0059] The printed circuit board according to the example may also include a solder resist layer 510 disposed on the second insulating portion 210 and / or the third insulating portion 310. The solder resist layer 510 may be disposed on the outermost side of the printed circuit board to protect the printed circuit board from external influences. The solder resist layer 510 may use a known solder resist, and the solder resist layer 510 may include an insulating resin and a filler dispersed in the insulating resin, but does not include glass fiber. The insulating resin may be a photosensitive insulating resin or a thermosetting resin, and the filler may be an inorganic filler and / or an organic filler, but the present disclosure is not limited thereto, and other polymer materials may be used as needed. The solder resist layer 510 may have an opening, and at least a portion of the second wiring layer 220 and at least a portion of the third wiring layer 320 may be exposed through the opening. The second wiring layer 220 exposed through the opening may be connected to another device such as a semiconductor chip, and the third wiring layer 320 exposed through the opening may be connected to a mainboard or another printed circuit board, and may also be connected to another device such as a semiconductor chip. In addition, a side surface of the solder resist layer 510 may be substantially coplanar with a side surface of the second insulating part 210 and a side surface of the resin layer 500 .

[0060] The printed circuit board according to the example may further include a surface treatment layer 520, which covers the exposed area of ​​the second wiring layer 220 and / or covers the exposed area of ​​the third wiring layer 320. The surface treatment layer 520 may include at least one of nickel (Ni), palladium (Pd) and gold (Au), and multiple layers formed using the above metals may be realized. The surface treatment layer 520 may be formed using an electroless nickel immersion gold (ENIG) method or an electroless nickel electroless palladium immersion gold (ENEPIG) method, but the present disclosure is not limited thereto. The surface treatment layer may include an organic substance. The surface treatment layer 520 may improve the bonding force and signal transmission of the wiring layer used as the pad of the printed circuit board and the components mounted on the printed circuit board.

[0061] Reference Figure 3B The printed circuit board according to the example may further include a semiconductor chip 600 disposed on the second substrate portion 200 and a connection member 610 for connecting the semiconductor chip 600 and the second wiring layer 220 of the second substrate portion 200 to each other.

[0062] Each of the semiconductor chips 600 may include an integrated circuit (IC) die in which hundreds to millions of devices are integrated into a single chip. In this case, the IC die may be, for example: a processor chip, such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (e.g., AP); a logic chip, such as a field programmable gate array (FPGA), an analog-to-digital converter, or an application-specific IC (ASIC), but the present disclosure is not limited thereto, and the IC die may also be a memory chip (such as a volatile memory (e.g., DRAM, high bandwidth memory (HBM)), a non-volatile memory (e.g., ROM, flash memory)) or a power management IC (PMIC). Optionally, the semiconductor chip 600 may be a segmented logic chip (segmented by die cutting), the segmented logic chips having different cores.

[0063] Each of the semiconductor chips 600 may be formed based on an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a substrate included in each body. Various circuits may be formed in the body. A connection pad may be formed on each body, and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). The semiconductor chip may be a bare die. In this case, a metal bump may be provided on the connection pad. The semiconductor chip may be a packaged die. In this case, a redistribution layer may be additionally formed on the connection pad, and a metal bump may be provided on the redistribution layer.

[0064] The connecting member 610 may be formed using a low melting point metal (e.g., solder such as tin (Sn)-aluminum (Al)-copper (Cu)), but the present disclosure is not limited thereto. The connecting member 610 may be formed in multiple layers or in a single layer. When formed in multiple layers, the connecting member 610 may include copper pillars and solder. When formed in a single layer, the connecting member 610 may include tin-silver solder or copper, but the present disclosure is not limited thereto. In addition, any device that serves as an intermediary for electrically connecting a semiconductor chip or an electronic component to the second wiring layer 220 of the second substrate portion 200 may be used without limitation. Figure 3B , two semiconductor chips are mounted, but the present disclosure is not limited thereto. A greater number of semiconductor chips may be mounted, and a greater or lesser number of semiconductor chips 600 may also be electrically connected to each other through the connection member 610.

[0065] The printed circuit board according to the example is not limited to Figure 3A and Figure 3B The components shown in the figure may also include conventional components of a printed circuit board. That is, the printed circuit board may also include components that can be used by those skilled in the art.

[0066] Figure 4A and Figure 4B is a schematic cross-sectional view showing a printed circuit board according to another example.

[0067] Reference Figure 4A and Figure 4B According to another example, the printed circuit board may further include a fourth substrate portion 400. The fourth substrate portion 400 may include: a fourth insulating portion 410 disposed on a side surface of the resin layer 500, a side surface of the second insulating portion 210, and a side surface of the third insulating portion 310; a fourth wiring layer 420 disposed on or in the fourth insulating portion; and a fourth via layer 430 passing through at least a portion of the fourth insulating portion 410 to connect the fourth wiring layers 420 to each other.

[0068] The fourth insulating portion 410 may include a fourth-first insulating portion 411, a fourth-second insulating portion 412, and a fourth-third insulating portion 413. The fourth-first insulating portion 411 may correspond to the first insulating portion 110, the fourth-second insulating portion 412 may correspond to the second insulating portion 210, and the fourth-third insulating portion 413 may correspond to the third insulating portion 310.

[0069] The fourth wiring layer 420 may include a fourth-first wiring layer 421, a fourth-second wiring layer 422, and a fourth-third wiring layer 423. The fourth-first wiring layer 421 may correspond to the first wiring layer 120, the fourth-second wiring layer 422 may correspond to the second wiring layer 220, and the fourth-third wiring layer 423 may correspond to the third wiring layer 320.

[0070] The fourth via layer 430 may include a fourth-first via layer 431, a fourth-second via layer 432, and a fourth-third via layer 433. The fourth-first via layer 431 may correspond to the first via layer 130, the fourth-second via layer 432 may correspond to the second via layer 230, and the fourth-third via layer 433 may correspond to the third via layer 330.

[0071] That a component of the fourth substrate portion 400 corresponds to a component of the first substrate portion 100, the second substrate portion 200 or the third substrate portion 300 may mean that: a component of the fourth substrate portion 400 includes substantially the same material as a component of the first substrate portion 100, the second substrate portion 200 or the third substrate portion 300, includes the same number of layers as a component of the first substrate portion 100, the second substrate portion 200 or the third substrate portion 300, has substantially the same thickness or density as a component of the first substrate portion 100, the second substrate portion 200 or the third substrate portion 300, or can be formed according to the same operation as that of a component of the first substrate portion 100, the second substrate portion 200 or the third substrate portion 300. For example, “the fourth-first insulating portion 411 may correspond to the first insulating portion 110” may mean that the components of the fourth-first insulating portion 411 may be the same as the components of the first insulating portion 110, and may mean that the fourth-first insulating portion 411 may include a core layer 111 and a buildup insulating layer 112, and may have the same number of layers. Such a configuration may be applied in the same manner between other components of the fourth substrate portion 400 and corresponding components of the second substrate portion 200 or the third substrate portion 300, and may be applied not only to the insulating portion but also to the wiring layer and the via layer. For example, the density of the wiring of the fourth-first wiring layer 421 may be substantially the same as the density of the wiring of the first wiring layer 120, and the density of the wiring of the fourth-second wiring layer 422 may be substantially the same as the density of the wiring of the second wiring layer 220.

[0072] The fourth substrate portion 400 may be disposed on the side surface of the resin layer 500, and may be disposed on the side surface of the second substrate portion 200 and the side surface of the third substrate portion 300. However, the fourth substrate portion 400 may not have a clearly distinguished boundary with the second substrate portion 200 and the third substrate portion 300, and the fourth substrate portion 400 may be understood as an area of ​​a printed circuit board, rather than a separately formed board component. In the operation of forming the first substrate portion 100, a portion of the fourth substrate portion 400 may be formed. In the operation of forming the second substrate portion 200, another portion of the fourth substrate portion 400 may be formed. In the operation of forming the third substrate portion 300, the other portion of the fourth substrate portion 400 may be formed. A detailed description thereof will be provided below in conjunction with a method for manufacturing a printed circuit board.

[0073] The fourth substrate portion 400 may perform a heat dissipation function. The fourth insulating portion 410, the fourth wiring layer 420, and the fourth via layer 430 may be arranged so that the heat transferred through the uppermost wiring layer in the fourth-second wiring layer 422 is dissipated to the lowermost side of the printed circuit board. Figure 4B, the heat generated in the semiconductor chip 600 can be discharged to the lowermost side of the printed circuit board through the fourth substrate part 400. Since the fourth substrate part 400 is configured to perform a heat dissipation function, the printed circuit board can have improved heat dissipation characteristics without changing the internal design of the first substrate part 100, the second substrate part 200, and the third substrate part 300. Since the fourth substrate part 400 is configured to correspond to the first substrate part 100, the second substrate part 200, and the third substrate part 300, the printed circuit board can have enhanced anti-warping characteristics. In this case, the fourth substrate part 400 can perform a heat dissipation function together with the resin layer 500. In this case, the heat dissipation effect can be further improved.

[0074] The same components as those of the printed circuit board according to the example, among the components except the fourth substrate part 400 , may be applied to a printed circuit board according to another example, and thus repeated descriptions thereof will be omitted.

[0075] Figure 5A and Figure 5B is a schematic cross-sectional view showing a printed circuit board according to still another example.

[0076] Reference Figure 5A and Figure 5B In a printed circuit board according to another example, the fourth substrate portion 400 may further include a metal block 440. The metal block 440 may pass through at least a portion of the fourth insulating portion 410 to be connected to the fourth wiring layer 420, for example, the metal block 440 may pass through the fourth-second insulating portion 412 to be connected to the fourth-first wiring layer 421. The metal block 440 may include a metal material. Any material having excellent thermal conductivity may be used as the metal material without limitation. Copper (Cu) may be preferably included, but the present disclosure is not limited thereto. An alloy including the above materials may be used. The metal block 440 may have a rectangular column shape, but the present disclosure is not limited thereto, and may have various shapes, such as a cylindrical shape and a polygonal column shape. In addition, the metal block 440 may have a shape similar to a pin. The metal block 440 may be formed using plating, but the present disclosure is not necessarily limited thereto. The method for forming the metal block 440 is not limited, such as forming the metal block 440 by removing a portion of the fourth-second insulating portion 412, inserting the metal block 440 into the removed portion, and attaching the metal block 440 to the fourth-second insulating portion 412, or inserting the metal block into the fourth-second insulating portion 412 like a rivet or the like to pass through the fourth-second insulating portion 412. In addition, Figure 5A and Figure 5B It is shown that the fourth substrate portion 400 does not include the fourth-second wiring layer 422 and the fourth-second via layer 432 . However, the present disclosure is not limited thereto, and the fourth substrate portion 400 may further include the fourth-second wiring layer 422 and the fourth-second via layer 432 .

[0077] The metal block 440 can improve the heat dissipation characteristics. When the metal block 440 is disposed on the fourth substrate portion 400, the metal of the fourth substrate portion 400 that performs the heat dissipation function can have a further increased area. That is, since the metal block 440 having excellent thermal conductivity is disposed in the fourth substrate portion 400, the printed circuit board according to yet another example can have excellent heat dissipation characteristics.

[0078] The same components as those of the printed circuit board according to the example and / or the printed circuit board according to another example, except the metal block 440 of the fourth substrate portion 400 , may be applied to the printed circuit board according to yet another example, and thus repeated descriptions thereof will be omitted.

[0079] Method for manufacturing printed circuit board 6A to 6H is a schematic cross-sectional view illustrating a method for manufacturing a printed circuit board according to an example.

[0080] Reference Fig. 6A , a first substrate portion 100 may be prepared.

[0081] The first substrate portion 100 may be formed by applying any process that can be applied by a person skilled in the art without limitation. The first substrate portion 100 may be manufactured in strip units and then singulated by slicing or sawing, but the present disclosure is not necessarily limited thereto, and for example, the first substrate portion 100 may be formed separately.

[0082] Reference Figure 6B , the first substrate portion 100 can be set in the fixture J.

[0083] The jig J may be a device for fixing the first substrate portion 100. When the operation of forming the first substrate portion 100 is performed using a process of forming the first substrate portion 100 in strip units and then singulating the first substrate portion 100, the jig J may be a dummy area generated in the operation of forming the first substrate portion 100. Defect inspection is performed on the first substrate portion 100 before the operation of setting the first substrate portion 100 in the jig J, and the manufacturing operation is no longer performed on the defective first substrate portion 100. That is, the second substrate portion 200 is not formed on the defective first substrate portion 100, thereby effectively reducing costs.

[0084] The jig J may be manufactured together in the operation of forming the first substrate portion 100, and thus the jig J may include components corresponding to those of the first substrate portion 100. In the case where the jig J is not removed in the operation to be described below, the jig J may correspond to a portion of the fourth substrate portion 400. That is, the jig J may correspond to the fourth-first insulating portion 411, the fourth-first wiring layer 421, and the fourth-first via layer 431 of the fourth substrate portion 400.

[0085] The first substrate portion 100 may be combined by attaching an adhesive member T to the lower surface of the jig J. The lower surface of the first substrate portion 100 and the lower surface of the jig J may be attached and fixed by the adhesive member T, respectively. The adhesive member T may be a conventional tape, a die attach film (DAF), etc., and any device that can be used by those skilled in the art to temporarily fix components may be used without limitation. In this case, the lowermost surface of the first wiring layer 120 of the first substrate portion 100 may be attached to the adhesive member T, but the present disclosure is not limited thereto.

[0086] Reference Figure 6C , a resin layer 500 may be filled between the first substrate portion 100 and the jig J.

[0087] The resin layer 500 may be formed by filling a space between the first substrate portion 100 and the jig J with a flowable resin in an uncured state and then curing it. When the resin layer 500 is disposed between the first substrate portion 100 and the jig J and cured, the first substrate portion 100 and the jig J may be fixed by the resin layer 500. In this case, the flowable resin may be filled to cover the side surface of the first insulating portion 110 of the first substrate portion 100, and may cover the side surface of the jig J. As described above, the jig J may be a portion of the fourth substrate portion 400, that is, the resin layer 500 may cover a portion of the side surface of the fourth substrate portion 400.

[0088] The resin layer 500 may include a flowable material so that the upper surface of the resin layer 500 may be substantially coplanar with the upper surface of the first insulating portion 110. However, the present disclosure is not limited thereto, and the upper surface of the resin layer 500 may be formed to protrude further than a portion of the first insulating portion 110. The resin layer 500 may be filled to the upper surface of the adhesive member T so that the lower surface of the resin layer 500 may be substantially coplanar with the lower surface of the first wiring layer 120 of the first substrate portion 100. Although in Figure 6C Although not shown in the drawings, the resin layer 500 may be formed to fill a space between the adhesive member and the first wiring layer 120 .

[0089] Reference FIG. 6D to FIG. 6F , after removing the adhesive member T, the second substrate portion 200 and the third insulating portion 310 may be formed.

[0090] When the resin layer 500 fixes the first substrate portion 100 and the jig J, the first substrate portion 100, the resin layer 500, and the jig J are not separated from each other even if the adhesive member T is removed. The second insulating portion 210 may be formed on the first insulating portion 110, and the third insulating portion 310 may be formed on a lower surface of the first insulating portion 110.

[0091] When the second substrate part 200 is formed on the first substrate part 100, a temporary layer 320' may be additionally formed on the lower portion of the first substrate part 100 to control the warpage of the printed circuit board. Fig.6D , the warpage can be controlled by forming the third insulating portion 310 to correspond to the second insulating portion 210. Fig.6D and Fig. 6E , warpage can be controlled by forming a temporary layer 320' to correspond to the second wiring layer 220. The temporary layer 320' may be formed using plating, and may be formed using the same process as the second wiring layer 220, but the temporary layer 320' may not be patterned. Fig. 6F , the temporary layer 320' may be removed. Any method that can be used by those skilled in the art may be used as a method for removing the temporary layer 320' without limitation.

[0092] When the second substrate portion 200 is formed on the first substrate portion 100, the fourth-second insulating portion 412, the fourth-third insulating portion 413, the fourth-second wiring layer 422, and the fourth-second via layer 432 may be further formed on the jig J as needed. As described above in conjunction with the printed circuit board according to another example, the fourth substrate portion 400 may perform a heat dissipation function. Therefore, the fourth-second wiring layer 422 may be designed in the operation of forming the second substrate portion 200 so that the fourth substrate portion 400 performs a heat dissipation function.

[0093] The present disclosure is not limited thereto. In the case where the final operation includes an operation of removing the jig J, no other components may be further formed on the jig J. That is, in the case where the jig J is removed, no other components may be formed on the jig J, thereby reducing costs. In this case, the second substrate portion 200 may be disposed on the first substrate portion 100 to extend onto the resin layer 500, but may not extend onto the jig J.

[0094] When the third insulating part 310 is formed on the lower surface of the first substrate part 100 , the above description may be applied in the same manner, and thus a repeated description will be omitted.

[0095] Reference Figure 6G, a third wiring layer 320 may be formed on the third insulating portion 310, and a third via layer 330 may be formed passing through the third insulating portion 310. In addition, a solder resist layer 510 may be formed on the second insulating portion 210 and the third insulating portion 310, and an opening may be formed in the solder resist layer 510 to expose the second wiring layer 220 and the third wiring layer 320, and a surface treatment layer may be formed on the exposed second wiring layer 220 and the third wiring layer 320. Thus, a structure such as Figure 4A A printed circuit board according to another example is shown.

[0096] Reference Figure 6H , which can be accomplished by cutting along the border of the resin layer 500. Figure 3A The printed circuit board according to the example shown. In this case, the cutting surface of each unit does not need to correspond to the boundary between the resin layer 500 and the jig J, and at least a portion of the resin layer 500 may be removed together. When the jig J is retained to perform a heat dissipation function as the fourth substrate portion 400, the jig J may not be cut off.

[0097] In addition, the printed circuit board according to the example may further include conventional components of the printed circuit board. Additions or omissions may be freely made without changing the technical significance of the present disclosure.

[0098] In the present disclosure, the first substrate portion and the fourth substrate portion may refer to two areas of the board that are distinguished from each other within a single printed circuit board. That is, the first substrate portion and the fourth substrate portion may not have a clearly distinguished boundary between them, and the respective substrate portions may not need to be manufactured separately and then combined with each other.

[0099] In the present disclosure, the same insulating material may refer not only to completely the same insulating material, but also to the same type of insulating material. Therefore, the same insulating material may have substantially the same composition, but may have slightly different specific composition ratios.

[0100] In the present disclosure, a cross-sectional shape may refer to a cross-sectional shape of an object when the object is cut vertically, or may refer to a cross-sectional shape of an object when the object is viewed from a side perspective. In addition, a shape on a plane may refer to a shape of an object when the object is cut horizontally, or may refer to a plane shape of an object when the object is viewed from a top or bottom perspective.

[0101] In the present disclosure, for the sake of convenience, upper side, upper part, upper surface, etc. are used to refer to the direction toward the surface on which the electronic components can be mounted based on the cross section of the drawings, and lower side, lower part, lower surface, etc. are used to refer to the opposite direction. However, the above directions are defined for the convenience of description. Therefore, it should be understood that the scope of the claims is not particularly limited by the above directions.

[0102] As used herein, the term "connection" may refer not only to "direct connection" but also to "indirect connection" through an adhesive layer or the like. The term "electrical connection" may include both a case where components are "physically connected" and a case where components are "not physically connected". In addition, the terms "first", "second", etc. may be used to distinguish a component from another component, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of example embodiments.

[0103] As used herein, the term "example" is provided to emphasize a particular feature, structure, or characteristic, and does not necessarily refer to the same example. In addition, in one or more examples, the particular characteristics or features may be combined in any suitable manner. For example, content described in a specific example may be used in other examples even if it is not described in other examples, unless it is described as being contrary to or inconsistent with content in other examples.

[0104] The terms used herein are only used to describe specific examples, and the present disclosure is not limited thereby.As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0105] While examples have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A first substrate portion including a first insulating portion and a plurality of first wiring layers, each of the plurality of first wiring layers being disposed on or in the first insulating portion; A resin layer, arranged to cover a side surface of the first insulating portion; as well as The second substrate portion includes a second insulating portion and a second wiring layer, the second insulating portion being provided to cover each of an upper surface of the first insulating portion and an upper surface of the resin layer, and the second wiring layer being provided on or in the second insulating portion.

2. The printed circuit board according to claim 1, wherein: The wirings of the second wiring layer are finer than the wirings of the first wiring layer.

3. The printed circuit board according to claim 1, wherein: The second insulating portion covers at least a portion of the first wiring layer.

4. The printed circuit board according to claim 1, wherein: A side surface of the second insulating portion is substantially coplanar with a side surface of the resin layer.

5. The printed circuit board according to claim 1, wherein At least a portion of the second wiring layer is provided on an upper region of the resin layer.

6. The printed circuit board according to claim 1, further comprising: The third substrate portion includes a third insulating portion and a third wiring layer. The third insulating portion is provided on a lower side of the first insulating portion, and the third wiring layer is provided on or in the third insulating portion.

7. The printed circuit board according to claim 6, wherein: The third insulating portion covers a lower surface of the resin layer.

8. The printed circuit board according to claim 6, wherein: The third insulating portion includes a material substantially the same as that of the second insulating portion.

9. The printed circuit board according to claim 6, further comprising: A solder resist layer is provided on each of the second insulating portion and the third insulating portion.

10. The printed circuit board according to claim 9, wherein: A side surface of the solder resist layer is substantially coplanar with a side surface of the second insulating portion and a side surface of the resin layer.

11. The printed circuit board according to claim 6, further comprising: A fourth substrate portion includes a fourth insulating portion and a fourth wiring layer, wherein the fourth insulating portion is arranged on the side surfaces of the second insulating portion and the third insulating portion and the side surface of the resin layer, and the fourth wiring layer is arranged on or in the fourth insulating portion.

12. The printed circuit board according to claim 11, wherein The fourth insulating part includes a fourth-first insulating part and a fourth-second insulating part, The fourth-first insulating portion includes a material substantially the same as that of the first insulating portion, and The fourth-second insulating portion includes a material substantially the same as that of the second insulating portion.

13. The printed circuit board according to claim 12, wherein: The fourth wiring layer includes a fourth-first wiring layer and a fourth-second wiring layer, The density of the wirings of the fourth-first wiring layer is substantially the same as the density of the wirings of the first wiring layer, and The density of wirings of the fourth-second wiring layer is substantially the same as the density of wirings of the second wiring layer.

14. The printed circuit board according to claim 12, wherein: The fourth-second insulating portion and the second insulating portion include a plurality of insulating layers, respectively, and each insulating layer of the fourth-second insulating portion and a corresponding insulating layer of the second insulating portion are an integral insulating layer.

15. The printed circuit board according to claim 11, wherein The fourth substrate portion includes a metal block passing through at least a portion of the fourth insulating portion, the metal block being connected to the fourth wiring layer.

16. The printed circuit board according to claim 1, wherein The resin layer includes at least one of a thermal interface material, a bonding sheet, an epoxy molding compound, and a bottom filling resin.

17. A printed circuit board comprising: A first substrate portion including a first insulating portion and a first wiring layer provided on or in the first insulating portion; A resin layer, configured to cover a side surface of the first substrate portion; as well as a second substrate portion including a second insulating portion and a second wiring layer, the second insulating portion being provided on the first insulating portion and the resin layer, and the second wiring layer being provided on or in the second insulating portion, The upper surface of the resin layer is substantially coplanar with the upper surface of the first insulating portion.

18. The printed circuit board according to claim 17, wherein: The side surface of the resin layer is exposed to the outside, and A side surface of the second insulating portion is substantially coplanar with a side surface of the resin layer.

19. A printed circuit board, comprising: A first substrate portion including a first insulating portion and a first wiring layer provided on or in the first insulating portion; A resin layer, configured to cover a side surface of the first substrate portion; a second substrate portion including a second insulating portion and a second wiring layer, the second insulating portion being provided on the first insulating portion and the resin layer, and the second wiring layer being provided on or in the second insulating portion; as well as a third substrate portion including a third insulating portion and a third wiring layer, wherein the third insulating portion is provided on a lower side of the first insulating portion, and the third wiring layer is provided on or in the third insulating portion, The lower surface of the resin layer is substantially coplanar with the lower surface of the lowermost first wiring layer among the first wiring layers.

20. The printed circuit board according to claim 19, wherein The second insulating portion and the third insulating portion are in contact with the resin layer.

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