Semiconductor structure, preparation method of semiconductor structure, memory and memory system
By designing a semiconductor structure in which the gate layer extends along the circumference of the sub-active column, the problem of poor transistor control performance in the semiconductor structure is solved, and better control performance is achieved.
Patent Information
- Application Number
- CN202310956288.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-31
- Publication Date
- 2025-02-14
AI Technical Summary
The transistor control performance of semiconductor structures is poor.
A semiconductor structure is designed in which the gate layer extends along the circumference of the sub-active column to at least both sides of the sub-active column to form a vertical transistor structure to improve the positive alignment between the gate layer and the sub-active column area.
By increasing the opposite area of the channel region of the gate layer and the sub-active column, the control performance of the transistor formed by the sub-active column and the gate layer is enhanced.
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Figure CN119451087A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, a memory, and a storage system. Background Art
[0002] The semiconductor structure generally includes a memory structure, and word lines and bit lines connected to the memory structure. The memory structure includes transistors distributed in an array, the bit lines are connected to the drains of the transistors, and the word lines are connected to the gate layers of the transistors. In the process of forming the transistors of the memory structure, there are still some problems that need to be further solved. Summary of the invention
[0003] The embodiments of the present application provide a semiconductor structure, a method for preparing the semiconductor structure, a memory and a storage system, aiming to solve the problem of poor transistor control performance of the semiconductor structure.
[0004] An embodiment of the present application provides a semiconductor structure, including:
[0005] An active column, comprising two sub-active columns extending along a first direction, wherein the two sub-active columns are arranged relatively spaced apart along a second direction, and the first direction and the second direction form an angle;
[0006] A first dielectric layer is provided on the outer peripheral surfaces of the two sub-active pillars which are away from each other;
[0007] A gate layer is arranged on a side of the first dielectric layer away from the sub-active column, and the gate layer extends along the circumference of the sub-active column; at least a portion of the surface of the gate layer facing the sub-active column is a concave surface, and at least a portion of the surface of the sub-active column facing the gate layer is a convex surface.
[0008] In some embodiments, the semiconductor structure layer further includes an isolation layer, and the isolation layer is located between the two sub-active pillars.
[0009] In some embodiments, the first dielectric layer contacts the isolation layer in a circumferential direction of the sub-active pillar; and the gate layer contacts the isolation layer in a circumferential direction of the sub-active pillar.
[0010] In some embodiments, the sub-active pillar includes a channel region, and a source and a drain distributed at two ends of the channel region along the first direction, and the gate layer extends circumferentially along the sub-active pillar to at least two sides of the channel region.
[0011] In some embodiments, the semiconductor structure includes a plurality of active pillars, and the plurality of active pillars are arranged in an array.
[0012] In some embodiments, the semiconductor structure includes a bit line extending along the second direction, and the sub-active pillars of the plurality of active pillars arranged along the second direction are respectively connected to the bit line.
[0013] In some embodiments, the gate layers opposite to the plurality of sub-active pillars arranged along a third direction are sequentially connected to form a word line, and the first direction and the second direction respectively form an angle with the third direction.
[0014] In some embodiments, the word line includes a connecting portion connected between two adjacent gate layers, and the connecting portion is disposed on a side surface of the isolation layer along the second direction.
[0015] In some embodiments, a surface of the gate layer facing the sub-active pillar is a curved surface.
[0016] In some embodiments, the surface of the gate layer facing the sub-active pillar includes a plurality of planes, the plurality of planes are sequentially distributed along the circumference of the sub-active pillar, and an angle is formed between two adjacent planes.
[0017] The present application also provides a method for preparing a semiconductor structure, the method comprising:
[0018] providing a substrate;
[0019] An active column is formed on the substrate, wherein the active column comprises two sub-active columns extending along a first direction, the two sub-active columns are arranged relatively spaced apart along a second direction, and the first direction and the second direction form an angle;
[0020] Forming first dielectric layers respectively on the outer peripheral surfaces of the two sub-active pillars which are away from each other;
[0021] A gate layer is formed on a side of the first dielectric layer away from the sub-active pillar, and the gate layer extends along a circumferential direction of the sub-active pillar to at least two sides of the sub-active pillar.
[0022] In some embodiments, forming an active pillar on the substrate includes:
[0023] forming an active pillar extending along the first direction on the substrate;
[0024] A groove is formed in the active column, and the groove penetrates the active column along a third direction to separate the active column into two sub-active columns extending along the first direction, and the two sub-active columns are arranged relatively spaced along a second direction, and the first direction and the second direction respectively form an angle with the third direction.
[0025] In some embodiments, forming an active pillar on the substrate further includes: filling an insulating material in the trench to form an isolation layer.
[0026] In some embodiments, before forming the trenches in the active pillars, the method further includes:
[0027] A second dielectric layer is formed on the substrate and filled around the active pillar.
[0028] In some embodiments, before forming the first dielectric layer on the outer peripheral surfaces of the two sub-active pillars which are away from each other, the method further includes:
[0029] The second dielectric layer is removed.
[0030] In some embodiments, the method further comprises:
[0031] A source and a drain are respectively formed at two ends of the sub-active pillar along the first direction, and a portion of the sub-active pillar between the source and the drain is a channel region.
[0032] In some embodiments, forming a gate layer on a side of the first dielectric layer away from the sub-active pillar includes:
[0033] forming metal layers respectively on a surface of the first dielectric layer facing away from the sub-active pillar, a side surface of the isolation layer along the second direction, and a surface of the substrate;
[0034] The portion of the metal layer opposite to the outer peripheral surface of the source electrode, the portion of the metal layer opposite to the outer peripheral surface of the drain electrode, and the portion of the metal layer located on the surface of the substrate are removed to form the gate layer.
[0035] In some embodiments, removing the portion of the metal layer opposite to the outer peripheral surface of the source electrode, the portion of the metal layer opposite to the outer peripheral surface of the drain electrode, and the portion of the metal layer located on the surface of the substrate to form the gate layer includes:
[0036] removing a portion of the metal layer that is opposite to the outer peripheral surface of the drain electrode;
[0037] removing the substrate;
[0038] The portion of the metal layer located on the surface of the substrate and the portion of the metal layer opposite to the outer peripheral surface of the source electrode are removed to form the gate layer.
[0039] In some embodiments, removing the portion of the metal layer opposite to the outer peripheral surface of the source electrode, the portion of the metal layer opposite to the outer peripheral surface of the drain electrode, and the portion of the metal layer located on the surface of the substrate to form the gate layer includes:
[0040] removing the portion of the metal layer opposite to the outer peripheral surface of the drain electrode and the portion of the metal layer located on the surface of the substrate;
[0041] removing the substrate;
[0042] The portion of the metal layer opposite to the outer peripheral surface of the source electrode is removed to form the gate layer.
[0043] In some embodiments, forming a source and a drain at two ends of the sub-active pillar along the first direction respectively includes:
[0044] Ion implantation is performed at two ends of the sub-active pillar along the first direction to form the source and the drain at two ends of the sub-active pillar along the first direction.
[0045] The embodiment of the present application further provides a memory, the memory comprising the semiconductor structure as described above, the semiconductor structure comprising:
[0046] An active column, comprising two sub-active columns extending along a first direction, wherein the two sub-active columns are arranged relatively spaced apart along a second direction, and the first direction and the second direction form an angle;
[0047] A first dielectric layer is provided on the outer peripheral surfaces of the two sub-active pillars which are away from each other;
[0048] The gate layer is disposed on a side of the first dielectric layer away from the sub-active pillar, and the gate layer extends along the circumference of the sub-active pillar to at least two sides of the sub-active pillar.
[0049] The present application also provides a storage system, the storage system comprising:
[0050] A memory as described above; and
[0051] A controller is connected to the memory, and is used to control the memory to store data.
[0052] The semiconductor structure provided in the embodiment of the present application can increase the facing area of the gate layer and the channel region of the sub-active pillar by extending the gate layer along the circumferential direction of the sub-active pillar to at least two sides of the sub-active pillar, so that the transistor formed by the sub-active pillar and the gate layer has better control performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.
[0054] Figure 1A top view of a schematic structural diagram of an embodiment of a semiconductor structure provided in an embodiment of the present application;
[0055] Figure 2 A three-dimensional structural view of a transistor structure of a semiconductor structure provided by an embodiment of the present application;
[0056] Figure 3 A flowchart of an embodiment of a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0057] Figures 4 to 13 A schematic diagram of a three-dimensional structure after different structural layers are formed during the preparation process of the semiconductor structure provided in an embodiment of the present application;
[0058] Fig.14 A top view of a structural schematic diagram of another embodiment of a semiconductor structure provided in an embodiment of the present application;
[0059] Fig.15 A schematic diagram of the structure of an embodiment of a storage system provided in an embodiment of the present application;
[0060] Fig.16 A schematic diagram of the structure of an embodiment of an electronic device provided in an embodiment of the present application.
[0061] Storage system 1; memory 10; host 20; controller 30; central processing unit 2; electronic device 3; semiconductor structure 100; substrate 110; second dielectric layer 122; active pillar 123; sub-active pillar 1231; channel region 1232; source 1233; drain 1234; side 1235; groove 124; isolation layer 125; first dielectric layer 126; gate layer 127; connection portion 1271; plane 1272; metal layer 128; metal portion 1281; word line 210; bit line 220. DETAILED DESCRIPTION
[0062] The technical solutions in the present disclosure will be described clearly and completely below in conjunction with the drawings in the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.
[0063] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present disclosure.
[0064] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.
[0065] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.
[0066] The embodiments of the present application provide a semiconductor structure, a method for manufacturing the semiconductor structure, a memory, and a storage system, which are described in detail below.
[0067] First, an embodiment of the present application provides a semiconductor structure.
[0068] Figure 1 A top view of a schematic structural diagram of an embodiment of a semiconductor structure provided in an embodiment of the present application; Figure 2 A three-dimensional structural view of a transistor structure of a semiconductor structure provided in an embodiment of the present application. Figure 1 and Figure 2 As shown, the semiconductor structure 100 includes an active column 123, a first dielectric layer 126 and a gate layer 127, the active column 123 includes two sub-active columns 1231 extending along a first direction Z, the two sub-active columns 1231 are arranged relatively spaced along a second direction X, and the first direction Z forms an angle with the second direction X. The angle formed by the first direction Z and the second direction X can be a right angle or an acute angle. The first dielectric layer 126 is arranged on the outer peripheral surfaces of the two sub-active columns 1231 that are separated from each other. The gate layer 127 is arranged on the side of the first dielectric layer 126 that is opposite to the ion active column 1231, thereby, the gate layer 127 and the active column 123 can form a vertical transistor structure.
[0069] Specifically, Fig. 9As shown, the sub-active pillar 1231 includes a channel region 1232, and a source 1233 and a drain 1234 distributed at both ends of the channel region 1232 along the first direction Z, and the gate layer 127 is arranged opposite to the channel region 1232 of the sub-active pillar 1231. The material of the two sub-active pillars 1231 of the active pillar 123 may include silicon (Si) or other semiconductor materials, which is not limited here.
[0070] In some embodiments, the gate layer 127 of the semiconductor structure 100 extends along the circumference of the sub-active pillar 1231, and at least a portion of the surface of the gate layer 127 facing the sub-active pillar 1231 is a concave surface, and at least a portion of the surface of the sub-active pillar 1231 facing the gate layer 127 is a convex surface. Thus, the area of the gate layer 127 facing the channel region 1232 of the sub-active pillar 1231 can be increased, so that the vertical transistor formed by the sub-active pillar 1231 and the gate layer 127 has better control performance.
[0071] It should be noted that a portion of the surface of the gate layer 127 facing the sub-active pillar 1231 may be a concave surface, or the entire surface of the gate layer 127 facing the sub-active pillar 1231 may be a concave surface. The concave surface of the gate layer 127 facing the sub-active pillar 1231 may be a curved surface, an arcuate surface, a concave surface composed of multiple planes, or other irregular concave surfaces, as long as the area facing the channel region 1232 of the sub-active pillar 1231 can be increased.
[0072] Similarly, a part of the surface of the sub-active pillar 1231 facing the gate layer 127 can be a convex surface, or the entire surface of the sub-active pillar 1231 facing the gate layer 127 can be a convex surface. The concave surface of the sub-active pillar 1231 facing the gate layer 127 can be a curved surface, an arc-shaped surface, a convex surface composed of multiple planes, or other irregular convex surfaces, as long as the area facing the gate layer 127 and the channel region 1232 of the sub-active pillar 1231 can be increased.
[0073] Specifically, Figure 2 As shown, the gate layer 127 is disposed opposite to the channel region 1232 of the sub-active pillar 1231 and extends circumferentially along the sub-active pillar 1231. At least a portion of the surface of the gate layer 127 facing the channel region 1232 is a concave surface. Fig. 9 As shown, at least a portion of the surface of the channel region 1232 facing the gate layer 127 is convex, so that the gate layer 127 and the channel region 1232 of the sub-active pillar 1231 have a larger facing area.
[0074] In some embodiments, Figure 1 and Figure 2As shown, the semiconductor structure 100 further includes an isolation layer 125, which is located between two sub-active pillars 1231 of the active pillar 123. The isolation layer 125 can isolate the two sub-active pillars 1231 of the active pillar 123 to prevent interference between the two active pillars 123. At the same time, the isolation layer 125 can also support the sub-active pillars 1231 to a certain extent. The material of the isolation layer 125 can be silicon nitride (SiN) or other insulating materials, which is not limited here.
[0075] The gate layer 127 can be in contact with the isolation layer 125 in the circumferential direction of the sub-active pillar 1231 , thereby increasing the length of the gate layer 127 in the circumferential direction of the sub-active pillar 1231 , thereby further increasing the facing area between the gate layer 127 and the channel region 1232 of the sub-active pillar 1231 .
[0076] In the circumferential direction of the sub-active pillar 1231, the first dielectric layer 126 can be in contact with the isolation layer 125. Alternatively, the first dielectric layer 126 can be separated from the isolation layer 125. Of course, the former can better keep the gate layer 127 and the sub-active pillar 1231 in an isolated state, and prevent the gate layer 127 from contacting the sub-active pillar 1231 through the gap between the first dielectric layer 126 and the isolation layer 125.
[0077] It should be noted that the two gate layers 127 on both sides of the active pillar 123 along the second direction X can be extended to the isolation layer 125 along the circumferential direction of the sub-active pillar 1231 and contact the isolation layer 125. Alternatively, one gate layer 127 on one side of the active pillar 123 along the second direction X can be extended to the isolation layer 125 along the circumferential direction of the sub-active pillar 1231 and contact the isolation layer 125. Of course, the former can improve the control performance of each transistor.
[0078] In some embodiments, the surface of the gate layer 127 of the semiconductor structure 100 facing the sub-active pillar 1231 may be curved so that the gate layer 127 and the channel region 1232 of the sub-active pillar 1231 have more facing areas.
[0079] The outer peripheral surfaces of the two sub-active pillars 1231 of the active pillar 123 that are away from each other are curved surfaces. After the first dielectric layer 126 and the gate layer 127 are formed on the outer peripheral surfaces of the sub-active pillars 1231, the surface of the gate layer 127 facing the sub-active pillars 1231 is a curved surface. The outer peripheral surfaces of the two sub-active pillars 1231 of the active pillar 123 that are away from each other are convex curved surfaces, and the surface of the gate layer 127 facing the sub-active pillars 1231 is a concave curved surface. Of course, the outer peripheral surfaces of the two sub-active pillars 1231 of the active pillar 123 that are away from each other may also include concave curved surfaces, and the surface of the gate layer 127 facing the sub-active pillars 1231 may include convex curved surfaces.
[0080] Specifically, the outer peripheral surfaces of the two sub-active pillars 1231 of the active pillar 123 facing each other are arc-shaped surfaces, and the generatrix of the arc-shaped surfaces extends along the first direction Z. The surface of the gate layer 127 facing the sub-active pillars 1231 is an arc-shaped surface, and the generatrix of the arc-shaped surface extends along the first direction Z.
[0081] In other embodiments, Fig.14 As shown, the surface of the gate layer 127 of the semiconductor structure 100 facing the sub-active pillar 1231 may also include a plurality of planes 1272, and the plurality of planes of the gate layer 127 are sequentially distributed along the circumference of the sub-active pillar 1231, and an angle is formed between two adjacent planes 1272, so that the gate layer 127 and the channel region 1232 of the sub-active pillar 1231 have more facing area.
[0082] Specifically, the sub-active pillar 1231 is a polygonal pillar, and the multiple side surfaces 1235 of the sub-active pillar 1231 are respectively planes, and are sequentially connected along the circumference of the sub-active pillar 1231. One side surface 1235 of the sub-active pillar 1231 is in contact with the isolation layer 125, and the other side surfaces 1235 of the sub-active pillar 1231 are respectively opposite to the gate layer 127. Correspondingly, the gate layer 127 includes a plurality of planes 1272 that are opposite to the multiple side surfaces 1235 of the sub-active pillar 1231 one by one, and the plurality of planes 1272 are sequentially connected along the circumference of the sub-active pillar 1231, and two adjacent planes 1272 of the gate layer 127 are arranged at an angle. Among them, the angle formed by two adjacent planes 1272 of the gate layer 127 can be an acute angle, a right angle, or an obtuse angle.
[0083] In some embodiments, Figure 1 and Figure 2 As shown, the semiconductor structure 100 includes a plurality of active pillars 123, and the plurality of active pillars 123 are arranged in an array. Specifically, the plurality of active pillars 123 of the semiconductor structure 100 are arranged in an array along the second direction X and the third direction Y. That is, the semiconductor structure 100 includes a plurality of rows of active pillars 123 sequentially distributed along the second direction X, and a plurality of active pillars 123 in each row of active pillars 123 are sequentially arranged along the third direction Y; and / or, the semiconductor structure 100 includes a plurality of rows of active pillars 123 sequentially distributed along the third direction Y, and a plurality of active pillars 123 in each row of active pillars 123 are sequentially distributed along the second direction X. The two sub-active pillars 1231 of each active pillar 123 are sequentially distributed along the second direction X.
[0084] like Figure 1As shown, the semiconductor structure 100 includes a bit line 220 extending along a second direction X, and the sub-active pillars 1231 of the plurality of active pillars 123 arranged along the second direction X are respectively connected to the bit line 220. Specifically, the drains 1234 of the sub-active pillars 1231 of the plurality of active pillars 123 arranged in the same row along the second direction X are respectively connected to the same bit line 220. In addition, the gate layers 127 opposite to the plurality of sub-active pillars 1231 arranged along the third direction Y are sequentially connected to form a word line 210. The voltage applied by the word line 210 controls the conduction or cutoff between the source 1233 and the drain 1234 of the sub-active pillar 1231, and the bit line 220 is used to perform a read or write operation on the transistor when the source 1233 and the drain 1234 of the sub-active pillar 1231 are conducted.
[0085] In some embodiments, the word line 210 includes a connection portion 1271 connected between two adjacent gate layers 127 , and the connection portion 1271 is disposed on the side of the isolation layer 125 along the second direction X. Thus, the connection portion 1271 can be formed simultaneously during the process of forming the gate layer 127 , so that the process of forming the word line 210 is simpler.
[0086] In order to better manufacture the semiconductor structure in the embodiment of the present application, the embodiment of the present application also provides a method for manufacturing the semiconductor structure, such as Figure 3 As shown, the method includes steps S110 to S140, which are described in detail as follows:
[0087] S110 , providing a substrate 110 .
[0088] like Figure 4 As shown, the substrate 110 is a base for forming the semiconductor structure 100. In some embodiments, the substrate 110 may be made of silicon (Si) or other semiconductor materials.
[0089] S120 , forming an active pillar 123 on the substrate 110 , the active pillar 123 including two sub-active pillars 1231 extending along the first direction Z, the two sub-active pillars 1231 being arranged relatively spaced apart along the second direction X, and the first direction Z and the second direction X forming an angle.
[0090] The active pillar 123 extending along the first direction Z can be formed on the substrate 110 by shallow trench isolation (STI) technology. Then, the active pillar 123 is etched to divide the active pillar 123 into two sub-active pillars 1231 extending along the first direction Z (eg, Figure 7 As shown in FIG. 1 , two sub-active pillars 1231 of the active pillar 123 are arranged relatively spaced apart along the second direction X. The first direction Z is arranged at an angle to the substrate 110. The first direction Z is at an angle to the second direction X.
[0091] In some embodiments, the step of forming the active pillar 123 on the substrate 110 may include step S121 and step S122, which are described in detail as follows:
[0092] S121 , forming active pillars 123 extending along a first direction Z on the substrate 110 .
[0093] like Figure 4 As shown, the cross-sectional shape of the active pillar 123 in the direction perpendicular to the first direction Z may be circular, elliptical, rectangular, polygonal, etc.
[0094] S122, forming a groove 124 in the active pillar 123, wherein the groove 124 penetrates the active pillar 123 along the third direction Y to separate the active pillar 123 into two sub-active pillars 1231 extending along the first direction Z, and the two sub-active pillars 1231 are arranged relatively spaced along the second direction X, and the first direction Z and the second direction X form an angle with the third direction Y respectively.
[0095] Among them, Figure 6 As shown, the active pillar 123 can be etched from the semiconductor structure 100 along the side of the active pillar 123 away from the substrate 110 to form a groove 124 in the active pillar 123. The groove 124 penetrates the active pillar 123 along the third direction Y, and the groove 124 extends from one end of the active pillar 123 away from the substrate 110 to the substrate 110, thereby separating the active pillar 123 into two sub-active pillars 1231 extending along the first direction Z.
[0096] In some embodiments, Figure 7 As shown, the step of forming the active pillar 123 on the substrate 110 may further include: filling the trench 124 with an insulating material to form an isolation layer 125. By filling the trench 124 of the active pillar 123 with the isolation layer 125, the two sub-active pillars 1231 of the active pillar 123 can be better isolated, and the active pillar 123 can be supported to a certain extent.
[0097] In some embodiments, Figure 5 As shown, before the step of forming the groove 124 in the active pillar 123, the method for preparing the semiconductor structure may further include: forming a second dielectric layer 122 on the substrate 110 to fill the active pillar 123 around, so as to support the active pillar 123 and facilitate etching the groove 124 in the active pillar 123 to form two sub-active pillars 1231. The material of the second dielectric layer 122 may be silicon dioxide (SiO2) or other insulating materials, which is not limited here.
[0098] In some embodiments, Figure 8As shown, the method for preparing the semiconductor structure further includes: forming a source 1233 and a drain 1234 at both ends of the sub-active pillar 1231 along the first direction Z, respectively, and the portion of the sub-active pillar 1231 between the source 1233 and the drain 1234 is a channel region 1232 .
[0099] Ion implantation may be performed at both ends of the sub-active pillar 1231 along the first direction Z, so as to form a source 1233 and a drain 1234 at both ends of the sub-active pillar 1231 along the first direction Z. By performing ion implantation on both ends of the sub-active pillar 1231 along the first direction Z, both ends of the sub-active pillar 1231 along the first direction Z can be made into a conductive structure, so that the source 1233 and the drain 1234 are formed at both ends of the sub-active pillar 1231 along the first direction Z.
[0100] S130 , forming first dielectric layers 126 on outer peripheral surfaces of two sub-active pillars 1231 that are away from each other.
[0101] like Fig.10 As shown, the height of the first dielectric layer 126 in the first direction Z is the same as the height of the sub-active pillar 1231 in the first direction Z. Among them, a layer of insulating material can be formed on the surfaces of the two sub-active pillars 1231 of the sub-active pillar 123, the surface of the isolation layer 125, and the surface of the substrate 110, and then the portion of the insulating material layer located on the surface of the isolation layer 125 and the portion of the insulating material layer located on the surface of the substrate 110 are etched to form the first dielectric layer 126 on the outer peripheral surfaces of the two sub-active pillars 1231 of the active pillar 123 that are separated from each other. The material of the first dielectric layer 126 may include silicon dioxide (SiO2) or other insulating materials, which are not limited here.
[0102] In some embodiments, before forming the first dielectric layer 126 on the mutually opposite outer surfaces of the two sub-active pillars 1231 , the method for preparing the semiconductor structure further includes: removing the second dielectric layer 122 to facilitate forming the first dielectric layer 126 and the gate layer 127 on the outer surface of the active pillar 123 .
[0103] S140 , forming a gate layer 127 on one side of the first dielectric layer 126 behind the sub-active pillar 1231 , wherein the gate layer 127 extends along the circumference of the sub-active pillar 1231 to at least two sides of the sub-active pillar 1231 .
[0104] The method for preparing the semiconductor structure provided in the embodiment of the present application can increase the facing area of the gate layer 127 and the channel region 1232 of the sub-active pillar 1231 by extending the gate layer 127 along the circumferential direction of the sub-active pillar 1231 to at least two sides of the sub-active pillar 1231, so that the vertical transistor formed by the sub-active pillar 1231 and the gate layer 127 has better control performance.
[0105] In some embodiments, the step of forming the gate layer 127 on the side of the first dielectric layer 126 facing the ion active pillar 1231 may include step S141 and step S142, which are described in detail as follows:
[0106] S141 , forming a metal layer 128 on a surface of the first dielectric layer 126 on a side facing away from the ion active pillar 1231 , a side surface of the isolation layer 125 along the second direction X, and a surface of the substrate 110 .
[0107] like Fig.10 As shown, a metal layer 128 can be formed by deposition on the surface of the first dielectric layer 126 on the side of the back ion active column 1231, the side of the isolation layer 125 along the second direction X, and the surface of the substrate 110. The material of the metal layer 128 may include tungsten (W) or other metals, which are not limited here.
[0108] S142 , removing the portion of the metal layer 128 opposite to the outer peripheral surface of the source 1233 , the portion of the metal layer 128 opposite to the outer peripheral surface of the drain 1234 , and the portion of the metal layer 128 located on the surface of the substrate 110 to form a gate layer 127 .
[0109] The portion of the metal layer 128 opposite to the outer peripheral surface of the source 1233 , the portion of the metal layer 128 opposite to the outer peripheral surface of the drain 1234 , and the portion of the metal layer 128 located on the surface of the substrate 110 are removed through an etching process, and the remaining metal layer 128 is the gate layer 127 opposite to the channel region 1232 of the sub-active pillar 1231 .
[0110] The portion of the metal layer 128 located on the side of the isolation layer 125 along the second direction X can connect two adjacent gate layers 127 along the third direction Y, so that the gate layers 127 opposite to the plurality of sub-active pillars 1231 arranged along the third direction Y are connected in sequence to form a word line 210.
[0111] Specifically, Fig.10 , Fig.11 and Fig.13 As shown, the metal layer 128 includes a metal portion 1281 located on the surface of the substrate 110. The step of removing the portion of the metal layer 128 opposite to the outer peripheral surface of the source 1233, the portion of the metal layer 128 opposite to the outer peripheral surface of the drain 1234, and the portion of the metal layer 128 located on the surface of the substrate 110 to form the gate layer 127 may include step S1421 to step S1423, which are described in detail as follows:
[0112] S1421 , removing the portion of the metal layer 128 that is opposite to the outer peripheral surface of the drain electrode 1234 .
[0113] Among them, Fig.11As shown, the metal layer 128 may be etched from a side of the active pillar 123 away from the substrate 110 to remove a portion of the metal layer 128 opposite to the outer peripheral surface of the drain electrode 1234 .
[0114] S1422, remove the substrate 110.
[0115] The side of the substrate 110 away from the active pillar 123 may be polished by chemical mechanical polishing (CMP) to remove the substrate 110. Fig.12 As shown, after the substrate 110 is removed, the metal portion 1281 of the metal layer 128 still remains.
[0116] S1423 , removing the metal portion 1281 and the portion of the metal layer 128 that is opposite to the outer peripheral surface of the source 1233 to form a gate layer 127 .
[0117] Among them, the metal part 1281 of the metal layer 128 and the part of the metal layer 128 opposite to the outer peripheral surface of the source 1233 can be etched through an etching process to remove the metal part 1281 of the metal layer 128 and the part of the metal layer 128 opposite to the outer peripheral surface of the source 1233, thereby forming a gate layer 127 opposite to the channel region 1232 between the source 1233 and the drain 1234.
[0118] In other embodiments, the step of removing the portion of the metal layer 128 opposite to the outer peripheral surface of the source 1233, the portion of the metal layer 128 opposite to the outer peripheral surface of the drain 1234, and the portion of the metal layer 128 located on the surface of the substrate 110 to form the gate layer 127 includes step S1424 and step S1426, which are described in detail as follows:
[0119] S1424, the portion of the metal layer 128 opposite to the outer peripheral surface of the drain 1234 and the metal layer 128 are located on the substrate
[0120] 110 Partial removal of the surface.
[0121] The metal layer 128 can be etched from the side of the active pillar 123 away from the substrate 110 to remove the portion of the metal layer 128 opposite to the outer peripheral surface of the drain electrode 1234 and the portion of the metal layer 128 located on the surface of the substrate 110, so as to form Fig.13 The structure shown.
[0122] S1425, removing the substrate 110.
[0123] The substrate 110 may be removed by a back thinning process.
[0124] S1426 , removing the portion of the metal layer 128 that is opposite to the outer peripheral surface of the source electrode 1233 to form a gate layer 127 .
[0125] After removing the substrate 110 and the portion of the metal layer 128 located on the surface of the substrate 110, the metal layer 128 can be etched from the side of the active pillar 123 close to the substrate 110 to remove the portion of the metal layer 128 opposite to the outer peripheral surface of the source electrode 1233. The remaining metal layer 128 is as follows: Figure 2 The gate layer 127 is shown opposite to the channel region 1232 .
[0126] An embodiment of the present application also provides a memory, which includes a semiconductor structure. The specific structure of the semiconductor structure refers to the above embodiment. Since the present memory adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.
[0127] See also Fig.15 The embodiment of the present application also provides a storage system 1, which includes a controller 30 and a memory 10. The controller 30 is connected to the memory 10 and is used to control the memory 10 to store data; wherein the memory 10 includes the semiconductor structure 100 in any of the above embodiments.
[0128] The semiconductor structure 100 may be an array wafer memory device, or a device combined with a CMOS (complementary metal oxide semiconductor) peripheral circuit.
[0129] Specifically, the semiconductor structure 100 can be stacked with the peripheral circuit or staggered with the peripheral circuit, which is not limited in the present application. The peripheral circuit is electrically connected to the semiconductor structure 100 to transmit signals to the semiconductor structure 100. The peripheral circuit can be used for logical operations and to control and detect the switching state of each storage unit in the semiconductor structure 100 through metal wiring to achieve data storage and reading.
[0130] Specifically, the above-mentioned memory 10 can be specifically a three-dimensional DRAM memory. Without violating the disclosure or teachings of this application, the memory 10 can also be other various types of volatile memories such as a dependent data memory that serves as a temporary storage medium for an operating system or other running programs (which can be called system memory).
[0131] The controller 30 may control the memory 10 through the channel CH, and the memory 10 may perform an operation based on the control of the controller 30 in response to a request from the host 20. The memory 10 may receive a command CMD and an address ADDR from the controller 30 through the channel CH and access an area selected from the memory cell array in response to the address. In other words, the memory 10 may perform an internal operation corresponding to the command on the area selected by the address.
[0132] In some embodiments, the storage system 1 may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), an eMCP, an MCP, a secure digital card in the form of SD, mini SD and micro SD, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.
[0133] Specifically, the storage system 1 can be used in terminal products such as computers, televisions, set-top boxes, and vehicles.
[0134] See also Fig.16 The embodiment of the present application also provides an electronic device 3, which includes a central processing unit 2 and the above-mentioned storage system 1 provided in the embodiment of the present application. Specifically, the electronic device 3 can be any device that can store data, such as a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, etc.
[0135] The central processing unit 2 is used to exchange information and data with the storage system 1 .
[0136] An electronic device provided in an embodiment of the present application has the same beneficial effects as the above-mentioned storage system due to the provision of the storage system provided in an embodiment of the present application.
[0137] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0138] The semiconductor structure, the method for preparing the semiconductor structure, the memory and the storage system provided in the embodiments of the present application are introduced in detail above. The principles and implementation methods of the present application are explained in this article by using specific examples. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor structure, characterized in that: include: An active column, comprising two sub-active columns extending along a first direction, wherein the two sub-active columns are arranged relatively spaced apart along a second direction, and the first direction and the second direction form an angle; A first dielectric layer is provided on the outer peripheral surfaces of the two sub-active pillars which are away from each other; A gate layer is arranged on a side of the first dielectric layer away from the sub-active column, and the gate layer extends along the circumference of the sub-active column; at least a portion of the surface of the gate layer facing the sub-active column is a concave surface, and at least a portion of the surface of the sub-active column facing the gate layer is a convex surface.
2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes an isolation layer, and the isolation layer is located between the two sub-active pillars.
3. The semiconductor structure according to claim 2, wherein: In a circumferential direction of the sub-active pillar, the first dielectric layer contacts the isolation layer; in a circumferential direction of the sub-active pillar, the gate layer contacts the isolation layer.
4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The sub-active pillar includes a channel region, and a source and a drain distributed at two ends of the channel region along the first direction. The gate layer is arranged opposite to the channel region and extends to at least two sides of the channel region along the circumference of the sub-active pillar.
5. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure includes a plurality of active pillars, and the plurality of active pillars are arranged in an array.
6. The semiconductor structure according to claim 5, characterized in that The semiconductor structure includes a bit line extending along the second direction, and the sub-active pillars of the plurality of active pillars arranged along the second direction are respectively connected to the bit line.
7. The semiconductor structure according to claim 5, characterized in that The gate layers opposite to the plurality of sub-active pillars arranged along a third direction are connected in sequence to form a word line, and the first direction and the second direction form an angle with the third direction respectively.
8. The semiconductor structure according to claim 7, wherein: The word line includes a connecting portion connected between two adjacent gate layers, and the connecting portion is arranged on a side surface of the isolation layer along the second direction.
9. The semiconductor structure according to any one of claims 1 to 3, characterized in that: A surface of the gate layer facing the sub-active pillar is a curved surface.
10. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The surface of the gate layer facing the sub-active pillar includes a plurality of planes, the plurality of planes are sequentially distributed along the circumference of the sub-active pillar, and an angle is formed between two adjacent planes.
11. A method for preparing a semiconductor structure, characterized in that: The method comprises: providing a substrate; An active column is formed on the substrate, wherein the active column comprises two sub-active columns extending along a first direction, the two sub-active columns are arranged relatively spaced apart along a second direction, and the first direction and the second direction form an angle; Forming first dielectric layers respectively on the outer peripheral surfaces of the two sub-active pillars which are away from each other; A gate layer is formed on a side of the first dielectric layer away from the sub-active pillar, and the gate layer extends along a circumferential direction of the sub-active pillar to at least two sides of the sub-active pillar.
12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The step of forming an active column on the substrate comprises: forming an active pillar extending along the first direction on the substrate; A groove is formed in the active column, and the groove penetrates the active column along a third direction to separate the active column into two sub-active columns extending along the first direction, and the two sub-active columns are arranged relatively spaced along a second direction, and the first direction and the second direction respectively form an angle with the third direction.
13. The method for preparing a semiconductor structure according to claim 12, wherein: The method of forming an active pillar on the substrate further includes: filling the trench with an insulating material to form an isolation layer.
14. The method for preparing a semiconductor structure according to claim 13, characterized in that: Before forming the trenches in the active pillars, the method further comprises: A second dielectric layer is formed on the substrate and filled around the active pillar.
15. The method for preparing a semiconductor structure according to claim 14, characterized in that: Before forming the first dielectric layer on the outer peripheral surfaces of the two sub-active pillars which are away from each other, the method further includes: The second dielectric layer is removed.
16. The method for preparing a semiconductor structure according to claim 13, wherein: The method further comprises: A source and a drain are respectively formed at two ends of the sub-active pillar along the first direction, and a portion of the sub-active pillar between the source and the drain is a channel region.
17. The method for preparing a semiconductor structure according to claim 16, wherein: Forming a gate layer on a side of the first dielectric layer away from the sub-active pillar, comprising: forming metal layers respectively on a surface of the first dielectric layer facing away from the sub-active pillar, a side surface of the isolation layer along the second direction, and a surface of the substrate; The portion of the metal layer opposite to the outer peripheral surface of the source electrode, the portion of the metal layer opposite to the outer peripheral surface of the drain electrode, and the portion of the metal layer located on the surface of the substrate are removed to form the gate layer.
18. The method for preparing a semiconductor structure according to claim 17, characterized in that: The metal layer includes a metal portion located on the surface of the substrate; the portion of the metal layer opposite to the outer peripheral surface of the source electrode, the portion of the metal layer opposite to the outer peripheral surface of the drain electrode, and the portion of the metal layer located on the surface of the substrate are removed to form the gate layer, comprising: removing a portion of the metal layer that is opposite to the outer peripheral surface of the drain electrode; removing the substrate; The metal portion and the portion of the metal layer that is opposite to the outer peripheral surface of the source electrode are removed to form the gate layer.
19. The method for preparing a semiconductor structure according to claim 17, wherein: The step of removing the portion of the metal layer opposite to the outer peripheral surface of the source electrode, the portion of the metal layer opposite to the outer peripheral surface of the drain electrode, and the portion of the metal layer located on the surface of the substrate to form the gate layer comprises: removing the portion of the metal layer opposite to the outer peripheral surface of the drain electrode and the portion of the metal layer located on the surface of the substrate; removing the substrate; The portion of the metal layer opposite to the outer peripheral surface of the source electrode is removed to form the gate layer.
20. The method for preparing a semiconductor structure according to claim 16, wherein: The step of forming a source and a drain at two ends of the sub-active column along the first direction respectively comprises: Ion implantation is performed at two ends of the sub-active pillar along the first direction to form the source and the drain at two ends of the sub-active pillar along the first direction.
21. A memory, characterized in that: The memory comprises the semiconductor structure according to any one of claims 1 to 10.
22. A storage system, characterized in that: The storage system comprises: The memory as claimed in claim 21; and A controller is connected to the memory, and is used to control the memory to store data.