Memory cell structure, memory cell array structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a memory cell structure, a memory cell array structure and a manufacturing method thereof.The memory cell structure comprises a grid electrode extending in the first direction, the grid electrode is provided with a first face and a second face which are opposite, and the second face is provided with a first concave face and a second concave face which are arranged at intervals; the first concave surface and the second concave surface are both concave towards the first surface; the gate dielectric layer at least covers the second surface in a shape-preserving manner; the semiconductor layer covers the side, away from the grid electrode, of the grid dielectric layer in a shape-preserving mode, the semiconductor layer is provided with a contact face right opposite to the second face, and the contact face is provided with a third concave face corresponding to the first concave face and a fourth concave face corresponding to the second concave face; comprising a lower electrode layer, an upper electrode layer and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer, and the lower electrode layer is in contact connection with the third concave surface; the bit line structure is in contact connection with the fourth recessed surface. The electrical performance of the storage unit structure can be improved at least.

Description

Technical Field

[0001] The disclosed embodiments relate to the semiconductor field, and in particular to a memory cell structure, a memory cell array structure, and a method for manufacturing the same. Background Art

[0002] With the continuous development of semiconductor structures, their critical dimensions are constantly decreasing. However, due to the limitations of lithography machines, there is a limit to the reduction of their critical dimensions. Therefore, how to make chips with higher storage density on a wafer is the research direction of many scientific researchers and semiconductor practitioners. In two-dimensional or planar semiconductor devices, storage units are arranged in the horizontal direction. Therefore, the integration density of two-dimensional or planar semiconductor devices can be determined by the area occupied by the unit storage unit. The integration density of two-dimensional or planar semiconductor devices is greatly affected by the technology of forming fine patterns, which makes the continuous increase of the integration density of two-dimensional or planar semiconductor devices limited. Therefore, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.

[0003] However, the arrangement of the functional devices in the current three-dimensional semiconductor devices requires a completely new design, such as making full use of the existing layout space while ensuring that the functional devices are not affected, so as to improve the integration density of the three-dimensional semiconductor devices. Summary of the invention

[0004] The embodiments of the present disclosure provide a memory cell structure, a memory cell array structure and a manufacturing method thereof, which are at least beneficial to improving the electrical performance of the memory cell structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a storage unit structure, including: a gate extending along a first direction, the gate having a first surface and a second surface opposite to each other along a second direction, the second surface having a first recessed surface and a second recessed surface arranged at intervals along the first direction, the first recessed surface and the second recessed surface are both recessed toward the first surface, and the first direction and the second direction intersect; a gate dielectric layer, conformally covering at least the second surface; a semiconductor layer, conformally covering a side of the gate dielectric layer away from the gate, the semiconductor layer having a contact surface opposite to the second surface, the contact surface having a third recessed surface corresponding to the first recessed surface, and a fourth recessed surface corresponding to the second recessed surface; a capacitor structure including a lower electrode layer, an upper electrode layer, and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer, the lower electrode layer being in contact with the third recessed surface; and a bit line structure being in contact with the fourth recessed surface.

[0006] In some embodiments, the lower electrode layer is an annular structure, and the outer wall of the lower electrode layer is in contact and connected with the entire third recessed surface; the first direction and the second direction constitute a reference plane, and the orthographic projection shape of the annular structure on the reference plane is a square ring, a circular ring, an elliptical ring or an N-sided ring, where N is a positive integer greater than or equal to 5.

[0007] In some embodiments, the sidewalls of the bit line structure extending along the third direction are in contact with the entire fourth recessed surface, and the first direction, the second direction and the third direction intersect each other.

[0008] In some embodiments, a plurality of capacitor structures are connected in parallel, the lower electrode layer of one of the plurality of capacitor structures is in contact with and connected to the third recessed surface, and the lower electrode layers of the remaining capacitor structures are in contact with and connected in sequence.

[0009] In some embodiments, among the multiple capacitor structures other than the capacitor structure in contact with the third recessed surface, the lower electrode layer in at least some of the capacitor structures is arranged along the first direction, and / or, the lower electrode layer in at least some of the capacitor structures is arranged along the second direction.

[0010] In some embodiments, the gate also has a third surface and a fourth surface opposite to each other along a third direction, and the first direction, the second direction and the third direction intersect each other; the gate dielectric layer also conformally covers the third surface and / or the fourth surface; the semiconductor layer also conformally covers a side of the gate dielectric layer away from the third surface and a side of the gate dielectric layer away from the fourth surface.

[0011] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a memory cell array structure, comprising: a plurality of memory cell structures as described in any one of the above items; the plurality of memory cell structures are arranged in sequence along the first direction and / or the third direction, and the first direction, the second direction and the third direction intersect with each other.

[0012] In some embodiments, a plurality of the memory cell structures are arranged in sequence along the first direction, the gates in the memory cell structures adjacent to each other along the first direction are electrically connected through a first electrical connection layer, and a dielectric layer is provided between the semiconductor layers in the memory cell structures adjacent to each other along the first direction.

[0013] In some embodiments, the plurality of storage cell structures are arranged in sequence along the third direction; a dielectric layer is provided between the lower electrode layers in the plurality of storage cell structures arranged in sequence along the third direction; the plurality of lower electrode layers arranged in sequence along the third direction surround the outer side wall of the same capacitor dielectric layer; the inner side of the capacitor dielectric layer forms a first through hole, and the upper electrode layer fills the first through hole.

[0014] In some embodiments, the plurality of memory cell structures are further arranged at intervals along the second direction, two adjacent memory cell structures along the second direction are axially symmetrical along the first direction, and two gates in the adjacent memory cell structures along the second direction are respectively contacted and connected to two first electrical connection layers, and the two first electrical connection layers are electrically connected through the second electrical connection layer.

[0015] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a method for manufacturing a memory cell array structure, comprising: providing a substrate; forming a plurality of memory cell structures arranged along a first direction and / or a third direction on the substrate; the memory cell structure comprising: a gate extending along the first direction, the gate having a first surface and a second surface opposite to each other along a second direction, the second surface having a first recessed surface and a second recessed surface arranged at intervals along the first direction, the first recessed surface and the second recessed surface both being recessed toward the first surface; a gate dielectric layer, conformally covering at least the second surface; a semiconductor layer, conformally covering a side of the gate dielectric layer away from the gate, the semiconductor layer having a contact surface facing the second surface, the contact surface having a third recessed surface corresponding to the first recessed surface, and a fourth recessed surface corresponding to the second recessed surface; a capacitor structure comprising a lower electrode layer, an upper electrode layer, and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer, the lower electrode layer being in contact with and connected to the third recessed surface; a bit line structure being in contact with and connected to the fourth recessed surface; the first direction, the second direction, and the third direction intersect each other.

[0016] In some embodiments, the steps of forming the capacitor structure and the bit line structure in the plurality of storage cell structures include: forming a stacking structure on the substrate, the stacking structure including a first isolation layer and a second isolation layer alternately stacked along the third direction; performing a patterning process on the stacking structure to form at least one first opening and at least one second opening, the first opening and the second opening being alternately arranged along the first direction; conformally covering an initial lower electrode layer and a capacitor dielectric layer on the inner wall of the first opening in sequence; forming the upper electrode layer that fills the remaining first opening; forming the bit line structure that fills the second opening; removing the first isolation layer to form a third opening, the third opening exposing a portion of the thickness of the initial lower electrode layer along the third direction; removing the exposed initial lower electrode layer to form a plurality of the lower electrode layers that are spaced apart along the third direction.

[0017] In some embodiments, the step of forming the semiconductor layer in the plurality of memory cell structures comprises: forming a third isolation layer that fills the third opening; laterally etching a portion of the width of the second isolation layer along the second direction to form a fourth opening, the fourth opening exposing the outer wall of the lower electrode layer away from the capacitor dielectric layer, and exposing a portion of the side wall of the bit line structure, the fourth opening having a first inner wall exposing the lower electrode layer and the bit line structure, and a second inner wall and a third inner wall that are arranged opposite to each other along the third direction; forming an initial semiconductor layer extending along the first direction, the initial semiconductor layer at least covering the first inner wall; forming an initial gate dielectric layer located on a side of the initial semiconductor layer away from the lower electrode layer, the initial gate dielectric layer extending along the first direction; forming an initial gate located on a side of the initial gate dielectric layer away from the initial semiconductor layer, the initial gate extending along the first direction; and patterning the initial semiconductor layer to form a plurality of semiconductor layers spaced apart along the first direction, wherein one semiconductor layer is in contact with and connected to one lower electrode layer and one bit line structure, respectively.

[0018] In some embodiments, the initial semiconductor layer also covers the second inner wall and / or the third inner wall, the initial gate dielectric layer is also located between the initial semiconductor layer covering the second inner wall and the initial gate, and / or the initial gate dielectric layer is also located between the initial semiconductor layer covering the third inner wall and the initial gate.

[0019] In some embodiments, there is a gap between the semiconductor layers adjacent to each other along the first direction, and the initial gate includes the gate facing the semiconductor layer and a first electrical connection layer facing the gap.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] The gate is designed to have a first recessed surface and a second recessed surface arranged at intervals along the first direction, and the gate dielectric layer and the semiconductor layer both have two recessed surfaces corresponding to the first recessed surface and the second recessed surface, respectively. Based on this structure, the capacitor structure and the bit line structure can be respectively embedded in the two recesses in the semiconductor layer to realize a 1T1C type storage unit structure, that is, a storage unit structure consisting of a transistor source or drain electrically connected to a capacitor. It can be understood that both the capacitor structure and the bit line structure can be regarded as partially embedded in the semiconductor layer, that is, the lower electrode layer is in contact with the third recessed surface, and the bit line structure is in contact with the fourth recessed surface. In this way, it is beneficial to increase the contact area between the lower electrode layer and the semiconductor layer to reduce the contact resistance between the two, and to increase the contact area between the bit line structure and the semiconductor layer to reduce the contact resistance between the two, thereby facilitating the improvement of the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer and the semiconductor layer, and improving the transmission efficiency and transmission accuracy of the electrical signal between the bit line structure and the semiconductor layer. Therefore, it is beneficial to improve the electrical performance of the storage unit structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of a three-dimensional structure of a storage unit structure provided by an embodiment of the present disclosure;

[0024] Figure 2 A schematic cross-sectional structure diagram of a storage unit structure provided by an embodiment of the present disclosure;

[0025] Figure 3 A schematic diagram of a three-dimensional structure of a gate in a memory cell structure provided in an embodiment of the present disclosure;

[0026] Figure 4 A schematic diagram of a three-dimensional structure of a gate, a gate dielectric layer and a semiconductor layer provided in one embodiment of the present disclosure;

[0027] Figure 5Another schematic diagram of a three-dimensional structure of a storage unit structure provided by an embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram of a top view of a storage unit structure provided in one embodiment of the present disclosure;

[0029] Figure 7 Another schematic diagram of a top view of a storage unit structure provided by an embodiment of the present disclosure;

[0030] Figure 8 A schematic diagram of another top view of a storage unit structure provided in an embodiment of the present disclosure;

[0031] Fig. 9 A schematic diagram of another top view of a storage unit structure provided in an embodiment of the present disclosure;

[0032] Fig.10 A schematic diagram of a three-dimensional structure of a storage cell array structure provided by another embodiment of the present disclosure;

[0033] Fig.11 A schematic diagram of a three-dimensional structure of a capacitor structure and a bit line structure in a memory cell array structure provided by another embodiment of the present disclosure;

[0034] Fig.12 A schematic diagram of a front view of a memory cell array structure provided by another embodiment of the present disclosure;

[0035] Fig.13 Another schematic diagram of the front view of a memory cell array structure provided by another embodiment of the present disclosure;

[0036] Fig.14 A schematic diagram of a top view of a memory cell array structure provided by another embodiment of the present disclosure;

[0037] Fig.15 Another schematic diagram of a top view of a memory cell array structure provided by another embodiment of the present disclosure;

[0038] Figures 16 to 23 A structural schematic diagram corresponding to each step of a method for manufacturing a memory cell array structure provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] As known from the background art, the electrical performance of the memory cell structure needs to be improved.

[0040] The disclosed embodiments provide a memory cell structure, a memory cell array structure and a manufacturing method thereof. In the memory cell structure, a first concave surface and a second concave surface of a gate are designed to be arranged at intervals along a first direction, and the gate dielectric layer and the semiconductor layer each have two concave surfaces corresponding to the first concave surface and the second concave surface, respectively. Based on the structure, a capacitor structure and a bit line structure can be designed to be partially embedded in the semiconductor layer, that is, the lower electrode layer is in contact with the third concave surface, and the bit line structure is in contact with the fourth concave surface. In this way, it is beneficial to increase the contact area between the lower electrode layer and the semiconductor layer to reduce the contact resistance between the two, and to increase the contact area between the bit line structure and the semiconductor layer to reduce the contact resistance between the two, thereby facilitating the improvement of the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer and the semiconductor layer, and improving the transmission efficiency and transmission accuracy of the electrical signal between the bit line structure and the semiconductor layer. Therefore, it is beneficial to improve the electrical performance of the memory cell structure.

[0041] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0042] An embodiment of the present disclosure provides a memory cell structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 A schematic diagram of a three-dimensional structure of a storage unit structure provided by an embodiment of the present disclosure;

[0043] Figure 2 A schematic cross-sectional structure diagram of a storage unit structure provided by an embodiment of the present disclosure; Figure 3 A schematic diagram of a three-dimensional structure of a gate in a memory cell structure provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of a three-dimensional structure of a gate, a gate dielectric layer and a semiconductor layer provided in one embodiment of the present disclosure; Figure 5 Another schematic diagram of a three-dimensional structure of a storage unit structure provided by an embodiment of the present disclosure; Figures 6 to 9 Four schematic diagrams of top views of the storage unit structure provided in one embodiment of the present disclosure. It should be noted that: Figures 1 to 9 All of them are partial structural schematic diagrams of storage unit structures.

[0044] refer to Figures 1 to 4 and Figure 6The memory cell structure includes: a gate 100 extending along a first direction X, the gate 100 having a first surface 101 and a second surface 102 opposite to each other along a second direction Y, the second surface 102 having a first concave surface 103 and a second concave surface 104 arranged at intervals along the first direction X, the first concave surface 103 and the second concave surface 104 both being concave toward the first surface 101, and the first direction X and the second direction Y intersecting; a gate dielectric layer 110, at least conformally covering the second surface 102; a semiconductor layer 120, conformally covering the gate dielectric layer 110 and away from the gate 10 0, the semiconductor layer 120 has a contact surface 121 facing the second surface 102, the contact surface 121 has a third recessed surface 122 corresponding to the first recessed surface 103, and a fourth recessed surface 123 corresponding to the second recessed surface 104; a capacitor structure 130 including a lower electrode layer 131, an upper electrode layer 132 and a capacitor dielectric layer 133 located between the upper electrode layer 132 and the lower electrode layer 131, the lower electrode layer 131 is in contact with the third recessed surface 122; a bit line structure 140 is in contact with the fourth recessed surface 123.

[0045] It can be understood that the gate 100 is designed to have a first recessed surface 103 and a second recessed surface 104 arranged at intervals along the first direction X, and the gate dielectric layer 110 and the semiconductor layer 120 both have two recessed surfaces corresponding to the first recessed surface 103 and the second recessed surface 104, respectively, wherein the semiconductor layer 120 has a third recessed surface 122 corresponding to the first recessed surface 103 and a fourth recessed surface 123 corresponding to the second recessed surface 104. Based on this structure, the capacitor structure 130 and the bit line structure 140 can be respectively embedded in the two recesses in the semiconductor layer 120 to realize a 1T1C type storage cell structure, that is, a storage cell structure consisting of a transistor source or drain electrically connected to a capacitor. It can be understood that both the capacitor structure 130 and the bit line structure 140 can be regarded as partially embedded in the semiconductor layer 120, that is, the lower electrode layer 131 is in contact with the third recessed surface 122, and the bit line structure 140 is in contact with the fourth recessed surface 123. This is beneficial to increase the contact area between the lower electrode layer 131 and the semiconductor layer 120 to reduce the contact resistance therebetween, and to increase the contact area between the bit line structure 140 and the semiconductor layer 120 to reduce the contact resistance therebetween, thereby facilitating the improvement of the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer 131 and the semiconductor layer 120, and improving the transmission efficiency and transmission accuracy of the electrical signal between the bit line structure 140 and the semiconductor layer 120. Therefore, it is beneficial to improve the electrical performance of the memory cell structure.

[0046] The memory cell structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0047] In some embodiments, the material of the gate 100 may be a metal material, such as titanium, tungsten or copper, etc. The material of the gate 100 may also be a compound material such as titanium nitride.

[0048] In some embodiments, in conjunction with reference Figure 3 and Figure 4 The gate 100 also has a third surface 105 and a fourth surface 106 that are opposite to each other along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect each other; the gate dielectric layer 110 also conformally covers the third surface 105 and / or the fourth surface 106; the semiconductor layer 120 also conformally covers the side of the gate dielectric layer 110 away from the third surface 105 and / or the side of the gate dielectric layer 110 away from the fourth surface 106. It can be understood that no matter how the layout area of ​​the semiconductor layer 120 is, the gate dielectric layer 110 is spaced between the semiconductor layer 120 and the gate 100.

[0049] In other words, the surface of the semiconductor layer 120 facing the gate 100 may also include part of the third surface 105 and / or the fourth surface 106. For example, the gate dielectric layer 110 also conformally covers the third surface 105 and the fourth surface 106, and the semiconductor layer 120 also conformally covers the side of the gate dielectric layer 110 away from the third surface 105 and the side of the gate dielectric layer 110 away from the fourth surface 106. That is to say, the surface of the gate 100 facing the semiconductor layer 120 includes part of the third surface 105, part of the fourth surface 106 and part of the second surface 102. Compared with the semiconductor layer 120 only facing part of the second surface 102, it is beneficial to further increase the facing area between the gate 100 and the semiconductor layer 120, thereby increasing the control ability of the gate 100 over the semiconductor layer 120.

[0050] In some embodiments, the material of the gate dielectric layer 110 may be a material with a high relative dielectric constant such as hafnium oxide or zirconium oxide. It should be noted that the relative dielectric constant here is a physical parameter that characterizes the dielectric properties or polarization properties of the dielectric material. Its value is equal to the ratio of the capacitance of a capacitor made with a preset material as the dielectric to the capacitance of a capacitor of the same size made with a vacuum as the dielectric.

[0051] In some embodiments, the material of the semiconductor layer 120 may be a metal semiconductor compound layer such as indium gallium zinc oxide or zinc tin oxide.

[0052] refer to Figure 1 , Figure 4 and Figure 6 In some embodiments, the lower electrode layer 131 may be an annular structure, and the outer wall of the lower electrode layer 131 and the entire third recessed surface 122 are in contact and connected. In other words, the outer wall of the lower electrode layer 131 and the entire third recessed surface 122 fit each other, that is, the outer wall of the lower electrode layer 131 and the entire third recessed surface 122 fit each other.

[0053] It can be understood that if the surface of the third recessed surface 122 is flat, then the outer wall surface of the corresponding lower electrode layer 131 is also flat. If the surface of the third recessed surface 122 is curved, then the outer wall surface of the corresponding lower electrode layer 131 is also curved. For example, if the third recessed surface 122 is a curved surface that is recessed toward the gate 100, then there is a protrusion embedded in the outer wall surface of the lower electrode layer 131 and the corresponding position to fit with the third recessed surface 122. In this way, it is beneficial to increase the contact area between the lower electrode layer 131 and the semiconductor layer 120 to reduce the contact resistance between the two, and it is beneficial to improve the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer 131 and the semiconductor layer 120, so as to improve the electrical performance of the storage unit structure.

[0054] In some embodiments, the outer wall of the lower electrode layer 131 may only partially contact the third recessed surface 122. It is understandable that the larger the contact area between the outer wall of the lower electrode layer 131 and the third recessed surface 122, the smaller the contact resistance between the lower electrode layer 131 and the semiconductor layer 120.

[0055] In some embodiments, the first direction X and the second direction Y constitute a reference plane, and the orthographic projection shape of the ring structure on the reference plane is a square ring, a circular ring, an ellipse, or an N-gonal ring, where N is a positive integer greater than or equal to 5. In other words, the orthographic projection shape of the lower electrode layer 131 on the reference plane is a square ring, a circular ring, an ellipse, or an N-gonal ring, so that it is convenient to set a plurality of capacitor structures 130 in parallel, thereby increasing the capacitance of the storage unit structure.

[0056] In some embodiments, the orthographic projection shape of the capacitor structure 130 as a whole on the reference surface can be a circle, a triangle, a square, or an N-gon (N can be greater than or equal to 5), etc. Taking the orthographic projection shape of the capacitor structure 130 on the reference surface as a circle as an example, the orthographic projection shape of the lower electrode layer 131 on the reference surface is a circular ring, the upper electrode layer 132 is located in the circle surrounded by the lower electrode layer 131, and is spaced from the lower electrode layer 131, and the capacitor dielectric layer 133 is located between the lower electrode layer 131 and the upper electrode layer 132.

[0057] refer to Figure 5 In some embodiments, the space surrounded by the upper electrode layer 132 may further include a filling layer 134, which may fill the space surrounded by the upper electrode layer 132. The material of the filling layer 134 may be a semiconductor material such as polysilicon. In some embodiments, the filling layer 134 may serve as a part of the upper electrode layer 132.

[0058] refer to Figures 7 to 9In some embodiments, the storage unit structure may include a plurality of capacitor structures 130 connected in parallel, a lower electrode layer 131 of one of the plurality of capacitor structures 130 is in contact with and connected to the third recessed surface 122, and the lower electrode layers 131 of the remaining capacitor structures 130 are in contact with and connected in sequence.

[0059] It should be noted that Figure 7 In the example of three capacitor structures 130 connected in parallel, the three capacitor structures 130 can be divided into a first capacitor structure, a second capacitor structure and a third capacitor structure, wherein the lower electrode layer 131 of the first capacitor structure and the third recessed surface 122 (reference Figure 4 ) are in contact connection, the lower electrode layer 131 of the second capacitor structure is in contact connection with the lower electrode layer 131 of the first capacitor structure, and the lower electrode layer 131 of the third capacitor structure is in contact connection with the lower electrode layer 131 of the second capacitor structure. By setting a plurality of capacitor structures 130 connected in parallel, the capacitance of the storage unit structure can be increased to improve the electrical performance of the storage unit structure.

[0060] In some embodiments, among multiple capacitor structures 130 other than the capacitor structure 130 in contact with the third recessed surface 122, the lower electrode layer 131 in at least some of the capacitor structures 130 is arranged along the first direction X, and / or, the lower electrode layer 131 in at least some of the capacitor structures 130 is arranged along the second direction Y.

[0061] It can be understood that the lower electrode layer 131 in at least part of the capacitor structure 130 is arranged along the first direction X, and / or the lower electrode layer 131 in at least part of the capacitor structure 130 is arranged along the second direction Y, which can mean that: multiple capacitor structures 130 except the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the first direction X, or, multiple capacitor structures 130 except the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the second direction Y, or, multiple capacitor structures 130 except the capacitor structure 130 in contact with the third recessed surface 122 are partially arranged along the first direction X and partially arranged along the second direction Y.

[0062] The following is an exemplary description of the arrangement of the plurality of capacitor structures 130 .

[0063] In some embodiments, reference Figure 7 , the multiple capacitor structures 130 are arranged in sequence along the second direction Y. In practical applications, the multiple capacitor structures can also be arranged in sequence along the first direction, and the whole formed by the multiple capacitor structures is spaced apart from the bit line structure.

[0064] In other embodiments, reference Figure 8The plurality of capacitor structures 130 connected in parallel to each other include a first portion extending along the second direction Y and a second portion extending along the first direction X. The first portion has a first end and a second end opposite to each other in the second direction Y. The capacitor structure 130 as the first end is connected to the third recessed surface 122 (reference Figure 4 ) is contacted and connected, and the capacitor structure 130 at the second end is contacted and connected with a capacitor structure 130 in the second part; wherein, the multiple capacitor structures 130 included in the first part are arranged in sequence along the second direction Y, and the multiple capacitor structures 130 included in the second part are arranged in sequence along the first direction X.

[0065] In some further embodiments, reference Fig. 9 On the basis that a plurality of mutually parallel capacitor structures 130 include a first portion extending along the second direction Y and a second portion extending along the first direction X, the second portion has a third end and a fourth end relative to each other in the first direction X; the plurality of mutually parallel capacitor structures 130 may also include a third portion extending along the second direction Y, and the third portion includes a plurality of capacitor structures 130 arranged in sequence along the second direction Y; wherein the capacitor structure 130 as the third end is in contact with and connected to the capacitor structure 130 as the second end, and the capacitor structure 130 as the fourth end is in contact with and connected to a capacitor structure 130 in the third portion.

[0066] It can be understood that in the above example, taking the storage unit structure including 7 capacitor structures 130 as an example, the 7 capacitor structures 130 are respectively a first capacitor structure, a second capacitor structure, a third capacitor structure...a seventh capacitor structure, wherein the lower electrode layer 131 of the first capacitor structure is in contact with the third recessed surface 122, and the lower electrode layer 131 of the second capacitor structure is in contact with the lower electrode layer 131 of the first capacitor structure. On this basis, the plurality of capacitor structures 130 except the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the first direction X, which means that the second capacitor structure to the seventh capacitor structure are arranged in sequence along the first direction X, and the lower electrode layer 131 is contacted and connected in sequence; the plurality of capacitor structures 130 except the capacitor structure 130 in contact with the third recessed surface 122 are arranged along the second direction Y, which means that the second capacitor structure to the seventh capacitor structure are arranged in sequence along the second direction Y, and the lower electrode layer 131 is contacted and connected in sequence; the plurality of capacitor structures 130 except the capacitor structure 130 in contact with the third recessed surface 122 are partially arranged along the first direction X, and partially arranged along the second direction Y, which may mean that the second capacitor structure to the fourth capacitor structure are arranged in sequence along the first direction X, and the lower electrode layer 131 is contacted and connected in sequence, the fourth capacitor structure to the sixth capacitor structure are arranged in sequence along the second direction Y, and the lower electrode layer 131 is contacted and connected in sequence, and the seventh capacitor structure is located on the side of the sixth capacitor structure close to the semiconductor layer 120 or on the side away from the semiconductor layer 120.

[0067] It should be noted that the number and arrangement of the above-mentioned capacitor structures 130 are only examples for the convenience of explanation. The number and arrangement of the capacitor structures 130 can also be other arrangements or other arrangement directions, etc. These methods also fall within the protection scope of the embodiments of the present disclosure and will not be explained one by one below.

[0068] In some embodiments, the material of the lower electrode layer 131 and / or the upper electrode layer 132 may be titanium nitride or cobalt nitride, etc.

[0069] In some embodiments, reference Figures 1 to 9 , the sidewalls of the bit line structure 140 extending along the third direction Z are in contact with the entire fourth recessed surface 123, and the first direction X, the second direction Y, and the third direction Z intersect each other. In this way, by setting the sidewalls of the bit line structure 140 extending along the third direction Z to be in contact with the entire fourth recessed surface 123, it is beneficial to increase the contact area between the bit line structure 140 and the fourth recessed surface 123, thereby facilitating the reduction of the contact resistance between the bit line structure 140 and the semiconductor layer 120, so as to improve the electrical performance of the memory cell structure.

[0070] In some embodiments, the surface of the bit line structure 140 facing the fourth recessed surface 123 fits with the fourth recessed surface 123, that is, if the surface of the fourth recessed surface 123 is flat, then the corresponding surface of the bit line structure 140 is also flat; if the surface of the fourth recessed surface 123 is curved, then the corresponding surface of the bit line structure 140 is also curved. For example, the fourth recessed surface 123 is a curved surface recessed toward the gate 100, then there is a protrusion embedded in the surface of the bit line structure 140 and the corresponding position thereof to fit with the fourth recessed surface 123.

[0071] In some embodiments, the first direction X and the second direction Y constitute a reference plane, and the orthographic projection shape of the bit line structure 140 on the reference plane may be a circle, a triangle, a square, or an N-gon (N may be greater than or equal to 5), etc.

[0072] In some embodiments, the bit line structure 140 may include: a bit line conductive layer 141 and a bit line blocking layer 142, wherein the bit line blocking layer 142 is at least located between the bit line conductive layer 141 and the semiconductor layer 120, which helps to prevent ions in the bit line conductive layer 141 and other film layers from diffusing into the semiconductor layer 120, so as to prevent the electrical properties of the semiconductor layer 120 from being affected.

[0073] In some embodiments, the material of the bit line conductive layer 141 may be metal such as tungsten or copper, and the material of the bit line barrier layer 142 may be titanium nitride (TiN), tungsten nitride (WN), titanium silicon nitride (TiSiN), or the like.

[0074] In summary, the gate 100 is designed to have a first recessed surface 103 and a second recessed surface 104 arranged at intervals along the first direction X, and the gate dielectric layer 110 and the semiconductor layer 120 both have two recessed surfaces corresponding to the first recessed surface 103 and the second recessed surface 104, respectively, wherein the semiconductor layer 120 has a third recessed surface 122 corresponding to the first recessed surface 103 and a fourth recessed surface 123 corresponding to the second recessed surface 104. Based on this structure, the capacitor structure 130 and the bit line structure 140 can be respectively embedded in the two recesses in the semiconductor layer 120 to realize a 1T1C type storage cell structure, that is, a storage cell structure consisting of a transistor source or drain electrically connected to a capacitor. It can be understood that both the capacitor structure 130 and the bit line structure 140 can be regarded as partially embedded in the semiconductor layer 120, that is, the lower electrode layer 131 is in contact with the third recessed surface 122, and the bit line structure 140 is in contact with the fourth recessed surface 123. This is beneficial to increase the contact area between the lower electrode layer 131 and the semiconductor layer 120 to reduce the contact resistance therebetween, and to increase the contact area between the bit line structure 140 and the semiconductor layer 120 to reduce the contact resistance therebetween, thereby facilitating the improvement of the transmission efficiency and transmission accuracy of the electrical signal between the lower electrode layer 131 and the semiconductor layer 120, and improving the transmission efficiency and transmission accuracy of the electrical signal between the bit line structure 140 and the semiconductor layer 120. Therefore, it is beneficial to improve the electrical performance of the memory cell structure.

[0075] Another embodiment of the present disclosure further provides a memory cell array structure, which is composed of a plurality of memory cell structures provided by the aforementioned embodiments. Fig.10 A schematic diagram of a three-dimensional structure of a storage cell array structure provided by another embodiment of the present disclosure; Fig.11 A schematic diagram of a three-dimensional structure of a capacitor structure and a bit line structure in a memory cell array structure provided by another embodiment of the present disclosure; Fig.12 A schematic diagram of a front view of a memory cell array structure provided by another embodiment of the present disclosure; Fig.13 Another schematic diagram of the front view of a memory cell array structure provided by another embodiment of the present disclosure; Fig.14 A schematic diagram of a top view of a memory cell array structure provided by another embodiment of the present disclosure; Fig.15 Another schematic diagram of a top view of a memory cell array structure provided in another embodiment of the present disclosure.

[0076] The memory cell array structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above embodiments will not be described in detail here.

[0077] refer to Figures 10 to 15The memory cell array structure may include: a plurality of memory cell structures provided in the aforementioned embodiments, wherein the plurality of memory cell structures are sequentially arranged in a first direction X and / or a third direction Z, and the first direction X, the second direction Y and the third direction Z intersect each other.

[0078] In some embodiments, reference Fig.10 and Fig.13 ,in, Fig.13 for Fig.10 A schematic diagram of a front view of a memory cell array structure is shown, wherein a plurality of memory cell structures are sequentially arranged in intervals along a first direction X, the gates 100 in the adjacent memory cell structures along the first direction X are electrically connected via a first electrical connection layer 150, and a dielectric layer 160 is provided between the semiconductor layers 120 in the adjacent memory cell structures along the first direction X. In other words, the gates 100 of the memory structures arranged along the first direction X are electrically connected to each other, and the semiconductor layers 120 of the memory structures arranged along the first direction X are insulated from each other.

[0079] In other embodiments, reference Fig.10 , Fig.12 and Fig.14 ,in, Fig.12 for Fig.10 Another front view schematic diagram of the memory cell array structure shown, Fig.14 for Fig.10 In the schematic diagram of a top view of the memory cell array structure shown, the plurality of gates 100 and the plurality of first electrical connection layers 150 spaced apart along the first direction X may also be an integrally formed structure. It is understandable that the plurality of first electrical connection layers 150 are formed while the plurality of gates 100 are formed.

[0080] In some embodiments, the material of the first electrical connection layer 150 may be the same as that of the gate 100 , thereby facilitating reduction of the interface state at the connection surface between the gate 100 and the first electrical connection layer 150 , thereby facilitating improvement of the electrical performance of the memory cell array structure.

[0081] In some embodiments, continue to refer to Fig.10 and Fig.13 The semiconductor layer 120 is isolated by the dielectric layer 160, which is beneficial to avoid electrical connection between the plurality of semiconductor layers 120 arranged at intervals along the first direction X, thereby helping to avoid signal anomalies in the memory cell array structure.

[0082] In some embodiments, the dielectric layer 160 may include insulating materials such as silicon oxide or silicon nitride; in other embodiments, the dielectric layer 160 may also be composed of air. Thus, the dielectric layer 160 is provided to discontinuity the plurality of semiconductor layers 120 arranged in intervals along the first direction X.

[0083] In some embodiments, the gate dielectric layers 110 in adjacent storage cell structures along the first direction X may be isolated by the dielectric layer 160; in other embodiments, the gate dielectric layers 110 in adjacent storage cell structures along the first direction X may be interconnected; in still other embodiments, the gate dielectric layers 110 in adjacent storage cell structures along the first direction X may be an integrally formed structure.

[0084] refer to Fig.10 and Fig.11 ,in, Fig.11 The structure diagram of a capacitor structure 130 and a bit line structure 140 is shown in FIG. 1 . In some embodiments, a plurality of memory cell structures are sequentially arranged in intervals along a third direction Z; a dielectric layer 160 is provided between the lower electrode layers 131 in the plurality of memory cell structures arranged in intervals along the third direction Z; the plurality of lower electrode layers 131 arranged in intervals along the third direction Z surround the outer side wall of the same capacitor dielectric layer 133; the inner side of the capacitor dielectric layer 133 forms a first through hole, and the upper electrode layer 132 fills the first through hole. By providing a dielectric layer 160 between the lower electrode layers 131 in the plurality of memory cell structures arranged in intervals along the third direction Z, the capacitor structures 130 arranged in the third direction Z can be spaced, and by providing an upper electrode layer 132 filling the first through hole, that is, the capacitor structures 130 arranged in the third direction Z share the upper electrode layer 132, and by providing a capacitor structure 130 arranged in the third direction Z share the upper electrode layer 132, the electrical performance of the memory cell array structure can be improved.

[0085] In some embodiments, the capacitor structures 130 in the multiple storage unit structures arranged at intervals along the third direction Z can also be separated by the dielectric layer 160, that is, the upper electrode layers 132 arranged at intervals along the third direction Z are also separated by the dielectric layer 160, and the capacitor dielectric layers 133 arranged at intervals along the third direction Z are also separated by the dielectric layer 160.

[0086] In some embodiments, reference Fig.10 and Fig.15 ,in, Fig.15 for Fig.10 A top-down structural schematic diagram of a memory cell array structure is shown, wherein a plurality of memory cell structures are also arranged at intervals along a second direction Y, two adjacent memory cell structures along the second direction Y are axially symmetric along a first direction X, and two gates 100 in adjacent memory cell structures along the second direction Y are respectively in contact with and connected to two first electrical connection layers 150, and the two first electrical connection layers 150 are electrically connected via a second electrical connection layer 170.

[0087] It can be understood that the first electrical connection layer 150 connects two gates 100 adjacent to each other along the first direction X, the two gates 100 located on one side of the second electrical connection layer 170 and adjacent to each other along the first direction X and the first electrical connection layer 150 connecting the two gates 100, the two gates 100 located on one side of the second electrical connection layer 170 and adjacent to each other along the first direction X and the first electrical connection layer 150 and the second electrical connection layer 170 connecting the two gates 100 together form an I-shape, and the two first electrical connection layers 150 are electrically connected through the second electrical connection layer 170, that is, the first gates 100 of the storage cell structure symmetrical along the first direction X axis are electrically connected through the second electrical connection layer 170. Compared with the storage cell array structure that does not include the second electrical connection layer 170, the gates 100 of the storage cell structure symmetrical along the first direction X axis are electrically connected through the second electrical connection layer 170, which is beneficial to reducing the resistance of the gates 100 themselves.

[0088] It should be noted that, in addition to being arranged at intervals along the second direction Y, the plurality of storage unit structures may also be arranged along the first direction X and / or the third direction Z as in the above embodiment.

[0089] In some embodiments, reference Fig.10 and Fig.11 The bit line structure 140 extends along the third direction Z, and the semiconductor layer 120 of the plurality of memory cell structures arranged in the third direction Z is connected to the same bit line structure 140. That is, an electrical signal can be transmitted to the plurality of memory cell structures arranged in the third direction Z through one bit line structure 140.

[0090] Yet another embodiment of the present disclosure provides a method for manufacturing a memory cell array structure, which is used to form the memory cell array structure provided by the aforementioned embodiment. Figures 16 to 23 A schematic diagram of the structure corresponding to each step of a method for manufacturing a memory cell array structure provided by another embodiment of the present disclosure. The method for manufacturing a memory cell array structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments can refer to the contents of the above-mentioned embodiments, and will not be repeated below.

[0091] refer to Figures 16 to 23The manufacturing method of the memory cell array structure may include the following steps: providing a substrate 200; forming a plurality of memory cell structures arranged along a first direction X and / or a third direction Y on the substrate 200; the memory cell structure includes: a gate 100 extending along the first direction X, the gate 100 having a first surface 101 and a second surface 102 opposite to each other along a second direction Y, the second surface 102 having a first concave surface 103 and a second concave surface 104 arranged at intervals along the first direction X, the first concave surface 103 and the second concave surface 104 both being concave toward the first surface 101, and the first direction X and the second direction Y intersecting; a gate dielectric layer 110, at least conformally covering the second surface 102; a semiconductor layer 120, conformally covering the side of the gate dielectric layer 110 away from the gate 100, the semiconductor layer 120 has a contact surface 121 facing the second surface 102, the contact surface 121 has a third recessed surface 122 corresponding to the first recessed surface 103, and a fourth recessed surface 123 corresponding to the second recessed surface 104; a capacitor structure 130 including a lower electrode layer 131, an upper electrode layer 132 and a capacitor dielectric layer 133 located between the upper electrode layer 132 and the lower electrode layer 131, the lower electrode layer 131 is in contact with and connected to the third recessed surface 122; a bit line structure 140 is in contact with and connected to the fourth recessed surface 123; a first direction X, a second direction Y and a third direction Z intersect each other.

[0092] It should be noted that the order of forming the gate 100, the gate dielectric layer 110, and the semiconductor layer 120, the step of forming the capacitor structure 130, and the step of forming the bit line structure 140 can be adjusted, which is described in detail below.

[0093] refer to Figures 16 to 18 The formation of the capacitor structure 130 and the bit line structure 140 in the plurality of memory cell structures may include the following steps: forming a stacked structure 210 on a substrate 200, the stacked structure 210 including a first isolation layer 211 and a second isolation layer 212 alternately stacked along a third direction Z; patterning the stacked structure 210 to form at least one first opening 220 and at least one second opening 230, the first opening 220 and the second opening 230 being alternately arranged along the first direction X; conforming the inner wall of the first opening 220 to the shape of the first opening 220 in sequence; Covering an initial lower electrode layer 135 and a capacitor dielectric layer 133; forming an upper electrode layer 132 that fills the remaining first opening 220; forming a bit line structure 140 that fills the second opening 230; along the second direction Y, transversely etching a portion of the width of the first isolation layer 211 to form a third opening 240, the third opening 240 exposes a portion of the thickness of the initial lower electrode layer 135 along the third direction Z; removing the exposed initial lower electrode layer 135 to form a plurality of lower electrode layers 131 spaced apart along the third direction Z.

[0094] The above steps are described in detail below.

[0095] refer to Fig.16 , a stacked structure 210 is formed on a substrate 200 .

[0096] It can be understood that the materials of the first isolation layer 211 and the second isolation layer 212 may be different. In some embodiments, the material of the first isolation layer 211 may be silicon oxide, and the material of the second isolation layer 212 may be silicon nitride; in other embodiments, the material of the first isolation layer 211 may be silicon oxide, and the material of the second isolation layer 212 may be polysilicon.

[0097] It should be noted that Fig.16 In the example, three first isolation layers 211 and three second isolation layers 212 are stacked along the third direction Z. In actual applications, the number of first isolation layers 211 and the number of second isolation layers 212 stacked along the third direction Z can be flexibly adjusted according to needs.

[0098] Continue to refer Fig.16 , the stack structure 210 is patterned to form a first opening 220 and a second opening 230 .

[0099] It can be understood that both the first opening 220 and the second opening 230 may penetrate the stack structure 210 to expose the surface of the substrate 200 .

[0100] Combined with reference Fig.16 and Fig.17 , forming an initial lower electrode layer 135 , a capacitor dielectric layer 133 , and an upper electrode layer 132 that fills the first opening 220 .

[0101] In some embodiments, during the process of forming the initial lower electrode layer 135, the capacitor dielectric layer 133, and the upper electrode layer 132 that fills the first opening, the second opening 230 can be covered first, thereby helping to avoid filling the second opening 230 when forming the initial lower electrode layer 135, the capacitor dielectric layer 133, and the upper electrode layer 132 that fills the first opening 220.

[0102] Combined with reference Fig.16 and Fig.17 , forming a bit line structure 140 , and the bit line structure 140 completely fills the second opening 230 .

[0103] Combined with reference Fig.17 and Fig.18 , the first isolation layer 211 is etched to form a third opening 240, and along the third direction Z, the third opening 240 exposes a partial thickness of the initial lower electrode layer 135, and the initial lower electrode layer 135 exposed by the third opening 240 is etched to form the lower electrode layers 131 arranged at intervals along the third direction Z.

[0104] It can be understood that, in one etching process, the initial lower electrode layers 135 in the plurality of first openings 220 are all etched into a plurality of lower electrode layers 131 that are disconnected from each other.

[0105] refer to Figures 19 to 23 , forming the semiconductor layer 120 in the plurality of memory cell structures may include the following steps: forming a semiconductor layer 120 that fills the third opening 240 (refer to Fig.18 ) of the third isolation layer 213; along the second direction Y, the second isolation layer 212 is laterally etched with a portion of the width to form a fourth opening 250, the fourth opening 250 exposes the outer wall of the lower electrode layer 131, and exposes a portion of the side wall of the bit line structure 140, the fourth opening 250 has a first inner wall exposing the lower electrode layer 131 and the bit line structure 140, and a second inner wall and a third inner wall arranged opposite to each other along the third direction Z; an initial semiconductor layer 124 extending along the first direction X is formed, and the initial semiconductor layer 124 at least covers the first inner wall; An initial gate dielectric layer 111 is formed on a side of the initial semiconductor layer 124 away from the lower electrode layer 131, and the initial gate dielectric layer 111 extends along the first direction X; an initial gate electrode 107 is formed on a side of the initial gate dielectric layer 111 away from the initial semiconductor layer 124, and the initial gate electrode 107 extends along the first direction X; the initial semiconductor layer 124 is patterned to form a plurality of semiconductor layers 120 arranged at intervals along the first direction X, and each semiconductor layer 120 is in contact and connected with a lower electrode layer 131 and a bit line structure 140, respectively.

[0106] The above steps are described in detail below.

[0107] refer to Fig.19 , forming a third isolation layer 213, part of the third isolation layer 213 can also be used as a dielectric layer in the above-mentioned memory cell array structure embodiment.

[0108] refer to Fig. 20 , a partial width of the second isolation layer 212 is etched to form a fourth opening 250. The first inner wall of the fourth opening 250 actually corresponds to the contact surface 121 of the semiconductor layer 120 to be formed subsequently. The second inner wall and the third inner wall are the top and bottom surfaces relative to each other along the third direction Z of the fourth opening 250.

[0109] refer to Fig.21 and Fig. 22 ,in Fig. 22 for Fig.21A schematic diagram of a top view of the structure shown forms an initial semiconductor layer 124, an initial gate dielectric layer 111 and an initial gate 107. The initial semiconductor layer 124 at least covers the first inner wall. The surface of the first inner wall covered by the initial semiconductor layer 124 serves as a contact surface for a subsequently formed semiconductor layer. The initial semiconductor layer 124 is set to at least cover the first inner wall so that the subsequently formed semiconductor layer can contact the capacitor structure 130.

[0110] refer to Fig.23 , the initial semiconductor layer is patterned to form semiconductor layers 120 arranged at intervals.

[0111] In some embodiments, the initial gate dielectric layer 111 is also patterned during the process of patterning the initial semiconductor layer, and the remaining initial gate dielectric layer 111 serves as the gate dielectric layer 110 ; in other embodiments, the initial gate dielectric layer 111 may not be patterned, and the initial gate dielectric layer 111 may directly serve as the gate dielectric layer 110 .

[0112] In some embodiments, the initial gate 107 is also patterned during the patterning of the initial semiconductor layer, and the remaining initial gate 107 serves as the gate 100 ; in other embodiments, the initial gate 107 may not be patterned, and the initial gate 107 may directly serve as the gate 100 .

[0113] In some embodiments, in conjunction with reference Fig. 20 , Fig.21 and Fig.10 The initial semiconductor layer 124 also covers the second inner wall and / or the third inner wall, the initial gate dielectric layer 111 is also located between the initial semiconductor layer 124 covering the second inner wall and the initial gate 107, and / or the initial gate dielectric layer 111 is also located between the initial semiconductor layer 124 covering the third inner wall and the initial gate 107.

[0114] It can be understood that the initial semiconductor layer 124 can only cover the first inner wall and the second inner wall, or the initial semiconductor layer 124 can only cover the first inner wall and the third inner wall, or the initial semiconductor layer 124 can cover the first inner wall, the second inner wall and the third inner wall, and the initial gate dielectric layer 111 is always located between the initial semiconductor layer 124 and the initial gate 107. By setting the initial semiconductor layer 124 to also cover the second inner wall and / or the third inner wall, the facing area between the formed initial gate 107 and the initial semiconductor layer 124 is increased. In the subsequent process of forming the gate 100 and the semiconductor layer 120, the facing area between the formed gate 100 and the semiconductor layer 120 will also increase, which is beneficial to increase the control ability of the gate 100 over the semiconductor layer 120.

[0115] In some embodiments, in conjunction with reference Fig.23 , Fig.12 and Fig.13 There is a gap between the semiconductor layers 120 adjacent to each other along the first direction X, and the initial gate 107 includes a gate 100 directly opposite to the semiconductor layer 120 and a first electrical connection layer 150 directly opposite to the gap.

[0116] It can be understood that in the process of forming the initial gate 107, the gate 100 and the first electrical connection layer 150 connecting adjacent gates 100 can be formed separately, or the portion of the initial gate 107 that is opposite to the semiconductor layer 120 is used as the gate 100, and the portion that is opposite to the gap between the semiconductor layer 120 is used as the first electrical connection layer 150.

[0117] In some embodiments, in conjunction with reference Fig.23 and Fig.15 , a plurality of memory cell structures arranged along the first direction X are a memory cell structure group. In the step of forming a plurality of memory cell structures arranged along the first direction X, a plurality of memory cell structure groups are formed along the second direction Y, and two adjacent memory cell structure groups along the second direction Y are axially symmetric along the first direction X. The manufacturing method of the memory cell array structure further includes: forming a second electrical connection layer 170, and the second electrical connection layer 170 is electrically connected to the gates 100 in the adjacent memory cell structures along the second direction Y.

[0118] It can be understood that the two groups of memory cell structure groups that are axially symmetrical along the first direction X and the second electrical connection layer 170 that connects the gates 100 in the adjacent memory cell structures together form an I-shape. By electrically connecting the gates 100 of the memory cell structure groups that are axially symmetrical along the first direction X through the second electrical connection layer 170, the resistance of the gates 100 in the memory cell structure groups can be reduced.

[0119] It should be noted that Fig. 22 and Fig.23 Not with Fig.21 The top view structural diagram of is completely consistent with that of Fig.21 Only the manufacturing method of the storage unit structure arranged along the third direction Z is shown. Figures 16 to 21 The structure shown in FIG. grows along the first direction, and can obtain Fig. 22 and Fig.23 Schematic diagram of the structure of the corresponding manufacturing method.

[0120] In some embodiments, the method of forming a capacitor structure 130, a semiconductor layer 120, a gate dielectric layer 110 and a gate 100 in the above-mentioned embodiment can be referred to to form the capacitor structure 130, the semiconductor layer 120, the gate dielectric layer 110 and the gate 100 in the storage cell structure group, and then a second electrical connection layer 170 connecting the gates 100 of the storage cell structures adjacent to each other along the second direction Y is formed.

[0121] It should be noted that the order of the steps of forming the capacitor structure 130, forming the bit line structure 140, and forming the semiconductor layer 120, the gate dielectric layer 110, and the gate 100 can also be changed. For example, the bit line structure 140 can be formed first, and then the capacitor structure 130 can be formed, and finally the semiconductor layer 120, the gate dielectric layer 110, and the gate 100 can be formed. Alternatively, the semiconductor layer 120, the gate dielectric layer 110, and the gate 100 can be formed first, and then the capacitor structure 130 can be formed, and finally the bit line structure 140 can be formed, and so on.

[0122] In addition, the manufacturing method of the memory cell structure is similar to the manufacturing method of the memory cell array structure, except that the manufacturing method has shorter process steps when forming a single memory cell structure.

[0123] In summary, the manufacturing method provided in another embodiment of the present disclosure is conducive to increasing the number of memory cell structures in the memory cell array structure within a unit volume, that is, it is conducive to improving the integration density of the memory cell array structure, and it is also conducive to improving the electrical performance of the memory cell array structure.

[0124] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A storage unit structure, characterized in that: include: A gate extending in a first direction, the gate having a first surface and a second surface opposite to each other in a second direction, the second surface having a first concave surface and a second concave surface arranged at intervals in the first direction, the first concave surface and the second concave surface both being concave toward the first surface, and the first direction and the second direction intersecting; a gate dielectric layer, at least conformally covering the second surface; a semiconductor layer conformally covering a side of the gate dielectric layer away from the gate, the semiconductor layer having a contact surface directly facing the second surface, the contact surface having a third concave surface corresponding to the first concave surface, and a fourth concave surface corresponding to the second concave surface; A capacitor structure comprising a lower electrode layer, an upper electrode layer and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer, wherein the lower electrode layer is in contact with and connected to the third recessed surface; The bit line structure is in contact with the fourth recessed surface.

2. The storage unit structure according to claim 1, characterized in that: The lower electrode layer is a ring-shaped structure, and the outer wall of the lower electrode layer is in contact with and connected to the entire third concave surface; The first direction and the second direction constitute a reference plane, and the orthographic projection shape of the annular structure on the reference plane is a square ring, a circular ring, an elliptical ring or an N-sided ring, where N is a positive integer greater than or equal to 5.

3. The storage unit structure according to claim 1, characterized in that: The sidewalls of the bit line structure extending along the third direction are in contact with the entire fourth recessed surface, and the first direction, the second direction and the third direction intersect each other.

4. The memory cell structure according to any one of claims 1 to 3, characterized in that: It comprises a plurality of capacitor structures connected in parallel with each other, the lower electrode layer of one of the plurality of capacitor structures is in contact with and connected to the third recessed surface, and the lower electrode layers of the remaining capacitor structures are in contact with and connected in sequence.

5. The storage unit structure according to claim 4, characterized in that: Among the multiple capacitor structures other than the capacitor structure in contact with the third recessed surface, the lower electrode layers in at least some of the capacitor structures are arranged along the first direction, and / or, the lower electrode layers in at least some of the capacitor structures are arranged along the second direction.

6. The memory cell structure according to any one of claims 1 to 3, characterized in that: The gate further has a third surface and a fourth surface opposite to each other along a third direction, and the first direction, the second direction and the third direction intersect each other; The gate dielectric layer also conformally covers the third surface and / or the fourth surface; The semiconductor layer also conformally covers a side of the gate dielectric layer away from the third surface and a side of the gate dielectric layer away from the fourth surface.

7. A memory cell array structure, characterized in that: include: A plurality of memory cell structures according to any one of claims 1 to 6; The plurality of storage unit structures are sequentially arranged at intervals along the first direction and / or the third direction, and the first direction, the second direction and the third direction intersect each other.

8. The memory cell array structure according to claim 7, characterized in that: The plurality of memory cell structures are sequentially arranged at intervals along the first direction, the gates in the memory cell structures adjacent to each other along the first direction are electrically connected via a first electrical connection layer, and a dielectric layer is provided between the semiconductor layers in the memory cell structures adjacent to each other along the first direction.

9. The memory cell array structure according to claim 7, characterized in that: The plurality of storage unit structures are sequentially arranged at intervals along the third direction; A dielectric layer is provided between the lower electrode layers in the plurality of storage unit structures arranged at intervals along the third direction; the plurality of lower electrode layers arranged at intervals along the third direction surround the outer side wall of the same capacitor dielectric layer; The inner side of the capacitor dielectric layer forms a first through hole, and the upper electrode layer fills the first through hole.

10. The memory cell array structure according to claim 8 or 9, characterized in that: The plurality of storage cell structures are also arranged at intervals along the second direction, and two adjacent storage cell structures along the second direction are axially symmetrical along the first direction, and two gates in the adjacent storage cell structures along the second direction are respectively contacted and connected to two first electrical connection layers, and the two first electrical connection layers are electrically connected through the second electrical connection layer.

11. A method for manufacturing a memory cell array structure, characterized in that: include: providing a substrate; forming a plurality of storage unit structures arranged along a first direction and / or a third direction on the substrate; The memory cell structure comprises: a gate extending along the first direction, the gate having a first surface and a second surface opposite to each other along the second direction, the second surface having a first concave surface and a second concave surface arranged at intervals along the first direction, the first concave surface and the second concave surface both being concave toward the first surface; a gate dielectric layer conformally covering at least the second surface; a semiconductor layer conformally covering a side of the gate dielectric layer away from the gate, the semiconductor layer having a contact surface facing the second surface, the contact surface having a third concave surface corresponding to the first concave surface, and a fourth concave surface corresponding to the second concave surface; a capacitor structure comprising a lower electrode layer, an upper electrode layer, and a capacitor dielectric layer located between the upper electrode layer and the lower electrode layer, the lower electrode layer being in contact and connected with the third concave surface; and a bit line structure being in contact and connected with the fourth concave surface; The first direction, the second direction and the third direction intersect each other.

12. The manufacturing method according to claim 11, characterized in that: The step of forming the capacitor structure and the bit line structure in a plurality of the memory cell structures comprises: forming a stacking structure on the substrate, the stacking structure comprising first isolation layers and second isolation layers alternately stacked along the third direction; Performing a patterning process on the stacked structure to form at least one first opening and at least one second opening, wherein the first opening and the second opening are alternately arranged along the first direction; Conformally covering an initial lower electrode layer and a capacitor dielectric layer on the inner wall of the first opening in sequence; forming the upper electrode layer that fills the remaining first opening; forming the bit line structure that fills the second opening; The first isolation layer is removed to form a third opening, wherein the third opening exposes a portion of the thickness of the initial lower electrode layer along the third direction; and the exposed initial lower electrode layer is removed to form a plurality of the lower electrode layers spaced apart along the third direction.

13. The manufacturing method according to claim 12, characterized in that: The step of forming the semiconductor layer in a plurality of the memory cell structures comprises: forming a third isolation layer that fills the third opening; Along the second direction, the second isolation layer is laterally etched to form a fourth opening, wherein the fourth opening exposes an outer wall of the lower electrode layer away from the capacitor dielectric layer and a part of the side wall of the bit line structure, and the fourth opening has a first inner wall that exposes the lower electrode layer and the bit line structure, and a second inner wall and a third inner wall that are oppositely arranged along the third direction; forming an initial semiconductor layer extending along the first direction, the initial semiconductor layer at least covering the first inner wall; forming an initial gate dielectric layer located on a side of the initial semiconductor layer away from the lower electrode layer, the initial gate dielectric layer extending along the first direction; forming an initial gate located on a side of the initial gate dielectric layer away from the initial semiconductor layer, wherein the initial gate extends along the first direction; The initial semiconductor layer is patterned to form a plurality of semiconductor layers spaced apart along the first direction, wherein one semiconductor layer is in contact with and connected to one lower electrode layer and one bit line structure respectively.

14. The manufacturing method according to claim 13, characterized in that: The initial semiconductor layer also covers the second inner wall and / or the third inner wall, the initial gate dielectric layer is also located between the initial semiconductor layer covering the second inner wall and the initial gate, and / or the initial gate dielectric layer is also located between the initial semiconductor layer covering the third inner wall and the initial gate.

15. The manufacturing method according to claim 13 or 14, characterized in that: There is a gap between the semiconductor layers adjacent to each other along the first direction, and the initial gate includes the gate facing the semiconductor layer and a first electrical connection layer facing the gap.

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