Trench capacitor and manufacturing method thereof

Abstract

The invention provides a trench capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate; forming a first groove to expose the first metal wire, a second groove to expose the second metal wire and a third groove to expose the third metal wire; a single-layer capacitor is formed in the first groove, a double-layer capacitor is formed in the second groove, the double-layer capacitor comprises a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode, and the single-layer capacitor comprises a second electrode, a second dielectric layer and a third electrode. According to the invention, the trench capacitors are formed in the second trench and the first trench, and the first to third electrodes utilize the first to third trenches to lead out the first to third metal wires in the substrate downwards, so that the lead-out of the trench capacitors and the wiring of the metal wires on the insulating layer are realized under the condition that no additional process steps are added; the capacitance density of the trench capacitor is increased, the process integration difficulty is reduced, and the design freedom degree of the trench capacitor is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a trench capacitor and a manufacturing method thereof. Background Art

[0002] Capacitors are a conventional passive component widely used in the field of integrated circuits. In some special applications, capacitors with large unit capacitance are needed to improve product performance, such as storing signals, reducing noise, and reducing coupling. Planar capacitors need to occupy a large area to obtain large capacitance, which will sacrifice design area. For this reason, trench capacitors become the best choice for large capacitance.

[0003] The existing trench capacitors can not only have their capacitance density further improved, but also their manufacturing process can be further optimized. Summary of the invention

[0004] The object of the present invention is to provide a trench capacitor and a manufacturing method thereof, so as to improve the capacitance density thereof and optimize the manufacturing process thereof.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a trench capacitor, comprising:

[0006] Providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed in the substrate;

[0007] forming a first trench in the insulating layer to expose the first metal line, a second trench to expose the second metal line, and a third trench to expose the third metal line;

[0008] A single-layer capacitor is formed on the first groove and the insulating layer around it, and a double-layer capacitor is formed on the second groove and the insulating layer around it, the double-layer capacitor includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode formed in sequence conformally, the single-layer capacitor includes the second electrode, the second dielectric layer and the third electrode formed in sequence conformally, the first electrode is electrically connected to the second metal wire using the second groove, the second electrode is electrically connected to the first metal wire using the first groove, and the third electrode is electrically connected to the third metal wire using the third groove.

[0009] Optionally, a dielectric barrier layer is further provided between the first to third metal wires and the insulating layer.

[0010] Optionally, the insulating layer includes a first region located above the first metal line, a second region located above the second metal line, and a third region located above the third metal line, the first region is provided with the first groove, the second region is provided with the second groove, and the third region is provided with the third groove, and the steps of forming the single-layer capacitor and the double-layer capacitor include:

[0011] Forming a first electrode material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0012] Performing a patterning process on the first electrode material layer, retaining the first electrode material layers in the first region, the second region and the third region, and using the first electrode material layer in the second region as the first electrode, the first electrode being electrically connected to the second metal wire, the first electrode material layer in the first trench being electrically connected to the first metal wire, and the first electrode material layer in the third trench being electrically connected to the third metal wire;

[0013] Forming a first dielectric material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0014] Forming a first mask to cover the first dielectric material layer in the second area, and performing an etching process to remove the exposed first dielectric material layer, using the first dielectric material layer in the second area as the first dielectric layer, and exposing the first electrode material layer at the bottom of the first trench and the bottom of the third trench;

[0015] Removing the first mask, and forming a second electrode material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0016] forming a second mask to cover the first region, the second region and the second electrode material layer therebetween, removing the exposed second electrode material layer, using the first region, the second region and the second electrode material layer therebetween as the second electrode, the second electrode being electrically connected to the first electrode material layer of the first trench and the first metal line, and exposing the first electrode material layer at the bottom of the third trench;

[0017] Removing the second mask, and conformally forming a second dielectric material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0018] forming a third mask to cover the first region, the second region and the second dielectric material layer therebetween, removing the exposed second dielectric material layer, using the first region, the second region and the second dielectric material layer therebetween as the second dielectric layer, and exposing the first electrode material layer at the bottom of the third trench, wherein the third mask completely covers the second electrode;

[0019] Removing the third mask, and conformally forming a third electrode material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0020] forming a fourth mask to cover the first region, the second region, the third region and the third electrode material layer therebetween, removing the exposed third electrode material layer, using the first region, the second region, the third region and the third electrode material layer therebetween as the third electrode, the third electrode being electrically connected to the first electrode material layer of the third trench and the third metal line;

[0021] The fourth mask is removed.

[0022] Optionally, the insulating layer includes a first region located above the first metal line, a second region located above the second metal line, and a third region located above the third metal line, the first region is provided with the first groove, the second region is provided with the second groove, and the third region is provided with the third groove, and the steps of forming the single-layer capacitor and the double-layer capacitor include:

[0023] Forming a first electrode material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0024] Performing a patterning process on the first electrode material layer, retaining the first electrode material layers in the first region, the second region and the third region, and using the first electrode material layer in the second region as the first electrode, the first electrode being electrically connected to the second metal wire, the first electrode material layer in the first trench being electrically connected to the first metal wire, and the first electrode material layer in the third trench being electrically connected to the third metal wire;

[0025] Forming a first dielectric material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0026] Forming a first mask to cover the first dielectric material layer in the second area, and performing an etching process to remove the exposed first dielectric material layer, using the first dielectric material layer in the second area as the first dielectric layer, and exposing the first electrode material layer at the bottom of the first trench and the bottom of the third trench;

[0027] Removing the first mask, and conformally forming a second electrode material layer and a second dielectric material layer in sequence to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0028] forming a second mask to cover the first region, the second region and the second dielectric material layer therebetween, removing the exposed second dielectric material layer and the second electrode material layer thereunder, retaining the first region, the second region and the second electrode material layer and the second dielectric material layer therebetween, so as to form the second electrode and the second dielectric layer, wherein the second electrode is electrically connected to the first electrode material layer of the first trench and the first metal line, and exposing the first electrode material layer at the bottom of the third trench;

[0029] removing the second mask and forming a third dielectric material layer to conformally cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0030] Performing an anisotropic dry etching process to remove the exposed third dielectric material layer, and using the third dielectric material layer retained on the second electrode and the sidewall of the second dielectric layer as a sidewall, and exposing the first electrode material layer at the bottom of the third trench;

[0031] forming a third electrode material layer to conformally cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench;

[0032] forming a third mask to cover the first region, the second region, the third region and the third electrode material layer therebetween, removing the exposed third electrode material layer, using the first region, the second region, the third region and the third electrode material layer therebetween as the third electrode, the third electrode being electrically connected to the first electrode material layer of the third trench and the third metal line;

[0033] The third mask is removed.

[0034] Optionally, a single-layer planar capacitor composed of the second electrode, the second dielectric layer and the third electrode is formed between the first region and the second region.

[0035] Optionally, the material of the first electrode, the second electrode and the third electrode includes one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

[0036] Optionally, the dielectric constants of the first dielectric layer and the second dielectric layer are greater than or equal to 3.9.

[0037] Optionally, the material of the third dielectric material layer is the same as that of the second dielectric layer.

[0038] According to another aspect of the present invention, a trench capacitor is provided, comprising:

[0039] substrate;

[0040] First to third metal wires are arranged in the same layer in the substrate;

[0041] an insulating layer, covering the first to third metal wires and having a first trench formed therein to expose the first metal wire, a second trench to expose the second metal wire, and a third trench to expose the third metal wire;

[0042] A double-layer capacitor is formed in the second groove and on the insulating layer around it, comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode which are sequentially formed conformally, wherein the first electrode is electrically connected to the second metal line by using the second groove, and the third electrode is electrically connected to the third metal line by using the third groove;

[0043] A single-layer capacitor is formed in the first groove and on the insulating layer around it, and includes the second electrode, the second dielectric layer and the third electrode which are formed conformally in sequence. The second electrode is electrically connected to the first metal wire by using the first groove.

[0044] Optionally, a single-layer planar capacitor is further provided, which is provided on the insulating layer between the first metal wire and the second metal wire and is composed of the second electrode, the second dielectric layer and the third electrode.

[0045] In summary, the present invention forms a first trench exposing the first metal wire in the insulating layer on the first metal wire, forms a second trench exposing the second metal wire in the insulating layer on the second metal wire, and forms a third trench exposing the third metal wire in the insulating layer on the third metal wire, and forms a single-layer capacitor in the first trench and on the insulating layer around the first trench, and forms a double-layer capacitor in the second trench and in the insulating layer around the second trench, the single-layer trench capacitor and the double-layer trench capacitor are connected in parallel, the single-layer trench capacitor is directly formed by using the second electrode, the second dielectric layer and the third electrode of the double-layer trench capacitor, and in the two capacitors, the second dielectric layer is formed by using the second electrode, the second dielectric layer and the third electrode of the double-layer trench capacitor. An electrode is connected to a second metal wire at the bottom of the second trench by using a second trench, a second electrode is connected to a first metal wire at the bottom of the first trench by using a first trench, and a third electrode is connected to a third metal wire at the bottom of the third trench by using a third trench. Thus, the first to third electrodes of the double-layer capacitor and the second to third electrodes of the single-layer capacitor are led downward by using the first to third metal wires in the substrate, and the lead-out of the double-layer trench capacitor and the wiring of the metal wires on the insulating layer are realized without adding additional process steps, thereby increasing the capacitance density of the trench capacitor, reducing the difficulty of process integration, and being conducive to improving the degree of freedom of trench capacitor design. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0047] Figure 1 is a flow chart of a method for manufacturing a trench capacitor provided in Embodiment 1;

[0048] Figure 2a to Figure 2m A schematic structural diagram corresponding to corresponding steps of the method for manufacturing a trench capacitor provided in Embodiment 1;

[0049] Figure 3a to Figure 3k This is a schematic structural diagram corresponding to the corresponding steps of the method for manufacturing a trench capacitor provided in the second embodiment.

[0050] In the attached figure:

[0051] 10-substrate; 11-first metal wire; 12-second metal wire; 13-third metal wire; 21-dielectric barrier layer; 22-insulating layer; 23-first trench; 24-second trench; 25-third trench; AA-first region; BB-second region; CC-third region; 26-first electrode material layer; 26a-first electrode; 27-first dielectric material layer; 27a-first dielectric layer; 28-first mask; 29-second electrode material layer; 29a-second electrode; 30-second mask; 31-second dielectric material layer; 31a-second dielectric layer; 32-third mask; 33-third electrode material layer; 33a-third electrode; 34-fourth mask; 35-third dielectric material layer; 35a-side wall. DETAILED DESCRIPTION

[0052] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0053] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0054] Embodiment 1

[0055] Figure 1 4 is a flow chart of a method for manufacturing a trench capacitor provided in the first embodiment.

[0056] like Figure 1 As shown, the manufacturing method of the trench capacitor provided in this embodiment includes:

[0057] S01: providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed in the substrate;

[0058] S02: forming a first trench in the insulating layer to expose the first metal line, a second trench to expose the second metal line, and a third trench to expose the third metal line;

[0059] S03: forming a single-layer capacitor on the first groove and the insulating layer around it and forming a double-layer capacitor on the second groove and the insulating layer around it, the double-layer capacitor comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode formed conformally in sequence, the single-layer capacitor comprising the second electrode, the second dielectric layer and the third electrode formed conformally in sequence, the first electrode being electrically connected to the second metal wire using the second groove, the second electrode being electrically connected to the first metal wire using the first groove, and the third electrode being electrically connected to the third metal wire using the third groove.

[0060] Figure 2a to Figure 2m The structural schematic diagram corresponding to the corresponding steps of the manufacturing method of the trench capacitor provided in this embodiment, next, Figure 2a to Figure 2m A method for manufacturing the trench capacitor will be described in detail.

[0061] First, please refer to Figure 2a , performing step S01, providing a substrate 10, in which first to third metal wires 11-13 arranged in the same layer and an insulating layer 22 covering the first to third metal wires 11-13 are formed.

[0062] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator, etc. In this embodiment, the material of the substrate 10 is described by taking silicon (silicon substrate) as an example.

[0063] A device layer and an interconnection layer electrically connected to the device layer are formed in the substrate 10. The interconnection layer is located above the device layer and can be formed using a Damascus process. The first to third metal wires 11 to 13 can be three metal wirings arranged at intervals of the Nth layer (N is greater than or equal to 1) in the interconnection layer, and the second metal wire 12 is located between the first metal wire 11 and the third metal wire 13. The materials of the three can include copper, for example. In this embodiment, the first to third metal wires 11 to 13 can be top-layer metal wirings arranged sequentially and adjacently.

[0064] A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed on the first to third metal wires 11 to 13. The material of the dielectric barrier layer 21 is used to block the escape of metal ions and serves as an etching stop layer during etching. The material may include, for example, silicon nitride or silicon carbonitride. The material of the insulating layer 22 is different from that of the dielectric barrier layer 21, and may include, for example, silicon oxide or silicon oxynitride.

[0065] In addition, in other examples of this embodiment, as needed, multiple (at least two) first metal wires 11, multiple second metal wires 12 and multiple third metal wires 13 may be provided, and multiple identical metal wires are connected in parallel.

[0066] Next, please refer to Figure 2b , executing step S02, forming a plurality of first trenches in the insulating layer to expose the first metal line, a plurality of second trenches to expose the second metal line, and a plurality of third trenches to expose the third metal line.

[0067] Specifically, a photolithography process may be used to define three etching regions (not shown) on the insulating layer 22 on the first metal line 11, the second metal line 12, and the third metal line 13, respectively, and then a dry etching process may be used to sequentially etch the insulating layer 22 and the dielectric barrier layer 21 to form a plurality of first trenches 23 disposed at intervals to expose the first metal line 11, a plurality of second trenches 24 disposed at intervals to expose the second metal line 12, and a plurality of third trenches 25 disposed at intervals to expose the second metal line 13. The first trench 23, the second trench 24, and the third trench 25 may have the same opening size. The first trench 23 and the region where the insulating layer 22 is located around it may be a first region AA, which is used to form a single-layer capacitor thereon in the future, the second trench 24 and the region where the insulating layer 22 is located around it may be a second region BB, which is used to form a double-layer capacitor thereon in the future, and the third trench 25 and the region where the insulating layer 22 is located around it may be a third region CC, which is used to electrically connect the third metal line 13 in the future, wherein the first region AA, the second region BB, and the third region CC may be disposed at intervals or disposed in contact with each other.

[0068] In addition, as required, in practice, the first area AA may correspond to a plurality of first metal lines 11, and the coverage area of ​​the first area AA may also be larger than the area covered by the first metal line, that is, only a portion of the first grooves 23 located directly above the first metal line 11 exposes the first metal line 11, and other first grooves 23 staggered from the first metal line 11 do not expose the first metal line 11. The second area BB and the second groove 24, the third area CC and the third groove 25 may be arranged similarly as above.

[0069] Next, step S03 is performed to form a single-layer capacitor on the first trench 23 and the insulating layer 22 around it, and a double-layer capacitor on the second trench 24 and the insulating layer 22 around it. The double-layer capacitor includes a first electrode 26a, a first dielectric layer 27a, a second electrode 29a, a second dielectric layer 31a and a third electrode 33a formed in sequence in a conformal manner. The single-layer capacitor includes a second electrode 29a, a second dielectric layer 31a and a third electrode 33a formed in sequence in a conformal manner. The first electrode 26a is electrically connected to the second metal wire 12, the second electrode 29a is electrically connected to the first metal wire 11, and the third electrode 33a is electrically connected to the third metal wire 13 using the third trench 25.

[0070] For details, please refer to Figure 2c , forming a first electrode material layer 26 to cover the surface of the insulating layer 22, the inner wall of the first trench 23, the second trench 24 and the third trench 25. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 26, which may include one or more thin film conductive layers, and its material may include, for example, one or more of titanium, titanium nitride, tantalum or tantalum nitride. Its formation process may include physical vapor deposition, chemical vapor deposition or atomic layer deposition, and the first electrode material layer 26 may have a relatively thin thickness to form a double-layer trench capacitor, and its thickness may be, for example, 100 angstroms to 400 angstroms.

[0071] Please refer to Figure 2d , the first electrode material layer 26 is patterned, the first electrode material layer 26 in the first area AA, the second area BB and the third area CC is retained, and the first electrode material layer 26 in the second area BB is used as the first electrode 26a, the first electrode 26a is electrically connected to the second metal line 12, the first electrode material layer 26 in the first trench 23 is electrically connected to the first metal line 11, and the first electrode material layer 26 in the third trench 25 is electrically connected to the third metal line 13. In addition, the first electrode 26a can also extend to cover the insulating layer 22 located around the outermost second trench 24 to facilitate the patterning process. In some examples, it is feasible not to retain the first electrode material layer 26 in the first area AA and the third area CC. However, retaining the first electrode material layer 26 in the first area AA and the third area CC can make the first area AA and the third area CC have a structure similar to the second area BB, which is beneficial to the simultaneous formation of corresponding structures in the first trench 23, the second trench 24 and the third trench 25. Moreover, the first electrode material layer 26 located at the bottom of the first trench 23 and the third trench 25 can not only be used for subsequent electrical connection of the first metal wire 11 and the third metal wire 13, but also serve as a protective layer for the first metal wire 11 and the third metal wire 13.

[0072] Please refer to Figure 2e, forming a first dielectric material layer 27 to cover the surface of the insulating layer 22, the inner walls of the first trench 23, the second trench 24 and the third trench 25, that is, to cover the surface of the insulating layer 22, the first region AA, the second region BB and the third region CC. The material of the first dielectric material layer 27 can be a dielectric material with a relatively high dielectric constant, and its dielectric constant can be, for example, greater than or equal to 3.9, and its material can be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide or rhodium oxide.

[0073] Please refer to Figure 2f , a first mask 28 is formed to cover the first dielectric material layer 27 of the second area BB, and an etching process is performed to remove the exposed first dielectric material layer 27, so that the first dielectric material layer 27 of the second area BB is used as the first dielectric layer 27a, and the first electrode material layer 26 at the bottom of the first trench 23 and the third trench 25 is exposed. The first mask 28 covers an area larger than the first electrode 26a, so that the first dielectric layer 27a completely covers the first electrode 26a. In addition, when the first dielectric material layer 27 of the first area AA and the third area CC is dry-etched, the first dielectric material layer 27 located at the bottom of the first trench 23, the bottom of the third trench 25, the insulating layer 22 and the surface of the first electrode material layer 26 is removed, and the first electrode material layer 26 at the bottom of the first trench 23 and the third trench 25 is exposed, and the sidewalls of the first trench 23 and the third trench 25 may retain, partially retain or not retain the first dielectric material layer 27. In practice, taking the dry etching process to remove the first dielectric material layer 27 as an example, the first dielectric material layer 27 may be retained or partially retained on the sidewalls of the first trench 23 and the third trench 25 .

[0074] Please refer to Figure 2g , remove the first mask 28, and form a second electrode material layer 29 to cover the surface of the insulating layer 22, the inner walls of the first trench 23, the second trench 24, and the third trench 25, that is, to cover the surface of the insulating layer 222, the first region AA, the second region BB, and the third region CC. The material and thickness of the second electrode material layer 29 can refer to the material and thickness of the first electrode material layer 26.

[0075] Please refer to Figure 2h, a second mask 30 is formed to cover the first region AA, the second region BB and the second electrode material layer 29 therebetween, the exposed second electrode material layer 29 is removed, the first region AA, the second region BB and the second electrode material layer 29 therebetween are used as the second electrode 29a, and the first electrode material layer 26 at the bottom of the third trench 25 is exposed. Among them, the second electrode 29a is electrically connected to the first metal line 11 using the first electrode material layer 26 at the bottom of the first trench 23, so that the second electrode 29a of the capacitor formed in the first region AA and the second region BB is electrically led to the first metal line 11. Taking dry etching as an example, the second electrode material layer 29 on the insulating layer 22 of the third region CC is removed, the second electrode material layer 29 on the side wall of the third trench 25 is exposed (or partially retained), and it is feasible that the second electrode material layer 29 is not retained, partially retained, or retained at the bottom of the third trench 25.

[0076] Please refer to Figure 2i , remove the second mask 30, and conformally form a second dielectric material layer 31 to cover the surface of the insulating layer 22, the inner walls of the first trench 23, the second trench 24, and the third trench 25, that is, to cover the surface of the insulating layer 22, the first region AA, the second region BB, and the third region CC. The material and thickness of the second dielectric material layer 31 may refer to the material and thickness of the first dielectric material layer 27.

[0077] Please refer to Figure 2j , a third mask 32 is formed to cover the first area AA, the second area BB and the second dielectric material layer 31 therebetween, the exposed second dielectric material layer 31 is removed, the first area AA, the second area BB and the second dielectric material layer 31 therebetween are used as the second dielectric layer 31a, and the first electrode material layer 26 at the bottom of the third trench 25 is exposed. The third mask 32 completely covers the second electrode 29a, that is, the area covered by the third mask 32 is slightly larger than the area covered by the second mask 30 (the second electrode 29a), so that the formed second dielectric layer 31a can completely cover the second electrode 29a, thereby avoiding the second electrode 29a from being exposed, so that it is completely electrically isolated from the subsequent third electrode 33a. Of course, the second dielectric material layer 31 can also be retained on the sidewall of the third trench 25.

[0078] Please refer to Figure 2k, remove the third mask 32, and conformally form the third electrode material layer 33 to cover the surface of the insulating layer 22, the inner wall of the first trench 23, the second trench 24, and the third trench 25, that is, to cover the surface of the insulating layer 22, the first region AA, the second region BB, and the third region CC. The material and thickness of the third electrode material layer 33 can refer to the material and thickness of the first electrode material layer 26. In practice, the thickness of the third electrode material layer 33 can also be greater than or equal to the thickness of the first electrode material layer 26 (or the second electrode material layer 29), so that the third electrode material layer 33 fills the first trench 23, the second trench 24, and the third trench 25.

[0079] Please refer to Figure 2l , form a fourth mask 34 to cover the first area AA, the second area BB, the third area CC and the third electrode material layer 33 therebetween, remove the exposed third electrode material layer 33, and use the first area AA, the second area BB, the third area CC and the third electrode material layer 33 therebetween as the third electrode 33a, and the third electrode 33a uses the first electrode material layer 26 at the bottom of the third trench 25 to electrically connect to the third metal wire 13.

[0080] Please refer to Figure 2m , and the fourth mask 34 is removed. Thus, a single-layer trench capacitor consisting of the second electrode 29a, the second dielectric layer 31a and the third electrode 33a is formed in the first area AA on the first metal line 11, and a double-layer trench capacitor consisting of the first electrode 26a, the first dielectric layer 27a, the second electrode 29a, the second dielectric layer 31a and the third electrode 33a is formed in the second area BB on the second metal line 12, and the second electrode 29a of the single-layer trench capacitor and the double-layer trench capacitor is electrically led downward through the first metal line 11, the first electrode 26a of the double-layer trench capacitor is electrically led downward through the second metal line 12, and the third electrode 33a of the single-layer trench capacitor and the double-layer trench capacitor is electrically led downward through the third trench 25. Moreover, a single-layer planar capacitor consisting of the second electrode 29a, the second dielectric layer 31a and the third electrode 33a is also formed in the area between the first area AA and the second area BB. The single-layer trench capacitor, the single-layer planar capacitor, and the double-layer trench capacitor are connected in parallel, which can significantly increase the capacitance value on the same substrate 10 area, that is, the capacitance density.

[0081] Embodiment 2

[0082] Embodiment 2 provides a method for manufacturing a trench capacitor.

[0083] like Figure 1 As shown, the manufacturing method of the trench capacitor provided in the second embodiment includes:

[0084] S01: providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed in the substrate;

[0085] S02: forming a first trench in the insulating layer to expose the first metal line, a second trench to expose the second metal line, and a third trench to expose the third metal line;

[0086] S03: forming a single-layer capacitor on the first groove and the insulating layer around it and forming a double-layer capacitor on the second groove and the insulating layer around it, the double-layer capacitor comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode formed conformally in sequence, the single-layer capacitor comprising the second electrode, the second dielectric layer and the third electrode formed conformally in sequence, the first electrode being electrically connected to the second metal wire using the second groove, the second electrode being electrically connected to the first metal wire using the first groove, and the third electrode being electrically connected to the third metal wire using the third groove.

[0087] The method for manufacturing the trench capacitor provided in the second embodiment is similar to the method provided in the first embodiment, and the difference lies mainly in the difference in the steps of forming the single-layer capacitor and the double-layer capacitor in step S03 of the second embodiment. Figure 3a to Figure 3k The schematic diagram of the structure corresponding to the corresponding steps of forming a single-layer capacitor and a double-layer capacitor provided in the second embodiment. Next, Figure 3a to Figure 3k A method for manufacturing the trench capacitor will be described in detail.

[0088] For details, please refer to Figure 3a , forming a first electrode material layer 26 to cover the surface of the insulating layer 22, the inner wall of the first trench 23, the second trench 24 and the third trench 25. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 26, which may include one or more thin film conductive layers, and its material may include, for example, one or more of titanium, titanium nitride, tantalum or tantalum nitride. Its formation process may include physical vapor deposition, chemical vapor deposition or atomic layer deposition, and the first electrode material layer 26 may have a relatively thin thickness to form a double-layer trench capacitor, and its thickness may be, for example, 100 angstroms to 400 angstroms.

[0089] Please refer to Figure 3b, the first electrode material layer 26 is patterned, the first electrode material layer 26 in the first area AA, the second area BB and the third area CC is retained, and the first electrode material layer 26 in the second area BB is used as the first electrode 26a, the first electrode 26a is electrically connected to the second metal line 12, the first electrode material layer 26 in the first trench 23 is electrically connected to the first metal line 11, and the first electrode material layer 26 in the third trench 25 is electrically connected to the third metal line 13. In addition, the first electrode 26a can also extend to cover the insulating layer 22 located around the outermost second trench 24 to facilitate the patterning process. In some examples, it is feasible not to retain the first electrode material layer 26 in the first area AA and the third area CC. However, retaining the first electrode material layer 26 in the first area AA and the third area CC can make the first area AA and the third area CC have a structure similar to the second area BB, which is beneficial to the simultaneous formation of corresponding structures in the first trench 23, the second trench 24 and the third trench 25. Moreover, the first electrode material layer 26 located at the bottom of the first trench 23 and the third trench 25 can not only be used for subsequent electrical connection of the first metal wire 11 and the third metal wire 13, but also serve as a protective layer for the first metal wire 11 and the third metal wire 13.

[0090] Please refer to Figure 3c , forming a first dielectric material layer 27 to cover the surface of the insulating layer 22, the inner walls of the first trench 23, the second trench 24 and the third trench 25, that is, to cover the surface of the insulating layer 22, the first region AA, the second region BB and the third region CC. The material of the first dielectric material layer 27 can be a dielectric material with a relatively high dielectric constant, and its dielectric constant can be, for example, greater than or equal to 3.9, and its material can be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide or rhodium oxide.

[0091] Please refer to Figure 3d, a first mask 28 is formed to cover the first dielectric material layer 27 of the second area BB, and an etching process is performed to remove the exposed first dielectric material layer 27, so that the first dielectric material layer 27 of the second area BB is used as the first dielectric layer 27a, and the first electrode material layer 26 at the bottom of the first trench 23 and the third trench 25 is exposed. The first mask 28 covers an area larger than the first electrode 26a, so that the first dielectric layer 27a completely covers the first electrode 26a. In addition, when the first dielectric material layer 27 of the first area AA and the third area CC is dry-etched, the first dielectric material layer 27 located at the bottom of the first trench 23, the bottom of the third trench 25, the insulating layer 22 and the surface of the first electrode material layer 26 is removed, and the first electrode material layer 26 at the bottom of the first trench 23 and the third trench 25 is exposed, and the sidewalls of the first trench 23 and the third trench 25 may retain, partially retain or not retain the first dielectric material layer 27. In practice, taking the dry etching process to remove the first dielectric material layer 27 as an example, the first dielectric material layer 27 may be retained or partially retained on the sidewalls of the first trench 23 and the third trench 25 .

[0092] Please refer to Figure 3e , remove the first mask 28, and conformally form the second electrode material layer 29 and the second dielectric material layer 31 in sequence to cover the surface of the insulating layer 22, the inner walls of the first trench 23, the second trench 24, and the third trench 25, that is, to cover the surface of the insulating layer 22, the first region AA, the second region BB, and the third region CC. The material and thickness of the second electrode material layer 29 can refer to the material and thickness of the first electrode material layer 26, and the material and thickness of the second dielectric material layer 31 can refer to the material and thickness of the first dielectric material layer 27, which will not be described in detail here.

[0093] Please refer to Figure 3f, a second mask 30 is formed to cover the first area AA, the second area BB and the second dielectric material layer 31 therebetween, the exposed second dielectric material layer 31 and the second electrode material layer 29 thereunder are removed, the first area AA, the second area BB and the second electrode material layer 29 and the second dielectric material layer 31 therebetween are retained, the first area AA, the second area BB and the second electrode material layer 29 therebetween are used as the second electrode 29a, the first area AA, the second area BB and the second dielectric material layer 31 therebetween are used as the second dielectric layer 31a, the second electrode 29a is electrically connected to the first metal line 11, and the first electrode material layer 26 is exposed at the bottom of the third trench 25. The coverage area of ​​the second mask 30 is larger than the coverage area of ​​the first dielectric layer 27a (the first mask 28), so that the second electrode 29a completely covers the first dielectric layer 27a, and after the second electrode 29a and the second dielectric layer 31a are formed by etching, the surface of the second dielectric layer 31a and the sidewalls of the second dielectric layer 31a and the second electrode 29a are exposed. Taking dry etching as an example, the third region CC is exposed outside the second mask 30, so that the second electrode material layer 29 and the second dielectric material layer 31 on the insulating layer 22 and the bottom of the third trench 25 are removed, while the second electrode material layer 29 and the second dielectric material layer 31 on the sidewall of the third trench 25 are retained or partially retained, so that the first trench 23, the second trench 24 and the third trench 25 have the same film layer as much as possible, so as to facilitate the synchronous formation of corresponding structures.

[0094] Please refer to Figure 3g , remove the second mask 30, and form a third dielectric material layer 35 to conformally cover the surface of the insulating layer 22, the first trench 23, the second trench 24, and the inner wall of the third trench 25. Of course, the third dielectric material layer 35 also covers the sidewalls of the second electrode 29a and the second dielectric layer 31a. The material of the third dielectric material layer 35 can be any suitable single-layer or multi-layer dielectric material suitable for forming the sidewall 35a, such as silicon nitride, silicon oxide, etc. In a preferred example, the material of the third dielectric material layer 35 can be the same as that of the second dielectric layer 31a, and for example, a high dielectric constant dielectric, so as to facilitate etching and help increase the capacitance value.

[0095] Please refer to Figure 3h , an anisotropic dry etching process is performed to remove the surface of the insulating layer 22, the surface of the second dielectric layer 31a and the third dielectric material layer 35 at the bottom of the third trench 25, exposing the surface of the insulating layer 22, the surface of the second dielectric layer 31a and the first electrode material layer 26 at the bottom of the third trench 25, and the third dielectric material layer 35 retained on the sidewalls of the second electrode 29a and the second dielectric layer 31a is used as a sidewall 35a to isolate the second electrode 29a and the third electrode 33a, and to completely cover the second electrode 29a.

[0096] Please refer to Figure 3i , the third electrode material layer 33 is conformally formed to cover the surface of the insulating layer 22, the inner wall of the first groove 23, the second groove 24 and the third groove 25, that is, to cover the surface of the insulating layer 22, the first area AA, the second area BB and the third area CC. The material and thickness of the third electrode material layer 33 can refer to the material and thickness of the first electrode material layer 26. In practice, the thickness of the third electrode material layer 33 can also be greater than or equal to the thickness of the first electrode material layer 26 (or the second electrode material layer 29), so that the third electrode material layer 33 fills the first groove 23, the second groove 24 and the third groove 25.

[0097] Please refer to Figure 3j , form a third mask 32 to cover the first area AA, the second area BB, the third area CC and the third electrode material layer 33 therebetween, remove the exposed third electrode material layer 33, and use the first area AA, the second area BB, the third area CC and the third electrode material layer 33 therebetween as the third electrode 33a, and the third electrode 33a uses the first electrode material layer 26 at the bottom of the third trench 25 to electrically connect to the third metal wire 13.

[0098] Please refer to Figure 3k , and the third mask 32 is removed. Thus, a single-layer trench capacitor consisting of the second electrode 29a, the second dielectric layer 31a and the third electrode 33a is formed in the first area AA on the first metal line 11, and a double-layer trench capacitor consisting of the first electrode 26a, the first dielectric layer 27a, the second electrode 29a, the second dielectric layer 31a and the third electrode 33a is formed in the second area BB on the second metal line 12, and the second electrode 29a of the single-layer trench capacitor and the double-layer trench capacitor is electrically led downward through the first metal line 11, the first electrode 26a of the double-layer trench capacitor is electrically led downward through the second metal line 12, and the third electrode 33a of the single-layer trench capacitor and the double-layer trench capacitor is electrically led downward through the third trench 25. Moreover, a single-layer planar capacitor consisting of the second electrode 29a, the second dielectric layer 31a and the third electrode 33a is also formed in the area between the first area AA and the second area BB. The single-layer trench capacitor, the single-layer planar capacitor and the double-layer trench capacitor are connected in parallel, which can significantly increase the capacitance value on the same projection area of ​​the substrate 10, that is, the capacitance density.

[0099] The other manufacturing processes of this embodiment are similar to those of the first embodiment, and the details can be referred to the first embodiment, which will not be described in detail here.

[0100] Embodiment 3

[0101] Embodiment 3 provides a trench capacitor.

[0102] Figure 2m A schematic structural diagram of a trench capacitor provided in Example 3.

[0103] The trench capacitor provided in the third embodiment can be formed by using the manufacturing method provided in the first embodiment. Figure 2m As shown, the trench capacitor may include a substrate 10, first to third metal wires 11-13, an insulating layer 22, a double-layer capacitor, and a single-layer capacitor. Among them, the first to third metal wires 11-13 are arranged in the same layer in the substrate 10; the insulating layer 22 covers the first to third metal wires 11-13 and has a plurality of (at least one) first trenches 23 formed in the insulating layer 22 to expose the first metal wire 11, a plurality of (at least one) second trenches 24 to expose the second metal wire 12, and a plurality of (at least one) third trenches 25 to expose the third metal wire 13; a double-layer capacitor (double-layer trench capacitor) is formed on the insulating layer 22 (second region BB) in and around the second trench 24, including a first electrode 26a, a first dielectric layer 27a, a second electrode 29a, a second dielectric layer 31a, and a third dielectric layer 32a formed conformally in sequence. Electrode 33a, the first electrode 26a is electrically connected to the second metal line 12 by the second groove 24, the second electrode 29a is electrically connected to the first metal line 11 by the first groove 23, and the third electrode 33a is electrically connected to the third metal line 13 by the third groove 25; a single-layer capacitor (single-layer trench capacitor) is formed on the insulating layer 22 (first area AA) in and around the first groove 23, including the second electrode 29a, the second dielectric layer 31a and the third electrode 33a formed in sequence conformally, which is in parallel with the double-layer capacitor of the second area BB, that is, they share the second electrode 29a, the second dielectric layer 31a and the third electrode 33a of the double-layer capacitor. Moreover, a single-layer planar capacitor composed of the second electrode 29a, the second dielectric layer 31a and the third electrode 33a can also be formed in the area between the first groove 23 and the second groove 24 (the area between the first area AA and the second area BB). The first dielectric layer 27a completely covers the first electrode 26a (including its surface and sidewalls) and the second dielectric layer 31a completely covers the second electrode 29a (including its surface and sidewalls), thereby achieving better electrical isolation among the first electrode 26a, the second electrode 29a and the third electrode 33a.

[0104] In addition, in other examples provided in this embodiment, such as Figure 3k As shown, the trench capacitor can also be formed by the manufacturing method provided in the second embodiment. The difference between the trench capacitor and the aforementioned trench capacitor is that the second dielectric layer 31a only covers the surface of the second electrode 29a but does not cover the side wall of the second electrode 29a, that is, the edges of the second electrode 29a, the second dielectric layer 31a and the third electrode 33a form a vertical or nearly vertical step, thereby forming a side wall 35a covering the side wall (step) of the second electrode 29a and the second dielectric layer 31a for electrically isolating the second electrode 29a from the third electrode 33a.

[0105] In summary, the present invention forms a first trench exposing the first metal wire in the insulating layer on the first metal wire, forms a second trench exposing the second metal wire in the insulating layer on the second metal wire, and forms a third trench exposing the third metal wire in the insulating layer on the third metal wire, and forms a single-layer capacitor in the first trench and on the insulating layer around the first trench, and forms a double-layer capacitor in the second trench and in the insulating layer around the second trench, the single-layer trench capacitor and the double-layer trench capacitor are connected in parallel, the single-layer trench capacitor is directly formed by using the second electrode, the second dielectric layer and the third electrode of the double-layer trench capacitor, and in the two capacitors, the second dielectric layer is formed by using the second electrode, the second dielectric layer and the third electrode of the double-layer trench capacitor. An electrode is connected to a second metal wire at the bottom of the second trench by using a second trench, a second electrode is connected to a first metal wire at the bottom of the first trench by using a first trench, and a third electrode is connected to a third metal wire at the bottom of the third trench by using a third trench. Thus, the first to third electrodes of the double-layer capacitor and the second to third electrodes of the single-layer capacitor are led downward by using the first to third metal wires in the substrate, and the lead-out of the double-layer trench capacitor and the wiring of the metal wires on the insulating layer are realized without adding additional process steps, thereby increasing the capacitance density of the trench capacitor, reducing the difficulty of process integration, and being conducive to improving the degree of freedom of trench capacitor design.

[0106] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a trench capacitor, characterized in that: include: Providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed in the substrate; forming a first trench in the insulating layer to expose the first metal line, a second trench to expose the second metal line, and a third trench to expose the third metal line; A single-layer capacitor is formed on the first groove and the insulating layer around it, and a double-layer capacitor is formed on the second groove and the insulating layer around it, the double-layer capacitor includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode formed in sequence conformally, the single-layer capacitor includes the second electrode, the second dielectric layer and the third electrode formed in sequence conformally, the first electrode is electrically connected to the second metal wire using the second groove, the second electrode is electrically connected to the first metal wire using the first groove, and the third electrode is electrically connected to the third metal wire using the third groove.

2. The method for manufacturing a trench capacitor according to claim 1, wherein: A dielectric barrier layer is also provided between the first to third metal wires and the insulating layer.

3. The method for manufacturing a trench capacitor according to claim 1, wherein: The insulating layer includes a first region located above the first metal line, a second region located above the second metal line, and a third region located above the third metal line, the first region is provided with the first groove, the second region is provided with the second groove, and the third region is provided with the third groove, and the steps of forming the single-layer capacitor and the double-layer capacitor include: Forming a first electrode material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; Performing a patterning process on the first electrode material layer, retaining the first electrode material layers in the first region, the second region and the third region, and using the first electrode material layer in the second region as the first electrode, the first electrode being electrically connected to the second metal wire, the first electrode material layer in the first trench being electrically connected to the first metal wire, and the first electrode material layer in the third trench being electrically connected to the third metal wire; Forming a first dielectric material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; Forming a first mask to cover the first dielectric material layer in the second area, and performing an etching process to remove the exposed first dielectric material layer, using the first dielectric material layer in the second area as the first dielectric layer, and exposing the first electrode material layer at the bottom of the first trench and the bottom of the third trench; Removing the first mask, and forming a second electrode material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; forming a second mask to cover the first region, the second region and the second electrode material layer therebetween, removing the exposed second electrode material layer, using the first region, the second region and the second electrode material layer therebetween as the second electrode, the second electrode being electrically connected to the first electrode material layer of the first trench and the first metal line, and exposing the first electrode material layer at the bottom of the third trench; Removing the second mask, and conformally forming a second dielectric material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; forming a third mask to cover the first region, the second region and the second dielectric material layer therebetween, removing the exposed second dielectric material layer, using the first region, the second region and the second dielectric material layer therebetween as the second dielectric layer, and exposing the first electrode material layer at the bottom of the third trench, wherein the third mask completely covers the second electrode; Removing the third mask, and conformally forming a third electrode material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; forming a fourth mask to cover the first region, the second region, the third region and the third electrode material layer therebetween, removing the exposed third electrode material layer, using the first region, the second region, the third region and the third electrode material layer therebetween as the third electrode, the third electrode being electrically connected to the first electrode material layer of the third trench and the third metal line; The fourth mask is removed.

4. The method for manufacturing a trench capacitor according to claim 1, wherein: The insulating layer includes a first region located above the first metal line, a second region located above the second metal line, and a third region located above the third metal line, the first region is provided with the first groove, the second region is provided with the second groove, and the third region is provided with the third groove, and the steps of forming the single-layer capacitor and the double-layer capacitor include: Forming a first electrode material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; Performing a patterning process on the first electrode material layer, retaining the first electrode material layers in the first region, the second region and the third region, and using the first electrode material layer in the second region as the first electrode, the first electrode being electrically connected to the second metal wire, the first electrode material layer in the first trench being electrically connected to the first metal wire, and the first electrode material layer in the third trench being electrically connected to the third metal wire; Forming a first dielectric material layer to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; Forming a first mask to cover the first dielectric material layer in the second area, and performing an etching process to remove the exposed first dielectric material layer, using the first dielectric material layer in the second area as the first dielectric layer, and exposing the first electrode material layer at the bottom of the first trench and the bottom of the third trench; Removing the first mask, and conformally forming a second electrode material layer and a second dielectric material layer in sequence to cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; forming a second mask to cover the first region, the second region and the second dielectric material layer therebetween, removing the exposed second dielectric material layer and the second electrode material layer thereunder, retaining the first region, the second region and the second electrode material layer and the second dielectric material layer therebetween, so as to form the second electrode and the second dielectric layer, wherein the second electrode is electrically connected to the first electrode material layer of the first trench and the first metal line, and exposing the first electrode material layer at the bottom of the third trench; removing the second mask and forming a third dielectric material layer to conformally cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; Performing an anisotropic dry etching process to remove the exposed third dielectric material layer, and using the third dielectric material layer retained on the second electrode and the sidewall of the second dielectric layer as a sidewall, and exposing the first electrode material layer at the bottom of the third trench; forming a third electrode material layer to conformally cover the surface of the insulating layer, the first trench, the second trench, and the inner wall of the third trench; forming a third mask to cover the first region, the second region, the third region and the third electrode material layer therebetween, removing the exposed third electrode material layer, using the first region, the second region, the third region and the third electrode material layer therebetween as the third electrode, the third electrode being electrically connected to the first electrode material layer of the third trench and the third metal line; The third mask is removed.

5. The method for manufacturing a trench capacitor according to claim 3 or 4, characterized in that: A single-layer planar capacitor composed of the second electrode, the second dielectric layer and the third electrode is also formed between the first region and the second region.

6. The method for manufacturing a trench capacitor according to claim 3 or 4, characterized in that: The materials of the first electrode, the second electrode and the third electrode include one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

7. The method for manufacturing a trench capacitor according to claim 3 or 4, characterized in that: The dielectric constants of the first dielectric layer and the second dielectric layer are greater than or equal to 3.

9.

8. The method for manufacturing a trench capacitor according to claim 4, wherein: The material of the third dielectric material layer is the same as that of the second dielectric layer.

9. A trench capacitor, characterized in that: include: substrate; First to third metal wires are arranged in the same layer in the substrate; an insulating layer, covering the first to third metal wires and having a first trench formed therein to expose the first metal wire, a second trench to expose the second metal wire, and a third trench to expose the third metal wire; A double-layer capacitor is formed in the second groove and on the insulating layer around it, comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode which are sequentially formed conformally, wherein the first electrode is electrically connected to the second metal line by using the second groove, and the third electrode is electrically connected to the third metal line by using the third groove; A single-layer capacitor is formed in the first groove and on the insulating layer around it, and includes the second electrode, the second dielectric layer and the third electrode which are formed conformally in sequence. The second electrode is electrically connected to the first metal wire by using the first groove.

10. The trench capacitor according to claim 9, wherein: A single-layer planar capacitor is also provided, which is provided on the insulating layer between the first metal wire and the second metal wire and is composed of the second electrode, the second dielectric layer and the third electrode.

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