Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a substrate, and forming a first metal wire, a second metal wire and an insulating layer in the substrate; forming a plurality of grooves in the insulating layer; forming a first electrode at least covering the groove and the insulating layer at the periphery of the groove; forming a first dielectric layer and a second electrode to conformally cover the groove and the first electrode at the periphery of the groove, and exposing part of the first electrode; forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the groove; and forming a plurality of through holes in the second dielectric layer and the insulating layer, forming a third metal wire electrically connected with the first metal wire and the first electrode, and forming a fourth metal wire electrically connected with the second metal wire and the second electrode. According to the semiconductor device, the two electrodes of the capacitor in the semiconductor device are led out downwards through the first metal wire and the second metal wire in the substrate, the process integration difficulty is lowered, and the freedom degree of design of the capacitor in the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Capacitors are a common passive component widely used in semiconductor devices. In some special applications, capacitors with large unit capacitance are needed to improve product performance, such as storing signals, reducing noise, and reducing coupling. Planar capacitors need to occupy a large area to obtain large capacitance, which will sacrifice design area. For this reason, trench capacitors become the best choice for large capacitors.

[0003] In the related art, the electrodes of the capacitors in the semiconductor devices are usually electrically led upwards, and the grooves thereof need to be filled with metal, which results in the structure and process of the electrically led trench capacitors being more complicated and not conducive to the design of the capacitors in the semiconductor devices. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to optimize the structure and manufacturing process of a trench capacitor.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a substrate, wherein a first metal line and a second metal line arranged in the same layer and an insulating layer covering the first metal line and the second metal line are formed in the substrate;

[0007] forming a plurality of grooves in the insulating layer between the first metal line and the second metal line;

[0008] forming a first electrode at least covering the trench and an insulating layer around the trench;

[0009] Forming a first dielectric layer and a second electrode to conformally cover the trench and the first electrode around the trench, and exposing a portion of the first electrode;

[0010] forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench;

[0011] A plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first metal line, the second metal line, the first electrode and the second electrode, a third metal line is formed to electrically connect the first metal line and the first electrode, and a fourth metal line is formed to electrically connect the second metal line and the second electrode.

[0012] Optionally, a capacitor region is provided on the insulating layer between the first metal wire and the second metal wire, a plurality of the grooves are formed in the capacitor region, and the step of forming the first electrode includes:

[0013] forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the groove;

[0014] Forming a first mask to cover the capacitor region and a first electrode material layer in a partial region close to one side of the first metal line;

[0015] Using the first mask, etching away the exposed first electrode material layer, and using the remaining first electrode material layer as the first electrode;

[0016] The first mask is removed.

[0017] Optionally, the step of forming the first dielectric layer and the second electrode includes:

[0018] forming a first dielectric material layer and a second electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode;

[0019] Forming a second mask to cover the capacitor region and a second electrode material layer in a partial region near one side of the second metal line, and the second mask to expose a portion of the second electrode material layer located on the first electrode;

[0020] Using the second mask, performing a dry etching process to sequentially remove the exposed second electrode material layer and the first dielectric material layer, using the remaining second electrode material layer as the second electrode and the remaining first dielectric material layer as the first dielectric layer, and exposing a portion of the surface of the first electrode;

[0021] The second mask is removed.

[0022] Optionally, the step of forming a plurality of through holes includes:

[0023] Forming a plurality of first through holes in the second dielectric layer to expose the first electrode and the second electrode respectively;

[0024] A plurality of second through holes are formed in the insulating layer and the second dielectric layer to expose the first metal line and the second metal line respectively.

[0025] Optionally, the step of forming the third metal line and the fourth metal line includes:

[0026] forming a metal material layer to cover the surface of the second dielectric layer, the first through hole and the inner wall of the second through hole;

[0027] A patterning process is performed on the metal material layer to form the third metal line electrically connecting the first metal line and the first electrode, and to form the fourth metal line electrically connecting the second metal line and the second electrode.

[0028] Optionally, a capacitor region is provided on the insulating layer between the first metal wire and the second metal wire, a plurality of the grooves are formed in the capacitor region, and the step of forming the first electrode includes:

[0029] forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the groove;

[0030] Forming a first mask to cover the capacitor region to a first electrode material layer above the first metal line;

[0031] Using the first mask, etching away the exposed first electrode material layer, and using the first electrode material layer from the capacitor region to above the first metal line as the first electrode, wherein the first electrode extends from the capacitor region to above the first metal line;

[0032] The first mask is removed.

[0033] Optionally, the step of forming the first dielectric layer and the second electrode includes:

[0034] forming a first dielectric material layer and a second electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode;

[0035] forming a second mask covering the capacitor region to a second electrode material layer above the second metal line;

[0036] Using the second mask, performing a dry etching process to sequentially remove the exposed second electrode material layer and the first dielectric material layer, using the remaining second electrode material layer as the second electrode, and the remaining first dielectric material layer as the first dielectric layer, wherein the second electrode extends from the capacitor region to above the second metal line;

[0037] The second mask is removed.

[0038] Optionally, the step of forming the plurality of through holes, the third metal wire and the fourth metal wire comprises:

[0039] Forming a plurality of through holes penetrating the insulating layer, the second dielectric layer, the first electrode, and the second electrode, so as to expose the first metal wire and the second metal wire at the bottom walls of the plurality of through holes, and to expose the first electrode and the second electrode at the side walls of the plurality of through holes;

[0040] forming a metal material layer to cover the surface of the second dielectric layer and the inner wall of the through hole;

[0041] A patterning process is performed on the metal material layer to form the third metal line electrically connecting the first metal line and the first electrode, and to form the fourth metal line electrically connecting the second metal line and the second electrode.

[0042] Optionally, when the patterning process is performed on the metal material layer, a metal pad is also simultaneously formed on the surface of the insulating layer for connection with an external circuit.

[0043] According to another aspect of the present invention, there is also provided a semiconductor device, comprising:

[0044] substrate;

[0045] A first metal line and a second metal line are arranged in the substrate in the same layer;

[0046] an insulating layer, covering the first metal line and the second metal, wherein a plurality of grooves are formed in the insulating layer;

[0047] A capacitor formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer and a second electrode formed conformally in sequence;

[0048] A second dielectric layer covers the capacitor, and a plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first electrode, the second electrode, the first metal wire, and the second metal wire respectively;

[0049] A third metal wire and a fourth metal wire, wherein the third metal wire electrically connects the first metal wire and the first electrode by using the through hole, and the fourth metal wire electrically connects the second metal wire and the second electrode by using the through hole.

[0050] In summary, the present invention has a plurality of grooves in the insulating layer between the first metal wire and the second metal wire, and forms a capacitor in the groove and on the insulating layer around the groove, the capacitor includes a first electrode, a first dielectric layer and a second electrode which are formed conformally in sequence, the first electrode and the second electrode respectively extend to both sides of the trench capacitor and are both exposed upward, then a second dielectric layer is formed to cover the capacitor and the insulating layer, and through holes are formed in the second dielectric layer and the insulating layer to respectively expose the first metal wire, the second metal wire, the first electrode and the second electrode, then a third metal wire is formed by the through hole to electrically connect the first electrode and the first metal wire, and a fourth metal wire is formed to electrically connect the second electrode and the second metal wire, thereby the two electrodes of the capacitor in the semiconductor device are led downward by the first metal wire and the second metal wire in the substrate, the lead-out of the capacitor in the semiconductor device and the wiring of the metal wire on the insulating layer are completed without adding additional process steps, the difficulty of process integration is reduced, and it is beneficial to improve the capacitance density and design freedom of the capacitor in the semiconductor device. In addition, compared with the related art where trench capacitors require metal to fill the trenches, the two electrodes of the trench capacitor in this embodiment extend to both sides to achieve electrical lead-out and do not need to be filled with metal, that is, voids are allowed to exist, which is beneficial to improving the freedom of capacitor design in semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0052] Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided in Embodiment 1;

[0053] Figure 2a to Figure 2m A schematic structural diagram corresponding to corresponding steps of the method for manufacturing a semiconductor device provided in Embodiment 1;

[0054] Figure 3a to Figure 3l This is a schematic structural diagram corresponding to the corresponding steps of the method for manufacturing a semiconductor device provided in the second embodiment.

[0055] In the attached figure:

[0056] 10-substrate; 11-first metal wire; 12-second metal wire; AA-capacitor area; BB-first extension area; CC-second extension area; 21-dielectric barrier layer; 22-insulating layer; 23-groove; 24-first electrode material layer; 24a-first electrode; 25-first mask; 26-first dielectric material layer; 26a-first dielectric layer; 27-second electrode material layer; 27a-second electrode; 28-second mask; 31-second dielectric layer; 32-first through hole; 33-second through hole; 34-metal material layer; 35-third metal wire; 36-fourth metal wire. DETAILED DESCRIPTION

[0057] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0058] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0059] Embodiment 1

[0060] Figure 1 It is a flow chart of a method for manufacturing a semiconductor device provided in the first embodiment.

[0061] like Figure 1 As shown, the method for manufacturing a semiconductor device provided in this embodiment includes:

[0062] S01: providing a substrate, wherein a first metal wire and a second metal wire arranged in the same layer and an insulating layer covering the first metal wire and the second metal wire are formed on the substrate;

[0063] S02: forming a plurality of grooves in the insulating layer between the first metal line and the second metal line;

[0064] S03: forming a first electrode to at least cover the trench and an insulating layer around the trench;

[0065] S04: forming a first dielectric layer and a second electrode to conformally cover the trench and the first electrode around the trench, and exposing a portion of the first electrode;

[0066] S05: forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench;

[0067] S06: forming a plurality of through holes in the second dielectric layer and the insulating layer to expose the first metal wire, the second metal wire, the first electrode and the second electrode, forming a third metal wire to electrically connect the first metal wire and the first electrode, and forming a fourth metal wire to electrically connect the second metal wire and the second electrode.

[0068] Figure 2a to Figure 2m The structural schematic diagram corresponding to the corresponding steps of the semiconductor device manufacturing method provided in this embodiment, next, Figure 2a to Figure 2m A method for manufacturing the semiconductor device is described in detail.

[0069] First, please refer to Figure 2a , perform step S01, provide a substrate 10, and form a first metal wire 11, a second metal wire 12 arranged in the same layer, and an insulating layer 22 covering the first metal wire 11 and the second metal wire 12 on the substrate 10.

[0070] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, and germanium on insulator, etc. In this embodiment, the material of the substrate 10 is described by taking silicon (silicon substrate) as an example.

[0071] A device layer and an interconnection layer electrically connected to the device layer are formed in the substrate 10. The interconnection layer is located above the device layer and can be formed by a Damascus process. The first metal wire 11 and the second metal wire 12 can be two metal wirings arranged at intervals in the Nth layer (N is greater than or equal to 1) in the interconnection layer, and the material thereof can include, for example, copper. In the present embodiment, the first metal wire 11 and the second metal wire 12 can be two top-layer metal wirings arranged at intervals. A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed on the first metal wire 11 and the second metal wire 12. The material of the dielectric barrier layer 21 is used to block the escape of metal ions and serve as an etching stop layer during etching. The material thereof can include, for example, silicon nitride or silicon carbonitride, and the material of the insulating layer 22 is different from that of the dielectric barrier layer 21, and can include, for example, silicon oxide or silicon oxynitride.

[0072] In addition, in other examples of this embodiment, as needed, multiple (at least two) first metal wires 11 and multiple second metal wires 12 can be set, and multiple identical metal wires are connected in parallel; other metal wires can also be arranged between the first metal wire 11 and the second metal wire 12.

[0073] Next, please refer to Figure 2b , performing step S02 to form a plurality of trenches 23 in the insulating layer 22 between the first metal line 11 and the second metal line 12 .

[0074] Specifically, a photolithography process may be used to define a plurality of openings on the insulating layer 22 between the first metal line 11 and the second metal line 12, and then the dielectric barrier layer 21 is used as an etching stop layer, and a dry etching process is performed to etch the insulating layer 22 to form a plurality of grooves 23 arranged at intervals, and expose the surface of the dielectric barrier layer 21. Among them, the region where the plurality of grooves 23 and the insulating layer 22 around them are located may be a capacitor region AA, which is used to subsequently form a single-layer trench capacitor thereon. Of course, in other examples of this embodiment, the groove 23 may not penetrate the insulating layer 22.

[0075] In addition, as required, the capacitor area AA may also extend into the insulating layer 22 on the first metal line 11 and / or the second metal line 12 , that is, a groove 23 may be formed in the insulating layer 22 on the first metal line 11 and / or the second metal line 12 .

[0076] Next, step S03 is performed to form a first electrode 24 a to at least cover the trench 23 and the insulating layer 22 around the trench 23 .

[0077] For details, please refer to Figure 2c , forming a first electrode material layer 24 to conformally cover the surface of the insulating layer 22 and the inner wall of the groove 23. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 24, which may include one or more thin film conductive layers, and its material may include, for example, one or more of titanium, titanium nitride, tantalum or tantalum nitride, and its formation process may include physical vapor deposition, chemical vapor deposition or atomic layer deposition, and the thickness of the first electrode material layer 24 may be, for example, 100 angstroms to 400 angstroms.

[0078] Please refer to Figure 2d , forming a first mask 25 to at least cover the capacitor area AA. Preferably, the first mask 25 can also appropriately extend to cover the portion of the insulating layer 22 near the edge of the capacitor area AA (e.g., the first extension area BB) to facilitate subsequent electrical lead-out. However, it should be noted that the first extension area BB cannot extend above the first metal line 11. In this embodiment, the first extension area BB is located on the side of the capacitor area AA close to the first metal line 11.

[0079] Please refer to Figure 2e , using the first mask 25, the exposed first electrode material layer 24 is etched away, and the remaining first electrode material layer 24 is used as the first electrode 24a, and then the first mask 25 is removed. The first electrode 24a conformally covers the inner wall of the trench 23 and the surface of the insulating layer 22 in the capacitor area AA, and also covers the insulating layer 22 in the first extension area BB.

[0080] Next, step S04 is performed to form a first dielectric layer 26a and a second electrode 27a to conformally cover the trench 23 and the first electrode 24a around the trench 23, and expose a portion of the first electrode 24a.

[0081] For details, please refer to Figure 2f , a first dielectric material layer 26 and a second electrode material layer 27 are sequentially conformally formed to cover the surfaces of the insulating layer 22 and the first electrode 24a. The material of the first dielectric material layer 26 may be a dielectric material with a relatively high dielectric constant, and its dielectric constant may be, for example, greater than or equal to 3.9, and its material may be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide; the material of the second electrode material layer 27 may be similar to that of the first electrode material layer 24.

[0082] Please refer to Figure 2g , forming a second mask 28 to at least cover the second electrode material layer 27 of the capacitor area AA, and the second mask 28 exposes a portion of the second electrode material layer 27 located on the first electrode 24a. The second mask 28 covers the second electrode material layer 27 of the capacitor area AA, and at least partially exposes the second electrode material layer 27 of the first extension area BB, that is, at least partially exposes the second electrode material layer 27 on the first electrode 24a. It is also preferred to cover a portion of the second electrode material layer 27 located on the other side of the capacitor area AA relative to the first extension area BB (the second extension area CC) to facilitate subsequent electrical extraction. Similar to the first extension area BB, the second extension area CC cannot extend above the second metal line 12.

[0083] Please refer to Figure 2h , using the second mask 28, a dry etching process is performed to remove the exposed second electrode material layer 27 and the first dielectric material layer 26 in turn, using the remaining second electrode material layer 27 as the second electrode 27a, and the remaining first dielectric material layer 26 as the first dielectric layer 26a, exposing the surface of a portion (first extension area BB) of the first electrode 24a, and then removing the second mask 28.

[0084] Thus, a single-layer trench capacitor consisting of a first electrode 24a, a first dielectric layer 26a and a second electrode 27a is formed on the insulating layer 22 in the trench 23 and on the periphery of the trench 23 (capacitor area AA) to increase the capacitance value (capacitance density) on the same substrate area.

[0085] Next, please refer to Figure 2i , step S05 is executed to form a second dielectric layer 31 covering the insulating layer 22 , the first electrode 24 a , the second electrode 27 a and the trench 23 .

[0086] Among them, the second dielectric layer 31 may include a single-layer dielectric or a multi-layer dielectric, and its material may include suitable insulating materials such as silicon oxide, silicon nitride, silicon carbide or silicon oxynitride, and may be formed by a suitable process including chemical vapor deposition or atomic layer deposition. In addition to covering the insulating layer 22, the first electrode 24a and the second electrode 27a, the second dielectric layer 31 also fills the groove 23. Compared with the use of electrode materials to fill the groove 23 used to form the capacitor in the related art, the second dielectric layer 31 is used to fill the groove 23 in this embodiment, which is not only conducive to saving electrode materials, but also provides greater freedom for the design of capacitors in semiconductor devices. It should be understood that the single-layer trench capacitor in this embodiment does not lead the electrode out of the trench 23, so it is not necessary to use electrode materials to fill the trench 23, that is, in this embodiment, voids are allowed in the single-layer trench capacitor (the second dielectric layer can be used to fill the void later).

[0087] Next, step S06 is performed to form a plurality of through holes in the second dielectric layer 31 and the insulating layer 22 to expose the first metal line 11, the second metal line 12, the first electrode 24a and the second electrode 27a, and to form a third metal line 35 to electrically connect the first metal line 11 and the first electrode 24a, and to form a fourth metal line 36 to electrically connect the second metal line 12 and the second electrode 27a.

[0088] For details, please refer to Figure 2j , a plurality of first through holes 32 are formed in the second dielectric layer 31 to expose the first electrode 24a and the second electrode 27a respectively. Part of the first through holes 32 are located in the second dielectric layer 31 on the first extension region BB to expose one of the first electrode 24a and the second electrode 27a, and another part of the first through holes 32 are located in the second dielectric layer 31 on the second extension region CC to expose the other of the first electrode 24a and the second electrode 27a. In this embodiment, the first through holes 32 close to the first metal line 11 can expose the first electrode 24a, and the first through holes 32 close to the second metal line 12 can expose the second electrode 27a.

[0089] Please refer to Figure 2k , a plurality of second through holes 33 are formed in the insulating layer 22 and the second dielectric layer 31 to expose the first metal line 11 and the second metal line 12 respectively. Part of the second through holes 33 may be located above the first metal line 11 to expose the first metal line 11, and another part of the second through holes 33 may be located above the second metal line 12 to expose the second metal line 12. In this embodiment, the second through holes 33 also penetrate the dielectric barrier layer 21 under the insulating layer 22, and when etching to form the second through holes 33, the dielectric barrier layer 21 may also serve as an etching stop layer for etching the second dielectric layer 31 and the insulating layer 22 to reduce damage to the metal lines.

[0090] Please refer to Figure 2l, forming a metal material layer 34 to cover the surface of the second dielectric layer 31, the inner wall of the first through hole 32 and the second through hole 33. The metal material layer 34 may be a metal material suitable for connection with an external circuit, such as aluminum or an aluminum alloy. In the present embodiment, the material of the first metal wire 11 and the second metal wire 12 includes copper, and the metal material layer 34 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer and a titanium nitride layer formed in sequence conformally. In practice, since the size (depth and opening width) of the first through hole 32 is small and the size of the second through hole 33 is large, the metal material layer 34 may fill the first through hole 32, and the metal material layer 34 may only cover the inner wall of the second through hole 33 without filling the second through hole 33.

[0091] Please refer to Figure 2m , a patterning process is performed on the metal material layer 34 to form a third metal line 35 connecting the first metal line 11 and the first electrode 24a and a fourth metal line 36 connecting the second metal line 12 and the second electrode 27a. Specifically, the patterning process of the metal material layer 34 includes disconnecting the metal material layer 34 connecting the two sides of the capacitor area AA, using the metal material layer 34 covering the second through hole 33 on the first metal line 11 to the first through hole 32 close to the first metal line 11 as the third metal line 35, and using the metal material layer 34 covering the second through hole 33 on the second metal line 12 to the first through hole 32 close to the second metal line 12 as the fourth metal line 36.

[0092] In addition, during the process of performing the patterning process on the metal material layer 34, the metal material layer 34 can also be used to simultaneously form a metal pad on the second dielectric layer 31, and other top-layer metal lines can be electrically led out to the metal pad for connection with an external circuit. In other words, the electrical lead-out (downward lead-out) of the single-layer trench capacitor of this embodiment can be achieved in the step of forming the metal pad, and no additional device structure and process steps are required.

[0093] It is worth mentioning that in other examples of this embodiment, the first extension area BB can also be located on the side of the capacitor area AA away from the first metal line 11, and the second extension CC is located on the side of the capacitor area AA away from the second metal line 12, so that a portion of the first electrode 24a in the single-layer capacitor is exposed to the side close to the second metal line 12, and the formed third metal line is electrically connected to the first metal line and the second electrode, and the fourth metal line is electrically connected to the second metal line and the first electrode.

[0094] Embodiment 2

[0095] Figure 1 It is a flow chart of a method for manufacturing a semiconductor device provided in the second embodiment.

[0096] like Figure 1 As shown, the method for manufacturing a semiconductor device provided in this embodiment includes:

[0097] S01: providing a substrate, wherein a first metal wire and a second metal wire arranged in the same layer and an insulating layer covering the first metal wire and the second metal wire are formed on the substrate;

[0098] S02: forming a plurality of grooves in the insulating layer between the first metal line and the second metal line;

[0099] S03: forming a first electrode to at least cover the trench and an insulating layer around the trench;

[0100] S04: forming a first dielectric layer and a second electrode to conformally cover the trench and the first electrode around the trench, and exposing a portion of the first electrode;

[0101] S05: forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench;

[0102] S06: forming a plurality of through holes in the second dielectric layer and the insulating layer to expose the first metal wire, the second metal wire, the first electrode and the second electrode, forming a third metal wire to electrically connect the first metal wire and the first electrode, and forming a fourth metal wire to electrically connect the second metal wire and the second electrode.

[0103] Figure 3a to Figure 3l The structural schematic diagram corresponding to the corresponding steps of the semiconductor device manufacturing method provided in this embodiment, next, Figure 3a to Figure 3l A method for manufacturing the semiconductor device is described in detail.

[0104] First, please refer to Figure 3a , perform step S01, provide a substrate 10, and form a first metal wire 11, a second metal wire 12 arranged in the same layer, and an insulating layer 22 covering the first metal wire 11 and the second metal wire 12 on the substrate 10.

[0105] Next, please refer to Figure 3b , performing step S02 to form a plurality of trenches 23 in the insulating layer 22 between the first metal line 11 and the second metal line 12 .

[0106] Next, step S03 is performed to form a first electrode 24 a to at least cover the trench 23 and the insulating layer 22 around the trench 23 .

[0107] For details, please refer to Figure 3c, forming a first electrode material layer 24 to conformally cover the surface of the insulating layer 22 and the inner wall of the groove 23. Any suitable process can be used to form a thin film conductive layer as the first electrode material layer 24, which may include one or more thin film conductive layers, and its material may include, for example, one or more of titanium, titanium nitride, tantalum or tantalum nitride, and its formation process may include physical vapor deposition, chemical vapor deposition or atomic layer deposition, and the thickness of the first electrode material layer 24 may be, for example, 100 angstroms to 400 angstroms.

[0108] Please refer to Figure 3d , a first mask 25 is formed to cover the capacitor area AA to the first electrode material layer 24 above the first metal line 11. The first mask 25 covers the first electrode material layer 24 in the capacitor area AA, and also extends to cover the first electrode material layer 24 above the first metal line 11, that is, includes the first electrode material layer 24 between the capacitor area AA and the first metal line 11 and the first electrode material layer 24 on the first metal line 11.

[0109] Please refer to Figure 3e , using the first mask 25, the exposed first electrode material layer 24 is etched away, and the remaining first electrode material layer 24 is used as the first electrode 24a, and then the first mask 25 is removed. The first electrode 24a conformally covers the inner wall of the trench 23 of the capacitor area AA and the surface of the insulating layer 22, and extends to cover the insulating layer 22 above the first metal line 11.

[0110] Next, step S04 is performed to form a first dielectric layer 26a and a second electrode 27a to conformally cover the trench 23 and the first electrode 24a around the trench 23, and expose a portion of the first electrode 24a.

[0111] For details, please refer to Figure 3f , a first dielectric material layer 26 and a second electrode material layer 27 are sequentially conformally formed to cover the surfaces of the insulating layer 22 and the first electrode 24a. The material of the first dielectric material layer 26 may be a dielectric material with a relatively high dielectric constant, and its dielectric constant may be, for example, greater than or equal to 3.9, and its material may be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide; the material of the second electrode material layer 27 may be similar to that of the first electrode material layer 24.

[0112] Please refer to Figure 3g , a second mask 28 is formed to cover the capacitor area AA to the second electrode material layer 27 above the second metal line 12. The second mask 28 covers the second electrode material layer 27 in the capacitor area AA, and also extends to cover the second electrode material layer 27 above the second metal line 12, that is, includes the second electrode material layer 27 between the capacitor area AA and the second metal line 12 and the second electrode material layer 27 on the second metal line 12.

[0113] Please refer to Figure 3h , using the second mask 28, performing a dry etching process, removing the exposed second electrode material layer 27 and the first dielectric material layer 26 in turn, using the remaining second electrode material layer 27 as the second electrode 27a, and the remaining first dielectric material layer 26 as the first dielectric layer 26a, and then removing the second mask 28.

[0114] Thus, a single-layer trench capacitor consisting of the first electrode 24a, the first dielectric layer 26a and the second electrode 27a is formed on the insulating layer 22 in the trench 23 and on the periphery of the trench 23 (capacitor region AA), so as to increase the capacitance value (capacitance density) on the same substrate area. Moreover, the first electrode 24a extends from the capacitor region AA to the top of the first metal line 11, and the second electrode 27a extends from the capacitor region AA to the top of the second metal line 12, so that the first electrode 24a and the second electrode 27a are exposed for subsequent electrical extraction.

[0115] Next, please refer to Figure 3i , step S05 is executed to form a second dielectric layer 31 covering the insulating layer 22 , the first electrode 24 a , the second electrode 27 a and the trench 23 .

[0116] Among them, the second dielectric layer 31 may include a single-layer dielectric or a multi-layer dielectric, and its material may include suitable insulating materials such as silicon oxide, silicon nitride, silicon carbide or silicon oxynitride, and may be formed by a suitable process including chemical vapor deposition or atomic layer deposition. In addition to covering the insulating layer 22, the first electrode 24a and the second electrode 27a, the second dielectric layer 31 also fills the groove 23. Compared with the use of electrode materials to fill the groove 23 used to form the capacitor in the related art, the second dielectric layer 31 is used to fill the groove 23 in this embodiment, which is not only conducive to saving electrode materials, but also provides greater freedom for the design of the trench capacitor. It should be understood that the single-layer trench capacitor in this embodiment does not lead the electrode out of the trench 23, so it is not necessary to use electrode materials to fill the trench 23, that is, in this embodiment, voids are allowed in the single-layer trench capacitor (the second dielectric layer can be used to fill the void later).

[0117] Next, step S06 is performed to form a plurality of through holes in the second dielectric layer 31 and the insulating layer 22 to expose the first metal line 11, the second metal line 12, the first electrode 24a and the second electrode 27a, and to form a third metal line 35 to electrically connect the first metal line 11 and the first electrode 24a, and to form a fourth metal line 36 to electrically connect the second metal line 12 and the second electrode 27a.

[0118] For details, please refer to Figure 3j, forming a plurality of through holes (second through holes 33) penetrating the insulating layer 22, the second dielectric layer 31, the first electrode 24a and the second electrode 27a, so as to expose the first metal line 11 and the second metal line 12 at the bottom walls of the plurality of second through holes 33, and to expose the first electrode 24a and the second electrode 27a at the side walls of the plurality of second through holes 33. That is, forming a plurality of second through holes 33 penetrating the dielectric barrier layer 21, the insulating layer 22, the first electrode 24a and the second dielectric layer 31 above the first metal line 11, so as to expose the first metal line 11 at the bottom wall of the second through hole 33, and to expose the first electrode 24a at the side wall of the second through hole 33. Similarly, forming a plurality of second through holes 33 penetrating the dielectric barrier layer 21, the insulating layer 22, the second electrode 27a and the second dielectric layer 31 above the second metal line 12, so as to expose the second metal line 12 at the bottom wall of the second through hole 33, and to expose the second electrode 27a at the side wall of the second through hole 33.

[0119] Please refer to Figure 3k , forming a metal material layer 34 to cover the surface of the second dielectric layer 31 and the inner wall of the second through hole 33. The metal material layer 34 covers the bottom wall and the side wall of the second through hole 33 to electrically connect the first metal wire 11, the second metal wire 12, the first electrode 24a and the second electrode 27a. The metal material layer 34 can be a metal material suitable for connecting to an external circuit, such as aluminum or an aluminum alloy. In the present embodiment, the material of the first metal wire 11 and the second metal wire 12 includes copper, and the metal material layer 34 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer and a titanium nitride layer formed in sequence conformally.

[0120] Please refer to Figure 3l , a patterning process is performed on the metal material layer 34 to form a third metal line 35 connecting the first metal line 11 and the first electrode 24a and a fourth metal line 36 connecting the second metal line 12 and the second electrode 27a. Specifically, the patterning process of the metal material layer 34 includes disconnecting the metal material layer 34 connecting the two sides of the capacitor area AA, using the metal material layer 34 covering the inner wall of the second through hole 33 on the first metal line 11 as the third metal line 35, and using the metal material layer 34 covering the inner wall of the second through hole 33 on the second metal line 12 as the fourth metal line 36.

[0121] In addition, during the process of performing the patterning process on the metal material layer 34, the metal material layer 34 can also be used to simultaneously form a metal pad on the second dielectric layer 31, and other top-level metal lines can be electrically led out to the metal pad for connection with an external circuit. In other words, the electrical lead-out (downward lead-out) of the capacitor in the semiconductor device of this embodiment can be achieved in the step of forming the metal pad (combined with the top-level metal wiring), and no additional device structure and process steps are required.

[0122] It is worth mentioning that in other examples of this embodiment, the first electrode in the capacitor can also extend to the second metal wire, and the second electrode extends above the first metal wire, so that the third metal wire formed is electrically connected to the first metal wire and the second electrode, and the fourth metal wire is electrically connected to the second metal wire and the first electrode.

[0123] Embodiment 3

[0124] Embodiment 3 provides a semiconductor device.

[0125] Figure 2m This is a schematic structural diagram of a semiconductor device provided in Example 3.

[0126] The semiconductor device provided in this example can be formed by the method provided in the first embodiment. Figure 2m As shown, the semiconductor device may include a substrate 10, a first metal line 11 and a second metal line 12, an insulating layer 22, a capacitor, a second dielectric layer 31, a third metal line 35 and a fourth metal line 36. The first metal line 11 and the second metal line 12 are arranged in the same layer in the substrate 10. The insulating layer 22 covers the first metal line 11 and the second metal line 12, and a plurality of grooves 23 are formed in the insulating layer 22 between the first metal line 11 and the second metal line 12. The capacitor is formed on the insulating layer 22 in and around the groove 23 (capacitor region AA), including a first electrode 24a, a first dielectric layer 26a and a second electrode 27a formed conformally in sequence, the first electrode 24a extends a portion of the length from the capacitor region AA to the first metal line 11 (i.e., a first extension region BB), and the second electrode 27 (which may also include the first electrode 24a and the first dielectric layer 26a) extends a portion of the length from the capacitor region AA to the second metal line 12 (i.e., a second extension region CC). The second dielectric layer 31 covers the surface of the capacitor and the insulating layer 22. A plurality of first through holes 32 are formed in the second dielectric layer 31 to expose the first electrode 24a (for example, above the first extension area BB) and the second electrode 27a (for example, above the second extension area CC), respectively. A plurality of second through holes 33 are formed in the second dielectric layer 31 and the insulating layer 22 to expose the first metal wire 11 and the second metal wire 12, respectively. The third metal wire 35 utilizes the first through hole 32 and the second through hole 33 close to the first metal wire 11 to electrically connect the first metal wire 11 and the first electrode 24a. The fourth metal wire 36 utilizes the first through hole 32 and the second through hole 33 close to the second metal wire 12 to electrically connect the second metal wire 12 and the second electrode 27a.

[0127] Figure 3l This is a schematic structural diagram of another semiconductor device provided in Example 3.

[0128] The semiconductor device provided in this example can be formed by the method provided in the second embodiment. Figure 3lAs shown, the semiconductor device may include a substrate 10, a first metal line 11 and a second metal line 12, an insulating layer 22, a capacitor, a second dielectric layer 31, a third metal line 35 and a fourth metal line 36. The first metal line 11 and the second metal line 12 are arranged in the same layer in the substrate 10. The insulating layer 22 covers the first metal line 11 and the second metal, and a plurality of grooves 23 are formed in the insulating layer 22 between the first metal line 11 and the second metal line 12. The capacitor is formed on the insulating layer 22 in and around the groove 23, including a first electrode 24a, a first dielectric layer 26a and a second electrode 27a formed conformally in sequence, and the first electrode 24a and the second electrode 27a extend from the capacitor to both sides to the top of the first metal line 11 and the second metal line 12, respectively. The second dielectric layer 31 covers the surface of the capacitor and the insulating layer 22. A plurality of through holes (second through holes 33) are formed in the second dielectric layer 31 and the insulating layer 22, respectively penetrating the first electrode 24a and the second electrode 27a and exposing the first metal wire 11 and the second metal wire 12, that is, the bottom wall of the second through hole 33 above the first metal wire 11 exposes the first metal wire 11, and the side wall thereof exposes the first electrode 24a, and the bottom wall of the second through hole 33 above the second metal wire 12 exposes the second metal wire 12, and the side wall thereof exposes the second electrode 27a. The third metal wire 35 covers the second through hole 33 on the first metal wire 11 to electrically connect the first metal wire 11 and the first electrode 24a, and the fourth metal wire 36 covers the second through hole 33 on the second metal wire 12 to electrically connect the second metal wire 12 and the second electrode 27a.

[0129] In summary, the present invention has a plurality of grooves in the insulating layer between the first metal wire and the second metal wire, and forms a capacitor in the groove and on the insulating layer around the groove, the capacitor includes a first electrode, a first dielectric layer and a second electrode which are formed conformally in sequence, the first electrode and the second electrode respectively extend to both sides of the capacitor and are both exposed upward, then a second dielectric layer is formed to cover the capacitor and the insulating layer, and through holes are formed in the second dielectric layer and the insulating layer to respectively expose the first metal wire, the second metal wire, the first electrode and the second electrode, then a third metal wire is formed by the through hole to electrically connect the first electrode and the first metal wire, and a fourth metal wire is formed to electrically connect the second electrode and the second metal wire, thereby the two electrodes of the capacitor in the semiconductor device are led downward by the first metal wire and the second metal wire in the substrate, the lead-out of the capacitor in the semiconductor device and the wiring of the metal wire on the insulating layer are completed without adding additional process steps, the difficulty of process integration is reduced, and it is beneficial to improve the capacitance density and design freedom of the capacitor in the semiconductor device. In addition, compared with the related art where trench capacitors require metal to fill the trenches, the two electrodes of the capacitor in this embodiment extend to both sides to achieve electrical lead-out and do not need to be filled with metal, that is, voids are allowed to exist, which is conducive to improving the freedom of trench capacitor design.

[0130] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, wherein a first metal line and a second metal line arranged in the same layer and an insulating layer covering the first metal line and the second metal line are formed in the substrate; forming a plurality of grooves in the insulating layer between the first metal line and the second metal line; forming a first electrode at least covering the trench and an insulating layer around the trench; Forming a first dielectric layer and a second electrode to conformally cover the trench and the first electrode around the trench, and exposing a portion of the first electrode; forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench; A plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first metal line, the second metal line, the first electrode and the second electrode, a third metal line is formed to electrically connect the first metal line and the first electrode, and a fourth metal line is formed to electrically connect the second metal line and the second electrode.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: A capacitor region is provided on the insulating layer between the first metal wire and the second metal wire, a plurality of grooves are formed in the capacitor region, and the step of forming the first electrode includes: forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the groove; Forming a first mask to cover the capacitor region and a first electrode material layer in a partial region close to one side of the first metal line; Using the first mask, etching away the exposed first electrode material layer, and using the remaining first electrode material layer as the first electrode; The first mask is removed.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The steps of forming the first dielectric layer and the second electrode include: forming a first dielectric material layer and a second electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode; Forming a second mask to cover the capacitor region and a second electrode material layer in a partial region near one side of the second metal line, and the second mask to expose a portion of the second electrode material layer located on the first electrode; Using the second mask, performing a dry etching process to sequentially remove the exposed second electrode material layer and the first dielectric material layer, using the remaining second electrode material layer as the second electrode and the remaining first dielectric material layer as the first dielectric layer, and exposing a portion of the surface of the first electrode; The second mask is removed.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The steps of forming a plurality of the through holes include: Forming a plurality of first through holes in the second dielectric layer to expose the first electrode and the second electrode respectively; A plurality of second through holes are formed in the insulating layer and the second dielectric layer to expose the first metal line and the second metal line respectively.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The steps of forming the third metal line and the fourth metal line include: forming a metal material layer to cover the surface of the second dielectric layer, the first through hole and the inner wall of the second through hole; A patterning process is performed on the metal material layer to form the third metal line electrically connecting the first metal line and the first electrode, and to form the fourth metal line electrically connecting the second metal line and the second electrode.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: A capacitor region is provided on the insulating layer between the first metal wire and the second metal wire, a plurality of grooves are formed in the capacitor region, and the step of forming the first electrode includes: forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the groove; Forming a first mask to cover the capacitor region to a first electrode material layer above the first metal line; Using the first mask, etching away the exposed first electrode material layer, and using the first electrode material layer from the capacitor region to above the first metal line as the first electrode, wherein the first electrode extends from the capacitor region to above the first metal line; The first mask is removed.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The steps of forming the first dielectric layer and the second electrode include: forming a first dielectric material layer and a second electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode; forming a second mask covering the capacitor region to a second electrode material layer above the second metal line; Using the second mask, performing a dry etching process to sequentially remove the exposed second electrode material layer and the first dielectric material layer, using the remaining second electrode material layer as the second electrode, and the remaining first dielectric material layer as the first dielectric layer, wherein the second electrode extends from the capacitor region to above the second metal line; The second mask is removed.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The steps of forming the plurality of through holes, the third metal wire and the fourth metal wire include: Forming a plurality of through holes penetrating the insulating layer, the second dielectric layer, the first electrode, and the second electrode, so as to expose the first metal wire and the second metal wire at the bottom walls of the plurality of through holes, and to expose the first electrode and the second electrode at the side walls of the plurality of through holes; forming a metal material layer to cover the surface of the second dielectric layer and the inner wall of the through hole; A patterning process is performed on the metal material layer to form the third metal line electrically connecting the first metal line and the first electrode, and to form the fourth metal line electrically connecting the second metal line and the second electrode.

9. The method for manufacturing a semiconductor device according to claim 5 or 8, characterized in that: When the metal material layer is patterned, a metal pad is also formed on the surface of the insulating layer for connection with an external circuit.

10. A semiconductor device, characterized in that: include: substrate; A first metal line and a second metal line are arranged in the substrate in the same layer; an insulating layer, covering the first metal line and the second metal, wherein a plurality of grooves are formed in the insulating layer; A capacitor formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer and a second electrode formed conformally in sequence; A second dielectric layer covers the capacitor, and a plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first electrode, the second electrode, the first metal wire, and the second metal wire respectively; A third metal wire and a fourth metal wire, wherein the third metal wire electrically connects the first metal wire and the first electrode by using the through hole, and the fourth metal wire electrically connects the second metal wire and the second electrode by using the through hole.

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