Semiconductor device and manufacturing method thereof
By forming a multi-layer SiGe epitaxial layer in the PMOS device and forming grooves on the side walls of the trench, the short channel effect problem caused by boron diffusion is solved, and leakage current is reduced and device performance is improved.
Patent Information
- Application Number
- CN202411459948.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-14
AI Technical Summary
In PMOS devices, high-temperature process steps may cause boron to diffusion into the gate channel region, causing short channel effects, resulting in increased leakage current and instability of threshold voltages.
A multi-layered SiGe epitaxial layer is formed in the source and drain regions of the semiconductor device, wherein the innermost undoped SiGe epitaxial layer does not completely cover the inner wall of the trench and forms grooves at the lower end of the side wall of the trench to increase the high concentration of SiGe The volume of the fill area.
It reduces the occurrence of short channel effects, and while maintaining device performance, it facilitates subsequent adjustments based on performance indicators to improve the overall performance of the device.
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Figure CN119451165A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art
[0002] With the development of semiconductor technology, the size of transistors continues to shrink, and the traditional thinning of gate dielectric thickness can no longer effectively improve the performance of transistors. In order to overcome this challenge, the industry has adopted a series of new technical means to improve the performance of transistors, especially in PMOS (P-type metal oxide semiconductor field effect transistor), it has become a common practice to improve device performance by using SiGe epitaxial layers in the source and drain regions.
[0003] In PMOS devices, the purpose of using SiGe epitaxial layers is to generate compressive stress in the source and drain regions, thereby increasing the mobility of holes. This is because the lattice constant of Ge atoms is greater than that of Si. When Ge is doped into Si, stress is generated between the SiGe layer and the pure Si base. This stress can improve the transport characteristics of carriers, thereby improving the overall performance of the device.
[0004] In PMOS devices, boron (B) is usually doped into the source and drain regions to form p-type doped regions to reduce source-drain resistance and improve device performance. However, subsequent high-temperature process steps (such as annealing) may cause boron to diffuse into the gate channel region, thereby causing short channel effect (SCE), resulting in increased leakage current, unstable threshold voltage and other problems.
[0005] In order to avoid this problem, a common practice is to first deposit an undoped SiGe layer in the source and drain regions of the PMOS device. For the specific structure, see Figure 1 In the structure of the semiconductor device of the prior art, the surface of the undoped boron SiGe layer L1 deposited in the groove of the semiconductor device has a U-shaped opening, which covers the entire inner wall of the groove. The purpose of this is to prevent boron from diffusing into the gate channel region in the subsequent high-temperature process, thereby avoiding the occurrence of short channel effect. However, this method also has its limitations, because the undoped SiGe layer may cause a decrease in other device performance indicators, for example, it may affect the resistance or stress effect of the source and drain regions. At the same time, the design of the first layer of SiGe epitaxial layer is an undoped layer solution, which is not easy to adjust, and the performance of the semiconductor device cannot be improved subsequently. Therefore, it is necessary to improve the design of the existing SiGe epitaxial layer. Summary of the invention
[0006] The present invention provides a semiconductor device and a method for manufacturing the same. By forming a multi-layer SiGe epitaxial layer, in which the innermost undoped SiGe epitaxial layer does not completely cover the inner wall of the trench, the short channel effect can be reduced and subsequent performance adjustment based on device performance indicators can be facilitated.
[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.
[0008] In order to achieve one or part or all of the above purposes or other purposes, a semiconductor device provided by a technical solution of the present invention includes a semiconductor substrate, a groove is formed in the semiconductor substrate, the groove is in a "∑" shape, a first SiGe filling layer not doped with boron is arranged on the inner wall of the groove, a SiGe filling area doped with boron is arranged on the first SiGe filling layer, and the first SiGe filling layer is arranged at the sharp corners of the side walls of both sides of the groove and the surface of the bottom wall of the groove; a groove is formed inwardly at the place where the first SiGe filling layer is not arranged on the side wall of the groove; the SiGe filling area is filled in the groove and on the first SiGe filling layer. The beneficial effect of this technical solution is that the undoped first SiGe filling layer filled in the inner wall of the "∑"-shaped groove of the present invention does not completely cover the inner wall of the groove, a groove is formed at the lower end of the side wall of the groove where the first SiGe filling layer is not filled, and the SiGe filling area is filled in the groove and on the first SiGe filling layer, and the groove can increase the volume of the high-concentration SiGe filling area doped with boron, improve stress, and on the basis of reducing the short channel effect, it can also facilitate subsequent performance adjustment based on device performance indicators.
[0009] The SiGe filling area includes a second SiGe filling layer and a third SiGe filling layer with different boron doping concentrations, the second SiGe filling layer covers the groove and the first SiGe filling layer, the third SiGe filling layer covers the second SiGe filling layer, and a silicon cap is provided after the third SiGe filling layer extends out of the semiconductor substrate groove.
[0010] The silicon cap covers the opening on the surface of the groove.
[0011] The outermost portion of the first SiGe filling layer is vertically flush with the trench opening and covers the sharp corners of the sidewalls on both sides of the trench inwardly.
[0012] The lateral depth and vertical depth of the recess in the semiconductor substrate are both smaller than the lateral depth and vertical depth of the trench in the semiconductor substrate.
[0013] The thickness of the first SiGe filling layer is 10A-60A, the thickness of the second SiGe filling layer is 100A-200A, the thickness of the third SiGe filling layer is 300A-600A, and the thickness of the silicon cap is 100A-250A.
[0014] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: Step 1: providing a semiconductor substrate, and etching a groove in the shape of "∑" on the semiconductor substrate; Step 2: epitaxially growing a first SiGe filling layer not doped with boron at the sharp corners of the two side walls and the bottom wall of the groove; Step 3: etching the groove, etching inwardly from the area on the side wall of the groove not filled with the first SiGe filling layer to form a groove, the lateral depth and vertical square depth of the formed groove in the semiconductor substrate are both smaller than the lateral depth and vertical depth of the groove in the semiconductor substrate; Step 4: depositing a second SiGe filling layer doped with boron on the first SiGe filling layer and in the groove; depositing a third SiGe filling layer doped with boron on the second SiGe filling layer; and depositing a silicon cap on the third SiGe filling layer.
[0015] The first SiGe filling layer, the second SiGe filling layer, and the third SiGe filling layer are made by chemical vapor deposition, including: using silicon-containing gas and germanium-containing gas as deposition gas, in combination with carrier gas and etching gas, maintaining the pressure of 10Torr-50Torr in the range of 600°C-800°C, and performing epitaxial growth; when the first SiGe filling layer grows in the step 2, the flow ratio of the etching gas to the deposition gas is greater than 0.5.
[0016] The percentage of Ge in the first SiGe filling layer is 10%-20%; the doping concentration of boron in the second SiGe filling layer is 1E19-8E19 / cm 3 The percentage of Ge in the second SiGe filling layer is 20%-30%; the doping concentration of boron in the third SiGe filling layer is 9E19-5E20 / cm 3 The percentage of Ge in the third SiGe filling layer is 30%-50%; the silicon cap is formed by boron-doped silicon deposition, and the boron doping concentration in the silicon cap is 5E20-5E21 / cm 3 .
[0017] The concentration of boron doped in the second SiGe filling layer is a gradient concentration, and the concentration of boron changes accordingly with the change of doping depth.
[0018] In the step three, the groove is etched by wet etching, using a tetramethylammonium hydroxide solution with a solution concentration of 2.3%-12.5% and an etching temperature of 20°C-30°C; in the step three, the etching rate ratio of the silicon substrate to the first SiGe filling layer is greater than 10:1.
[0019] The thickness of the first SiGe filling layer is 10A-60A, the thickness of the second SiGe filling layer is 100A-200A, the thickness of the third SiGe filling layer is 300A-600A, and the thickness of the silicon cap is 100A-250A.
[0020] Compared with the prior art, the beneficial effects of the present invention mainly include: the undoped first SiGe filling layer filled in the inner wall of the "∑"-shaped groove of the present invention does not completely cover the inner wall of the groove, and a groove is formed at the lower end of the groove side wall where the first SiGe filling layer is not filled, and the second SiGe filling layer is filled in the groove and on the first SiGe filling layer. The set groove can increase the volume of the high-concentration second SiGe filling layer and improve the stress. At the same time, the position of the groove is relatively low, and the boron diffused during the annealing stage is also difficult to affect the channel area. On the basis of reducing the short channel effect, it can also facilitate subsequent performance adjustment based on device performance indicators.
[0021] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 It is a schematic diagram of the structure of a semiconductor device in the prior art.
[0024] Figure 2 This is a schematic diagram of the semiconductor device manufacturing process of the present application.
[0025] Figure 3 This is a schematic diagram of the semiconductor device structure of the present application.
[0026] In the figure, 1, substrate; 2, upper side wall; 3, lower side wall; 4, groove; 5, bottom wall; 6, sharp corner. DETAILED DESCRIPTION
[0027] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.
[0028] Embodiment 1
[0029] Embodiment 1 provides a semiconductor device. The structure of the semiconductor device in Embodiment 1 is shown in FIG. Figure 3 The semiconductor device includes a groove formed between the gate regions of the semiconductor substrate, the groove is a Sigma-shaped groove, and its shape is two symmetrical "∑"-shaped grooves. The cross-sectional profile of the Sigma-shaped groove is not a regular hexagon, and the two groove corners 6 of its side wall are close to the surface of the semiconductor substrate, that is, the length of the upper side wall 2 forming the groove side wall corner is less than the length of the lower side wall 3.
[0030] The first SiGe filling layer L1 is provided on the sharp corners 6 of the two side walls of the groove and the bottom wall 5. A groove 4 is provided inwardly at the lower side wall 3 of the groove where the first SiGe filling layer is not provided. The lateral depth and vertical depth of the groove 4 in the semiconductor substrate 1 are smaller than the lateral depth and vertical depth of the groove in the semiconductor substrate 1. There is an arc-shaped concave surface on the surface of the first SiGe filling layer L1, and the arc-shaped concave surface is formed after etching when the groove is formed. The first SiGe filling layer L1 is not doped with boron. A second SiGe filling layer L2 and a third SiGe filling layer L3 are also provided on the upper part of the first SiGe filling layer L1. The second SiGe filling layer L2 is arranged above the first SiGe filling layer L1 and inside the groove 4, and the groove 4 is arranged on the lower sidewall 3 of the groove. The second SiGe filling layer L2 doped with boron fills the groove 4. When the annealing step is performed in the subsequent process, the boron will diffuse, but the groove position is low, so it is difficult for the boron to diffuse into the channel between the source and the drain, which affects the channel area. At the same time, due to the setting of the groove 4, the volume and stress of the SiGe filling layer can be increased, which can facilitate the adjustment of the corresponding parameters to improve the performance of the device. At the same time, due to the setting of the groove 4, when the second SiGe filling layer L2 is filled, a larger concave surface will be formed on the upper part of the second SiGe filling L2 layer. The third SiGe filling layer L3 is filled on the upper part of the second SiGe filling layer L2, and after the third SiGe filling layer L3 fills the groove area, an upward convex portion will be formed on the surface of the semiconductor substrate, and the middle part of the convex portion convexes outward, and both sides show a downward trend. A silicon cap L4 is also provided above the third SiGe filling layer L3, and the silicon cap L4 is used to maintain the stress of the lower SiGe filling layer, and Si reacts with Ni to generate NiSi in the subsequent silicide process. The surface of the silicon cap L4 formed above the third SiGe filling layer L3 in Example 1 is flat and flush with the surface of the semiconductor substrate 1, and it completely covers the opening of the trench in the semiconductor substrate.
[0031] In order to ensure that the opening of the groove 4 meets the requirements, the first SiGe filling layer L1 is filled until its outer wall (opposite to the direction of the groove tip) is flush with the opening of the groove on the semiconductor substrate 1 in the vertical direction. Since the lower side wall 3 of the groove is longer than the upper side wall 2, after the first SiGe filling layer L1 is filled, part of the side wall on the lower side wall 3 of the groove is not covered by the first SiGe filling layer L1. Therefore, when the groove is opened, it can be opened along the position not covered by the first SiGe filling layer L1.
[0032] The thickness of the first SiGe filling layer L1 is 10A-60A, the thickness of the second SiGe filling layer L2 is 100A-200A, the thickness of the third SiGe filling layer L3 is 300A-600A, and the thickness of the silicon cap L4 is 100A-250A.
[0033] Embodiment 2
[0034] Embodiment 2 provides a method for manufacturing a semiconductor device, wherein the method for forming the semiconductor device is as follows: Figure 2 , including the following steps: S1: providing a semiconductor substrate, etching a "∑"-shaped groove on the semiconductor substrate; the specific steps of forming the "∑"-shaped groove include forming a mask layer (not shown) on the semiconductor substrate, patterning the mask layer, dry etching the semiconductor substrate 1 to form a U-shaped groove, and then wet etching the groove wall of the U-shaped groove with crystal orientation selection to form a "∑"-shaped groove. Then, epitaxially grow a first SiGe filling layer L1 on the sharp corners of the two side walls and the bottom wall of the groove, the first SiGe filling layer is not doped with boron, and the percentage of Ge in the first SiGe filling layer is 10%-20% (the Ge percentage here refers to the molar percentage), wherein the percentage of Ge in the first SiGe filling layer can be a fixed concentration or a gradient concentration, and the gradient concentration here refers to the concentration of Ge changing accordingly with the change of depth. As a common gradient concentration, the concentration of Ge decreases with the increase of the depth of the filling layer, and the increase of depth is linearly related to the decrease of Ge concentration.
[0035] S2: Etching a groove, etching inwardly to form a groove in the area on the side wall of the groove that is not filled with the first SiGe filling layer, the lateral depth and vertical square depth of the formed groove in the semiconductor substrate are both smaller than the lateral depth and vertical depth of the groove in the semiconductor substrate, the etching here adopts wet etching, and a tetramethylammonium hydroxide solution with a solution concentration of 2.3%-12.5% is used. The tetramethylammonium hydroxide solution has an etching selection effect, and the etching rate for silicon is greater than the etching rate of the first SiGe filling layer. The etching temperature is 20℃-30℃, and the etching rate ratio of the silicon substrate to the first SiGe filling layer is greater than 10:1. By selecting the etching rate, a groove is formed on the lower side wall of the groove that is not covered by the first SiGe filling layer, and a shallow concave surface is etched on the surface of the first SiGe filling layer. By controlling the etching time, the depth of the groove in the lateral direction and vertical direction in the substrate can meet the requirements. At the same time, in order to ensure that the position of the groove etching meets the design requirements, the groove cross-section formed in S1 is not a regular hexagon, and the length of the upper side wall 2 of the groove is less than the length of the lower side wall 3. When the first SiGe filling layer L1 is covered at the same time, the outer wall of the first SiGe filling layer L1 and the opening of the groove are located in the same plane in the vertical direction. Since the length of the upper side wall 2 is different from the length of the lower side wall 3, there will be an area on the lower side wall that is not filled with the first SiGe filling layer L1, which can be used to form a groove. The groove formed in S2 is located at the lower end of the groove side wall. During the annealing stage, the boron in the second SiGe filling layer L2 doped with boron will diffuse. Due to the low position, the boron diffusion will not affect the channel area. At the same time, the groove formed by etching can increase the volume of the high-concentration SiGe filling layer to increase the application and facilitate the adjustment of device performance.
[0036] S3: a second SiGe filling layer L2 is deposited on the first SiGe filling layer L1 and in the groove 4. The second SiGe filling layer L2 is doped with boron, and the boron concentration is 1E19-8E19 / cm 3 The percentage of Ge in the second SiGe filling layer is 20%-30%, and the boron concentration doped in the second SiGe filling layer is a gradient concentration. As the boron doping depth changes, the boron concentration changes accordingly.
[0037] As a preferred example, in the second embodiment, the boron concentration of the second SiGe filling layer decreases linearly with the increase of the doping depth;
[0038] The concentration of Ge in the second SiGe filling layer may be a fixed concentration or a gradient concentration.
[0039] S4: depositing a third SiGe filling layer L3 on the second SiGe filling layer L2, wherein the third SiGe filling layer L3 is doped with boron, and the boron concentration is 9E19-5E20 / cm 3The percentage of Ge in the third SiGe filling layer L3 is 30%-50%, the doping concentration of the third SiGe filling layer L3 can be a fixed concentration or a gradient concentration, and the Ge concentration in the third SiGe filling layer L3 can be a fixed concentration or a gradient concentration;
[0040] S5: a silicon cap L4 is deposited on the third SiGe filling layer L3. The silicon cap L4 is formed by depositing boron-doped silicon. The boron concentration in the silicon cap L4 is 5E20-5E21 / cm 3 The surface of the silicon cap L4 above the third SiGe filling layer L3 is flat and flush with the surface of the semiconductor substrate 1, and it completely covers the opening of the trench in the semiconductor substrate. The formed silicon cap L4 can ensure that the stress of the first SiGe filling layer L1, the second SiGe filling layer L2, and the third SiGe filling layer L3 below is maintained.
[0041] Among them, the thickness of the first SiGe filling layer is 10A-60A, the thickness of the second SiGe filling layer is 100A-200A, the thickness of the third SiGe filling layer is 300A-600A, and the thickness of the silicon cap is 100A-250A.
[0042] In Example 2, the first SiGe filling layer, the second SiGe filling layer and the third SiGe filling layer are grown using a reduced pressure chemical vapor deposition device, using silicon-containing gas (such as SiH4 or dichlorosilane) and germanium-containing gas (such as GeH4 or GeCl4) as deposition gas, combined with a carrier gas (such as hydrogen or nitrogen), an etching gas (such as HCL) and a doping gas B2H6 (the first SiGe filling layer is undoped, so no doping gas is used when preparing the first SiGe filling layer), and maintaining a pressure of 10Torr-50Torr in the range of 600°C-800°C for epitaxial growth; wherein, in order to ensure that the first SiGe filling layer in step S1 is directionally filled in the sharp corners of the trench side walls, according to the different growth rates of silicon germanium deposition on different silicon crystal orientations, the etching and deposition gas flow ratio is controlled to be greater than 0.5, so that the first SiGe filling layer can be directionally filled in the sharp corners of the trench side walls.
[0043] The semiconductor device and the manufacturing method thereof provided by the present invention are introduced in detail above. The structure and working principle of the present invention are described in detail by using specific examples in this article. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made to the present invention without departing from the principle of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A semiconductor device, comprising a semiconductor substrate, wherein a groove is formed in the semiconductor substrate, wherein the groove is in a "∑" shape, wherein a first SiGe filling layer not doped with boron is disposed on the inner wall of the groove, and a SiGe filling region doped with boron is disposed on the first SiGe filling layer, wherein: The first SiGe filling layer is arranged at the sharp corners of the sidewalls on both sides of the trench and the surface of the bottom wall of the trench; Where the first SiGe filling layer is not provided on the sidewall of the trench, a groove is formed inwardly; The groove and the first SiGe filling layer are filled with a SiGe filling region.
2. A semiconductor device according to claim 1, characterized in that: The SiGe filling area includes a second SiGe filling layer and a third SiGe filling layer with different boron doping concentrations, the second SiGe filling layer covers the groove and the first SiGe filling layer, the third SiGe filling layer covers the second SiGe filling layer, and a silicon cap is provided after the third SiGe filling layer extends out of the semiconductor substrate groove.
3. A semiconductor device according to claim 2, characterized in that: The silicon cap covers the opening on the surface of the groove.
4. A semiconductor device according to claim 1, characterized in that: The outermost portion of the first SiGe filling layer is vertically flush with the trench opening and covers the sharp corners of the sidewalls on both sides of the trench inwardly.
5. A semiconductor device according to claim 1, characterized in that: The lateral depth and vertical depth of the recess in the semiconductor substrate are both smaller than the lateral depth and vertical depth of the trench in the semiconductor substrate.
6. A semiconductor device according to claim 2, characterized in that: The thickness of the first SiGe filling layer is 10A-60A, the thickness of the second SiGe filling layer is 100A-200A, the thickness of the third SiGe filling layer is 300A-600A, and the thickness of the silicon cap is 100A-250A.
7. A method for manufacturing a semiconductor device, characterized in that: The steps include: Step 1: providing a semiconductor substrate, and etching a "∑"-shaped groove on the semiconductor substrate; Step 2: epitaxially growing a first SiGe filling layer not doped with boron on the sharp corners of the two side walls and the bottom wall of the trench; Step 3: etching a groove, etching inwardly from the area on the sidewall of the groove that is not filled with the first SiGe filling layer to form a groove, wherein the lateral depth and vertical depth of the formed groove in the semiconductor substrate are both smaller than the lateral depth and vertical depth of the groove in the semiconductor substrate; Step 4: depositing a second SiGe filling layer doped with boron on the first SiGe filling layer and in the groove; depositing a third SiGe filling layer doped with boron on the second SiGe filling layer; and depositing a silicon cap on the third SiGe filling layer.
8. A method for manufacturing a semiconductor device according to claim 7, characterized in that: The first SiGe filling layer, the second SiGe filling layer, and the third SiGe filling layer are prepared by chemical vapor deposition, including: using silicon-containing gas and germanium-containing gas as deposition gas, with carrier gas and etching gas, maintaining a pressure of 10 Torr-50 Torr in the range of 600° C.-800° C., and performing epitaxial growth; When the first SiGe filling layer grows in the step 2, the flow ratio of the etching gas to the deposition gas is greater than 0.
5.
9. A method for manufacturing a semiconductor device according to claim 7, characterized in that: The percentage of Ge in the first SiGe filling layer is 10%-20%; The boron doping concentration in the second SiGe filling layer is 1E19-8E19 / cm 3 , the percentage of Ge in the second SiGe filling layer is 20%-30%; The doping concentration of boron in the third SiGe filling layer is 9E19-5E20 / cm 3 , the percentage of Ge in the third SiGe filling layer is 30%-50%; The silicon cap is formed by depositing boron-doped silicon, and the boron doping concentration in the silicon cap is 5E20-5E21 / cm 3 .
10. A method for manufacturing a semiconductor device according to claim 9, characterized in that: The concentration of boron doped in the second SiGe filling layer is a gradient concentration, and the concentration of boron changes accordingly with the change of doping depth.
11. A method for manufacturing a semiconductor device according to claim 7, characterized in that: In the step three, the groove is etched by wet etching, using a tetramethylammonium hydroxide solution with a solution concentration of 2.3%-12.5% and an etching temperature of 20°C-30°C; in the step three, the etching rate ratio of the silicon substrate to the first SiGe filling layer is greater than 10:
1.
12. A method for manufacturing a semiconductor device according to claim 7, characterized in that: The thickness of the first SiGe filling layer is 10A-60A, the thickness of the second SiGe filling layer is 100A-200A, the thickness of the third SiGe filling layer is 300A-600A, and the thickness of the silicon cap is 100A-250A.