Under-gate anti-radiation reinforcing structure of high-voltage SiC MOSFET

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a high-voltage SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) under-gate anti-radiation reinforcing structure which comprises a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a gate electrode, the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and a heavily doped N well layer; wherein the diffusion layer comprises a low-doped N body region I and a carrier storage layer; a groove structure is etched in the surface area of the semiconductor epitaxial layer between the adjacent lightly doped P well layers I; a P-type doped region is formed on the inner surface of the groove structure through ion implantation; and a dielectric layer is formed in the inner cavity of the P-type doped region through deposition. A groove structure is introduced into a JFET region of the SiC MOSFET device, P-type impurities are injected into the side wall and the bottom of the groove to form a P-type doped region, the groove is filled with dielectric materials such as SiO2, the groove structure transfers a strong electric field at a gate oxide interface to the bottom of the JFET region, the electric field intensity in thin gate oxide is greatly reduced, and therefore the single-particle gate penetration resistance of the SiC MOSFET device is improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and more particularly to a high-voltage SiC MOSFET gate under-gate radiation-resistant reinforcement structure. Background Art

[0002] Silicon carbide high-voltage power devices have better electrothermal properties than traditional silicon devices and can work normally in more demanding environments. Therefore, they have broad application prospects in photovoltaic power generation, electric vehicles, aerospace, etc. For the aerospace field, power devices must not only meet the requirements of high voltage, high power, high frequency and low loss, but also have good radiation resistance.

[0003] For high-voltage SiC power devices, radiation hardening is a major problem. Current SiC power devices often experience single-particle burnout when the blocking voltage is less than 1 / 3 and the LET is no higher than 10MeV.cm2 / mg, which is far lower than theoretical expectations. Single-particle radiation usually involves very complex electrothermal coupling responses inside the device. When heavy ions bombard the power device, a large number of electron-hole pairs are generated along the trajectory. These electron-hole pairs drift under the action of the electric field, forming a large instantaneous current inside the device. Some electrons and holes will also accumulate at both ends of the device, thereby reconstructing the electric field inside the device, resulting in strong electric field breakdown in the device, such as single-particle gate breakdown.

[0004] In addition, the instantaneous large current and instantaneous temperature rise formed inside the device by the massive electron-hole movement and strong electric field coupling may trigger the conduction of the parasitic NPN transistor inside the device, resulting in local single-particle burning of the device under lower bias voltage conditions.

[0005] like Figure 1As shown in the common planar gate SiC MOSFET device structure in Figure 1, when heavy ions bombard the power device, a large number of electron-hole pairs will be generated along the trajectory of movement. These electron-hole pairs drift under the electric field formed by the reverse blocking voltage, forming a huge instantaneous current inside the device, especially the JFET region of the SiC MOSFET device, which becomes the weakest position due to the high electric field strength. On the one hand, the movement of a large number of electrons and holes under the action of the electric field will form an instantaneous large current in the local area of ​​the device, resulting in a large amount of power consumption and temperature rise in the local area of ​​the device, and eventually causing serious ablation damage to the local part of the device. In this process, the instantaneous large current and high temperature may also cause the parasitic NPN transistor in the SiC MOSFET device to turn on, exacerbating the single particle burning of the SiC MOSFET device. On the other hand, a large number of electrons and holes drift under the action of the electric field, and the excess carriers that are not extracted or recombined in time are accumulated on the surface and back of the device. In particular, the accumulation of a large number of holes on the surface of the JFET region may cause the gate oxide to break down, causing the SiC MOSFET device to have a single particle gate penetration and damage the device. Summary of the invention

[0006] The main technical problem solved by the present invention is to provide a high-voltage SiC MOSFET gate under-gate radiation-resistant reinforcement structure, which solves the problems in the above-mentioned background technology.

[0007] To solve the above technical problems, according to one aspect of the present invention, more specifically, a high-voltage SiCMOSFET gate-under-radiation reinforcement structure is provided, comprising a drain, a semiconductor epitaxial layer, a metal source, and a gate;

[0008] The semiconductor epitaxial layer includes a substrate layer, a diffusion layer, a P-well layer and a heavily doped N-well layer;

[0009] The diffusion layer includes a low-doped N body region 1, a carrier storage layer, a low-doped N body region 2, a high-doped N body region 1 and a high-doped N body region 2;

[0010] The P-well layer includes a lightly doped P-well layer 1, a heavily doped P-well layer and a lightly doped P-well layer 2;

[0011] A groove structure is etched in the surface area of ​​the semiconductor epitaxial layer between the adjacent lightly doped P well layers;

[0012] The inner surface of the trench structure is formed with a P-type doping region by ion implantation, and the cross-sectional profile of the P-type doping region is in a 'U' shape;

[0013] A dielectric layer is formed in the inner cavity of the P-type doping region by deposition.

[0014] Furthermore, in a single MOS cell, the dielectric layer is located directly below the gate.

[0015] Furthermore, the dielectric layer is made of SiO2, SiN, and Al2O3 materials.

[0016] Furthermore, in the P-well layer, only the heavily doped P-well layer is in ohmic contact with the metal source electrode.

[0017] Furthermore, the lightly doped P-well layer 1 and the heavily doped P-well layer between adjacent MOS cells are integrated as one.

[0018] Furthermore, the cross-sectional heights of the low-doped N body region 2 and the high-doped N body region 1 are the same, and the low-doped N body region 2 is located above the high-doped N body region 1.

[0019] Furthermore, the lightly doped P well layer 2 is located below the lightly doped P well layer 1, and the highly doped N body region 2 is located between two adjacent lightly doped P well layers 2 and 1.

[0020] Furthermore, an isolation dielectric is deposited on the outer surface of the gate.

[0021] The beneficial effects of the anti-radiation reinforcement structure under the gate of a high-voltage SiC MOSFET of the present invention are:

[0022] 1. The present invention introduces a trench structure in the JFET region of the SiC MOSFET device, injects P-type impurities into the sidewalls and bottom of the trench to form a P-type doped region, and fills the trench with dielectric materials such as SiO2. The trench structure transfers the strong electric field at the gate oxide interface to the bottom of the JFET region, greatly reducing the electric field strength in the thin gate oxide, thereby improving the single-particle gate penetration resistance of the SiC MOSFET device.

[0023] 2. The P-type doped regions at the bottom and sidewalls of the groove of the present invention enhance the hole extraction efficiency near the JFET region at the moment of heavy ion bombardment, can quickly and efficiently remove the electron-hole pairs generated by heavy ion bombardment, reduce the current and radiation response time generated by single particle radiation, and can effectively improve the single particle radiation resistance of SiC MOSFET.

[0024] 3. By introducing the trench structure, the present invention enhances the pinch-off effect of JFET at high blocking voltage, and can increase the doping concentration of the carrier storage layer without affecting the voltage blocking capability of the device, thereby improving the recombination efficiency of holes and electrons at the moment of single-particle radiation, and improving the radiation resistance of SiC MOSFET devices.

[0025] 4. The present invention adjusts the layout of the P-well layer injection window by optimizing the layout design of the P-well layer, and adjusts the injection sequence of the N-well and P-well layers, so that the bottom of the N-well is completely surrounded by the P-well layer. By using a larger area of ​​the P-well layer to completely surround the bottom of the N-well, the base region transport coefficient of the NPN transistor can be effectively reduced to suppress the NPN amplification effect, thereby achieving the purpose of increasing the single particle burnout threshold voltage of the SiCMOSFET device.

[0026] 5. The SiC MOSFET proposed in the present invention has a simple structure and only requires the addition of processes such as trench etching, P-type ion implantation at the sidewall and bottom of the trench, and trench backfilling, adjustment of the layout of the P-well layer, and change of the order of N-well implantation and P-well layer implantation. It is generally compatible with existing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0028] Figure 1 The device structure of the existing planar gate SiC MOSFET;

[0029] Figure 2 Schematic diagram of a single cell structure of the present invention

[0030] Figure 3 It is a radiation-resistant reinforcement structure under the gate of high-voltage SiC MOSFET.

[0031] In the figure: 1. drain; 2. substrate layer; 3. low-doped N-body region 1; 4. carrier storage layer; 5. lightly doped P-well layer 1; 6. metal source; 7. N-well layer; 8. gate; 9. isolation dielectric; 10. dielectric layer; 11. P-type doped region; 12. heavily doped P-well layer; 13. low-doped N-body region 2; 14. highly doped N-body region 1; 15. lightly doped P-well layer 2; 16. highly doped N-body region 2. DETAILED DESCRIPTION

[0032] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0033] like Figure 2-3As shown, according to one aspect of the present invention, a high-voltage SiC MOSFET gate-under-radiation reinforcement structure is provided, comprising a drain 1, a semiconductor epitaxial layer, a metal source 6, and a gate 8; the semiconductor epitaxial layer comprises a substrate layer 2, a diffusion layer, a P-well layer, and a heavily doped N-well layer 7; wherein the diffusion layer comprises a low-doped N-body region 13, a carrier storage layer 4, a low-doped N-body region 2 13, a highly doped N-body region 14, and a highly doped N-body region 2 16; the P-well layer comprises a lightly doped P-well layer 15, a heavily doped P-well layer 12, and a lightly doped P-well layer 2 15; a groove is etched in the surface area of ​​the semiconductor epitaxial layer between adjacent lightly doped P-well layers 5. Groove structure; a P-type doped region 11 is formed on the inner surface of the groove structure by ion implantation, and the cross-sectional profile of the P-type doped region 11 is in the shape of a "U"; a dielectric layer 10 is formed in the inner cavity of the P-type doped region 11 by deposition, and the dielectric layer 10 is composed of SO2 material; a groove structure is introduced into the JFET region, and P-type impurities are implanted into the sidewalls and bottom of the groove to form a P-type doped region, and SiO2 dielectric material is filled in the groove. The groove structure transfers the strong electric field at the gate oxide interface to the bottom of the JFET region, greatly reducing the electric field strength in the thin gate oxide, thereby improving the single-particle gate penetration resistance of the SiC MOSFET device.

[0034] In this embodiment, in a single MOS cell, its dielectric layer 10 is located directly below the gate 8, and only the heavily doped P well layer 12 in the P well layer is in ohmic contact with the metal source 6, and the lightly doped P well layer 15 and the heavily doped P well layer 12 between adjacent MOS cells are integrated.

[0035] like Figure 2 As shown, a trench structure is introduced into the JFET region of the device, and P-type impurities are injected into the sidewalls and bottom of the trench to form a P-type doped region 11, and a dielectric material such as SiO2 is filled in the trench to form a dielectric layer 10.

[0036] In this way, the trench structure transfers the strong electric field at the gate oxide interface to the bottom of the JFET region, greatly reducing the electric field strength in the thin gate oxide, thereby improving the SiC MOSFET device's ability to resist single-particle gate penetration.

[0037] At the same time, the P-type doped region 11 at the bottom and side walls of the groove increases the area of ​​the hole extraction path in the active area, which can enhance the hole extraction efficiency in the body at the moment of heavy ion bombardment; in addition, due to the introduction of the groove structure, the pinch-off effect of the JFET at high blocking voltage is enhanced, and the doping concentration of the carrier storage layer is increased without affecting the voltage blocking capability of the device, thereby improving the recombination efficiency of holes and electrons at the moment of single particle radiation.

[0038] By optimizing the layout design of the P-well layer, the P-well layer injection window layout is adjusted, and the N-well injection and P-well layer injection sequence are adjusted so that the bottom of the N-well is completely surrounded by the P-well layer. Using a larger P-well layer to completely surround the bottom of the N-well can effectively reduce the base region transport coefficient of the NPN transistor to suppress the NPN amplification effect, thereby achieving the purpose of increasing the single particle burnout threshold voltage of the SiC MOSFET device.

[0039] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A high-voltage SiC MOSFET gate anti-radiation reinforcement structure, characterized in that: It comprises a drain electrode (1), a semiconductor epitaxial layer, a metal source electrode (6), and a gate electrode (8); The semiconductor epitaxial layer comprises a substrate layer (2), a diffusion layer, a P-well layer and a heavily doped N-well layer (7); The diffusion layer includes a low-doped N body region 1 (3), a carrier storage layer (4), a low-doped N body region 2 (13), a high-doped N body region 1 (14) and a high-doped N body region 2 (16); The P-well layer comprises a lightly doped P-well layer 1 (5), a heavily doped P-well layer (12) and a lightly doped P-well layer 2 (15); A groove structure is etched in the surface area of ​​the semiconductor epitaxial layer between adjacent lightly doped P well layers (5); A P-type doping region (11) is formed on the inner surface of the groove structure by ion implantation, and the cross-sectional profile of the P-type doping region (11) is in a 'U' shape; A dielectric layer (10) is formed in the internal cavity of the P-type doping region (11) by deposition.

2. The high-voltage SiC MOSFET gate anti-radiation reinforcement structure according to claim 1, characterized in that: In a single MOS cell, the dielectric layer (10) is located directly below the gate (8).

3. The high voltage SiC MOSFET gate anti-radiation reinforcement structure according to claim 1, characterized in that: The dielectric layer (10) is made of SiO2, SiN, and Al2O3 materials.

4. The high-voltage SiC MOSFET gate anti-radiation reinforcement structure according to claim 1, characterized in that: Among the P-well layers, only the heavily doped P-well layer (12) is in ohmic contact with the metal source electrode (6).

5. The high voltage SiC MOSFET gate anti-radiation reinforcement structure according to claim 1, characterized in that: The lightly doped P well layer (5) and the heavily doped P well layer (12) between adjacent MOS cells are integrated as one.

6. The high voltage SiC MOSFET gate under-radiation reinforcement structure according to claim 1, characterized in that: The cross-sectional height of the low-doped N body region 2 (13) is the same as that of the high-doped N body region 1 (14), and the low-doped N body region 2 (13) is located above the high-doped N body region 1 (14).

7. The high voltage SiC MOSFET gate anti-radiation reinforcement structure according to claim 1, characterized in that: The lightly doped P well layer 2 (15) is located below the lightly doped P well layer 1 (5), and the highly doped N body region 2 (16) is located between two adjacent lightly doped P well layers 2 (15) and lightly doped P well layer 1 (5).

8. The high voltage SiC MOSFET gate anti-radiation reinforcement structure according to claim 1, characterized in that: An isolation medium (9) is deposited on the outer surface of the gate (8).

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