SiC MOSFET Devices and Manufacturing Methods

Abstract

The present invention discloses a SiC MOSFET device, wherein the device unit comprises: a bottom doped region doped with a second conductive type is formed under the bottom surface of a gate trench of a trench gate; the bottom doped region is connected to a source electrode, so that the voltage borne by a gate dielectric layer on the bottom surface of the gate trench is determined by a gate-source voltage and thereby reduces the electric field strength borne by the gate dielectric layer on the bottom surface of the gate trench; a lead-out structure of the bottom doped region connected to the source electrode comprises: a formation region of the lead-out structure is located in the region of the gate trench and the gate conductive material layer in the corresponding region is removed and filled with a first dielectric layer; a first through hole is formed at the top of the formation region of the lead-out structure, the top of the first through hole contacts the front metal layer corresponding to the source electrode, and the bottom passes through an interlayer film, a first dielectric layer and a gate dielectric layer and contacts the bottom doped region. The present invention also discloses a method for manufacturing a SiC MOSFET device. The present invention can make it easy to realize the lead-out structure of connecting the bottom doped region to the source electrode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a SiC MOSFET device; the present invention also relates to a method for manufacturing a SiC MOSFET device. Background Art

[0002] Compared with Si, SiC has a bandgap width that is nearly three times that of silicon, and its critical breakdown electric field during breakdown is also 10 times that of silicon devices. This means that under the same breakdown voltage, the width of the drift region of SiC devices is only 1 / 10 of that of Si devices, and its doping concentration can be increased by 100 times. Compared with Si devices, the drift region resistance of SiC devices can be greatly reduced. Therefore, it has a great advantage in high voltage (breakdown voltage greater than 600V) applications. In more and more applications, Si-based super junction and Si-based IGBT devices are being replaced.

[0003] SiC MOSFET is the first choice. According to the structure of its gate, there are two major categories: one is the planar gate SiC MOSFET, and the other is the trench gate SiC MOSFET.

[0004] Compared with planar gate SiC MOSFET, trench gate SiC MOSFET has the following characteristics:

[0005] The step (Pitch) of the trench gate is smaller, which means that the density of the channel is higher. Higher channel density means lower channel resistance. Compared with Si-based MOSFET and IGBT, SiC MOSFET has greatly reduced doping concentration and thickness in the drift region, and the resistance of the drift region is greatly reduced. This increases the proportion of channel resistance in the total resistance, which is more obvious in 600V and 1200V SiC MOSFET. Therefore, higher channel density and lower channel resistance help to reduce the specific on-resistance.

[0006] In addition, for trench gate SiC MOSFET, higher mobility can be obtained by selecting a suitable crystal orientation, thereby further reducing the channel resistance.

[0007] Trench gate MOSFET can also reduce the JFET effect of the channel and reduce the specific on-resistance.

[0008] Trench gate MOSFET is increasingly widely used due to these advantages. The present invention mainly improves trench gate SiC MOSFET.

[0009] like Figure 1This is a cross-sectional structural diagram of the device unit of the first existing SiC MOSFET device; here we take the N-type SiC MOSFET as an example. The N-type is currently the most common, because the mobility of electrons in SiC MOSFET is about 7 times that of holes; this is different from Si devices, where the mobility of electrons in silicon devices is 3 times that of holes. Because of the difference in mobility, the N-type has a lower on-resistance and is currently the most common structure. The device units of the first existing SiC MOSFET device include:

[0010] N-type heavily doped SiC substrate 101, after thinning, is used as a drain region, and a back metal layer is formed on the back of the drain region as a drain. The lower the resistivity of the SiC substrate 101, the better. However, the SiC substrate 101 is different from the Si substrate, and the lowest resistivity that can be achieved is around 0.02Ω*cm. The current minimum resistivity of the Si substrate can reach less than 1mΩ*cm. In addition, compared with the Si substrate, the SiC substrate 101 is more difficult to thin. Therefore, the substrate resistance of the SiC MOSFET is greater than that of the Si-based device.

[0011] A SiC epitaxial layer 102 is formed on the SiC substrate 101, which may be a single epitaxial layer or multiple epitaxial layers. Usually, we hope that the resistivity of the SiC epitaxial layer 102 can be reduced when it is close to the channel, that is, the doping concentration can be increased, so as to reduce the diffusion resistance of the MOSFET, that is, the resistance formed by the current from being concentrated in the channel to the entire drift region. Therefore, two epitaxial layers are also used to realize the SiC epitaxial layer 102.

[0012] The trench gate includes a gate dielectric layer 107 and a gate conductive material layer 106. The gate conductive material layer 106 is usually made of heavily doped polysilicon. The gate dielectric layer 107 is an insulating layer, usually silicon dioxide, which can be oxidized at high temperature, usually between 1150°C and 1250°C, or deposited by CVD. The thickness of the oxide layer is usually around 50nm.

[0013] The channel region 103 is usually formed by aluminum ion implantation.

[0014] The heavily doped source region 105 is usually formed by using Nitrogen ion implantation.

[0015] The heavily doped P+ region, namely the ohmic contact region 104, is used to connect the channel region 103 and form a good ohmic contact with the subsequent via corresponding to the source metal.

[0016] After the front metal layer 109 is patterned, a source and a gate are formed, wherein the source is connected to the source region 105 and the P+ region 104 at the bottom through a through hole; the gate is in contact with the gate conductive material layer 106 through a through hole. In order to form a good ohmic contact with the gate conductive material layer 106, the source region 105 and the P+ region 104, the front metal layer 109 is usually TiNiAl.

[0017] The through hole will pass through the interlayer film (ILD) 108. The thickness of the interlayer film 108 is usually around 1 μm, and it is usually composed of two layers of silicon dioxide. A typical condition is PSG+BPSG.

[0018] SiC material has a high bandgap width. When it breaks down, its critical electric field strength can reach 3e6V / cm. For trench gate MOSFET, its highest electric field strength usually occurs at the bottom of the gate trench. This is because of the curvature effect. In terms of process, the gate trench needs to be made as smooth as possible to reduce the curvature effect. As for the electric field strength of the gate dielectric layer 107, such as the oxide layer, due to Gauss's theorem, it is necessary to multiply it by the critical electric field of SiC at the breakdown time. That is, the dielectric constant of SiC (ε semi ) and the dielectric constant of silicon dioxide (ε insulator ) ratio, which is usually around 2.6; therefore, the electric field strength in the silicon dioxide body is basically close to the limit of the electric field strength it can withstand, which will lead to an increase in gate leakage and affect the reliability of the device.

[0019] There are many solutions available. One feasible solution is to increase the dielectric constant of the oxide layer, thereby reducing Such as Si 3 N 4 It is an insulating layer material with high K. However, its application is limited by its higher interface defect density.

[0020] Another method, which is also widely used in the industry, is to reduce the electric field strength at the interface of SiC and silicon dioxide through device design. The maximum electric field strength at the interface of SiC during breakdown is set to no more than 1.5e6V / cm, which is an empirical value.

[0021] A very common practice in the industry is to use Figure 2 The device unit structure of the second conventional SiC MOSFET device is shown, and Figure 1 The differences are:

[0022] A P-type implant is performed at the bottom of the gate trench to form a bottom doped region 110 .

[0023] At the same time, it is hoped that the bottom doped region 110 is connected to the source, not floating. This is because if the bottom doped region 110 is floating, then when the device is subjected to a high drain voltage, its holes will be completely depleted. When the device is turned on, there is no way to provide holes, and they can only be generated by thermal excitation. The generated holes are slow and still in a depleted state, increasing its on-resistance, that is, dynamically increasing the on-resistance.

[0024] In addition, if the bottom doped region 110 is connected to the source, it can also better shield the gate and reduce the electric field strength of the oxide layer.

[0025] However, how to achieve contact between the bottom doped region 110 and the source is currently a difficulty.

[0026] At present, some common practices are to connect the bottom doped region 110 to the source through high-energy ion implantation, such as P-type implantation. However, this energy usually needs to be greater than 1MeV, which exceeds the capabilities of a large part of the machine. In addition, too high an implantation energy will also cause more serious lattice defects.

[0027] The bottom doped region 110 can also be connected to the source electrode by using trench etching and P-type silicon filling technology, but the P-type silicon filling process is complicated and the cost is relatively high. Summary of the invention

[0028] The technical problem to be solved by the present invention is to provide a SiC MOSFET device, which can form a bottom doped region connected to the source at the bottom of the gate trench, thereby reducing the electric field strength of the gate dielectric layer on the bottom surface of the gate trench and improving the reliability of the gate dielectric layer, and at the same time, can make the lead-out structure connecting the bottom doped region to the source easy to realize. To this end, the present invention also provides a method for manufacturing a SiC MOSFET device.

[0029] In order to solve the above technical problems, the device unit of the SiC MOSFET device provided by the present invention comprises:

[0030] A SiC epitaxial layer doped with a first conductivity type is provided, wherein a trench gate is formed in the SiC epitaxial layer.

[0031] The trench gate comprises a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0032] A bottom doped region is formed in the SiC epitaxial layer below the bottom surface of the gate trench. The bottom doped region has second conductivity type doping, and a top surface of the bottom doped region contacts a bottom surface of the gate dielectric layer at the bottom surface of the gate trench.

[0033] A channel region doped with a second conductivity type is formed in the SiC epitaxial layer, the channel region extends downward from the top surface of the SiC epitaxial layer, the gate conductive material layer vertically passes through the channel region, and the surface of the channel region is covered by the side of the gate conductive material layer to form a conductive channel.

[0034] The SiC epitaxial layer at the bottom of the channel region constitutes a drift region.

[0035] A source region consisting of a heavily doped region of the first conductivity type is formed on the surface of the channel region.

[0036] The top of the gate conductive material layer is connected to a gate composed of a front metal layer.

[0037] The top of the source region is connected to a source electrode formed by a front metal layer.

[0038] The bottom doped region is connected to the source, so that the voltage borne by the gate dielectric layer at the bottom surface of the gate trench is determined by the voltage difference between the source and the gate, thereby reducing the electric field strength borne by the gate dielectric layer at the bottom surface of the gate trench.

[0039] The lead-out structure of the bottom doped region connected to the source electrode comprises:

[0040] The lead-out structure forming region is located in the gate trench region, the gate conductive material layer in the lead-out structure forming region is removed, and the first dielectric layer is filled in the gate conductive material layer removed region.

[0041] A first through hole is formed at the top of the formation area of ​​the lead-out structure, the top of the first through hole contacts the front metal layer corresponding to the source, and the bottom of the first through hole passes through the interlayer film, the first dielectric layer and the gate dielectric layer and contacts the bottom doped area.

[0042] A further improvement is that the SiC epitaxial layer is formed on a SiC substrate, the SiC substrate is heavily doped with the first conductivity type, and the drain region is composed of the thinned SiC substrate or is formed by back ion implantation of the thinned SiC substrate.

[0043] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0044] A further improvement is that a device unit region of the SiC MOSFET device is formed by connecting a plurality of the device units in parallel.

[0045] In a top view, the device unit is a strip structure or a polygonal structure.

[0046] The polygonal structure includes a square or a hexagon.

[0047] A further improvement is that the device unit is a strip-shaped structure and the gate trench is strip-shaped.

[0048] The gate trenches and the mesa regions between the gate trenches are alternately arranged along a width direction of the gate trenches.

[0049] A further improvement is that, along the length direction of the gate trench, the formation area of ​​the lead-out structure is located at one or more positions along the length direction of the gate trench, and the formation area of ​​the lead-out structure includes both ends or the middle position of the gate trench along the length direction.

[0050] A further improvement is that the width of the gate trench in the region where the lead-out structure is formed is greater than or equal to the width of the gate trench outside the region where the lead-out structure is formed.

[0051] A further improvement is that the material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

[0052] A further improvement is that the maximum depth of the gate trench is greater than 1 micron.

[0053] A further improvement is that the first dielectric layer is composed of the interlayer film.

[0054] In order to solve the above technical problems, in the method for manufacturing a SiC MOSFET device provided by the present invention, the step of forming a device unit includes:

[0055] Step 1: forming a SiC epitaxial layer doped with a first conductivity type, wherein a gate trench is formed in the SiC epitaxial layer.

[0056] Step 2: Perform second conductivity type ion implantation to form a bottom doped region in the SiC epitaxial layer below the bottom surface of the gate trench.

[0057] Step three: a gate dielectric layer on the inner surface of the gate trench; a top surface of the bottom doped region contacts the bottom surface of the gate dielectric layer on the bottom surface of the gate trench.

[0058] Step 4: filling a gate conductive material layer in the gate trench formed with the gate dielectric layer.

[0059] Step 5: forming a second conductive type doped channel region in the SiC epitaxial layer, wherein the channel region extends downward from the top surface of the SiC epitaxial layer, and the gate conductive material layer vertically passes through the channel region, and the surface of the channel region is covered by the side of the gate conductive material layer to form a conductive channel.

[0060] The SiC epitaxial layer at the bottom of the channel region constitutes a drift region.

[0061] Step six: forming a source region composed of a heavily doped region of the first conductivity type on the surface of the channel region.

[0062] Step seven: removing the gate conductive material layer in the region where the lead-out structure connecting the bottom doped region to the source is formed.

[0063] Step eight: filling a first dielectric layer in the region of the gate trench where the gate conductive material layer is removed.

[0064] Step nine, forming an interlayer film, a through hole, and a front metal layer, and patterning the front metal layer to form a source and a gate; the top of the gate conductive material layer is connected to the gate through a corresponding through hole, and the top of the source region is connected to the source through a corresponding through hole.

[0065] The through hole located at the top of the formation area of ​​the lead-out structure is called a first through hole, the top of the first through hole is in contact with the front metal layer corresponding to the source, and the bottom of the first through hole passes through the interlayer film, the first dielectric layer and the gate dielectric layer and is in contact with the bottom doped area.

[0066] The structure in which the bottom doped region is connected to the source makes the voltage borne by the gate dielectric layer at the bottom surface of the gate trench determined by the voltage difference between the source and the gate, thereby reducing the electric field strength borne by the gate dielectric layer at the bottom surface of the gate trench.

[0067] A further improvement is that in step 1, the SiC epitaxial layer is formed on a SiC substrate, and the SiC substrate is heavily doped with the first conductivity type.

[0068] After step nine, the following backside processes are also included:

[0069] The SiC substrate is thinned.

[0070] A drain region is formed, wherein the drain region is composed of the thinned SiC substrate or is formed by performing back ion implantation on the thinned SiC substrate.

[0071] A back metal layer is formed on the back side of the drain region and the drain electrode is formed by the back metal layer.

[0072] A further improvement is that a device unit region of the SiC MOSFET device is formed by connecting a plurality of the device units in parallel.

[0073] In a top view, the device unit is a strip structure or a polygonal structure.

[0074] The polygonal structure includes a square or a hexagon.

[0075] A further improvement is that the device unit is a strip-shaped structure and the gate trench is strip-shaped.

[0076] The gate trenches and the mesa regions between the gate trenches are alternately arranged along a width direction of the gate trenches.

[0077] A further improvement is that, along the length direction of the gate trench, the formation area of ​​the lead-out structure is located at one or more positions along the length direction of the gate trench, and the formation area of ​​the lead-out structure includes both ends or the middle position of the gate trench along the length direction.

[0078] A further improvement is that the width of the gate trench in the region where the lead-out structure is formed is greater than or equal to the width of the gate trench outside the region where the lead-out structure is formed.

[0079] A further improvement is that the material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

[0080] A further improvement is that the maximum depth of the gate trench is greater than 1 micron.

[0081] A further improvement is that the first dielectric layer is composed of the interlayer film, and step eight is merged into the formation process of the interlayer film in step nine.

[0082] The present invention can form a bottom doping region connected to the source electrode at the bottom of the gate trench, thereby reducing the electric field strength of the gate dielectric layer on the bottom surface of the gate trench and improving the reliability of the gate dielectric layer;

[0083] At the same time, the lead-out structure of the bottom doped region connected to the source in the present invention is achieved by removing the gate conductive material layer in a partial area of ​​the gate groove, then filling the first dielectric layer and forming a first through hole at the bottom passing through the first dielectric layer. This lead-out structure does not require high-energy ion implantation, so it is easy to implement and the final process cost will also be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0085] Figure 1 It is a schematic diagram of the cross-sectional structure of a device unit of the first existing SiC MOSFET device;

[0086] Figure 2 is a schematic diagram of a cross-sectional structure of a device unit of the second existing SiC MOSFET device;

[0087] Figure 3 It is a first photolithography layout corresponding to the lead-out structure of the bottom doping region of the SiC MOSFET device according to an embodiment of the present invention;

[0088] Figure 4A is the device unit of the SiC MOSFET device of the embodiment of the present invention Figure 3 Schematic diagram of the cross-sectional structure at the AA dotted line in FIG.

[0089] Figure 4B is the device unit of the SiC MOSFET device of the embodiment of the present invention Figure 3 Schematic diagram of the cross-sectional structure at the dotted line BB in FIG.

[0090] Figure 4C is the device unit of the SiC MOSFET device of the embodiment of the present invention Figure 3 Schematic diagram of the cross-sectional structure at the CC dotted line in FIG.

[0091] Figure 5 It is a second photolithography layout of the lead-out structure of the bottom doping region of the SiC MOSFET device according to an embodiment of the present invention;

[0092] Figure 6 This is the third photolithography layout of the lead-out structure of the bottom doped region of the SiC MOSFET device according to the embodiment of the present invention. DETAILED DESCRIPTION

[0093] SiC MOSFET device according to an embodiment of the present invention:

[0094] SiC MOSFET device according to an embodiment of the present invention:

[0095] like Figure 3 As shown in FIG. 1 , it is a first photolithography layout of the lead-out structure of the bottom doping region 10 of the SiC MOSFET device according to an embodiment of the present invention; Figure 4A FIG. 1 is a diagram showing the device unit of the SiC MOSFET device according to an embodiment of the present invention. Figure 3 The schematic diagram of the cross-sectional structure at the AA dotted line in FIG. Figure 4B FIG. 1 is a diagram showing the device unit of the SiC MOSFET device according to an embodiment of the present invention. Figure 3 The schematic diagram of the cross-sectional structure at the dotted line BB in FIG. Figure 4C FIG. 1 is a diagram showing the device unit of the SiC MOSFET device according to an embodiment of the present invention. Figure 3 A schematic cross-sectional structure diagram at the CC dashed line in FIG. 1 ; a device unit of a SiC MOSFET device according to an embodiment of the present invention comprises:

[0096] A SiC epitaxial layer 2 doped with a first conductivity type is provided, wherein a trench gate is formed in the SiC epitaxial layer 2 .

[0097] The trench gate includes a gate trench, a gate dielectric layer 7 formed on the inner surface of the gate trench, and a gate conductive material layer 6 filled in the gate trench.

[0098] A bottom doped region 10 is formed in the SiC epitaxial layer 2 below the bottom surface of the gate trench. The bottom doped region 10 has second conductivity type doping, and the top surface of the bottom doped region 10 contacts the bottom surface of the gate dielectric layer 7 at the bottom surface of the gate trench.

[0099] A channel region 3 doped with a second conductive type is formed in the SiC epitaxial layer 2, and the channel region 3 extends downward from the top surface of the SiC epitaxial layer 2. The gate conductive material layer 6 vertically passes through the channel region 3, and the surface of the channel region 3 is covered by the side of the gate conductive material layer 6 to form a conductive channel.

[0100] The SiC epitaxial layer 2 at the bottom of the channel region 3 constitutes a drift region.

[0101] A source region 5 consisting of a heavily doped region of the first conductivity type is formed on the surface of the channel region 3 .

[0102] The top of the gate conductive material layer 6 is connected to the gate composed of the front metal layer 9 .

[0103] The top of the source region 5 is connected to a source electrode formed by a front metal layer 9 .

[0104] The bottom doped region 10 is connected to the source, so that the voltage borne by the gate dielectric layer 7 at the bottom surface of the gate trench is determined by the voltage difference between the source and the gate, thereby reducing the electric field strength borne by the gate dielectric layer 7 at the bottom surface of the gate trench.

[0105] The lead-out structure of the bottom doped region 10 connected to the source includes:

[0106] The lead-out structure is formed in a region of the gate trench. The gate conductive material layer 6 in the lead-out structure formation region is removed, and a first dielectric layer 8a is filled in the region where the gate conductive material layer 6 is removed.

[0107] A first through hole 14 is formed at the top of the formation area of ​​the lead-out structure, the top of the first through hole 14 contacts the front metal layer 9 corresponding to the source, and the bottom of the first through hole 14 passes through the interlayer film 8, the first dielectric layer 8a and the gate dielectric layer 7 and contacts the bottom doped region 10.

[0108] Depend on Figure 3 As shown, the figure 11 corresponds to the layout for defining the gate trench in the photolithography, that is, the shape of the formed gate trench is completely defined by the figure 11, and the figure 11 is a strip structure; the figure 12 corresponds to the layout for defining the formation area of ​​the lead-out structure in the photolithography, and the gate conductive material layer 6 in the gate trench opened by the figure 12 will be removed, that is, the gate conductive material layer 6 in the intersection area of ​​the figures 11 and 12 will be removed, and the first dielectric layer 8a will be formed. The first dielectric layer 8a can be referred to Figure 4B shown.

[0109] In the embodiment of the present invention, the SiC epitaxial layer 2 is formed on a SiC substrate 1, the SiC substrate 1 is heavily doped with a first conductivity type, and the drain region is composed of the thinned SiC substrate 1 or is formed by back ion implantation of the thinned SiC substrate 1.

[0110] A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0111] The device unit region of the SiC MOSFET device is formed by connecting a plurality of the device units in parallel.

[0112] In top view, the device unit is a strip-shaped structure. In other embodiments, the device unit can also be a polygonal structure; the polygonal structure includes a square or a hexagon. Figure 3 As shown, although the strip structure corresponding to the figure 11 is also a rectangle, as the device unit, the device unit of the strip structure is arranged in the device unit area only along one direction, that is, the width direction of the strip corresponding to the figure 11. When the device unit is a polygonal structure, the polygonal structure will be arranged symmetrically in the X direction and the Y direction.

[0113] When the device unit is a strip structure, the gate trench is strip-shaped, that is, Figure 3 The bar definition corresponding to Figure 11.

[0114] The gate trenches and the mesa regions between the gate trenches are alternately arranged along a width direction of the gate trenches.

[0115] In the length direction of the gate trench, the formation area of ​​the lead-out structure is located at one or more positions along the length direction of the gate trench, and the formation area of ​​the lead-out structure includes both ends or the middle position of the gate trench along the length direction. Figure 3As shown, the formation area of ​​the lead-out structure corresponding to the graph 12 is located at a position along the length direction of the gate trench and the position is the middle position of the formation area of ​​the lead-out structure including the gate trench along the length direction. Figure 5 As shown, it is a second photolithography layout of the lead-out structure of the bottom doping region of the SiC MOSFET device according to an embodiment of the present invention; it can be seen that the formation area of ​​the lead-out structure corresponding to Figure 12 is located at two positions along the length direction of the gate trench and the two positions are the formation area of ​​the lead-out structure including the two end positions of the gate trench along the length direction.

[0116] The width of the gate trench in the region where the lead-out structure is formed is greater than or equal to the width of the gate trench outside the region where the lead-out structure is formed. Figure 3 As shown in FIG. 1 , the width of the gate trench in the region where the lead-out structure is formed is equal to the width of the gate trench outside the region where the lead-out structure is formed. Figure 6 As shown, it is a third photolithography layout of the lead-out structure of the bottom doping region of the SiC MOSFET device in an embodiment of the present invention, and the width of the gate trench in the formation area of ​​the lead-out structure is greater than the width of the gate trench outside the formation area of ​​the lead-out structure; that is, the width of the gate trench corresponding to the intersection of Figure 12 and Figure 11 is greater.

[0117] The material of the gate dielectric layer 7 includes an oxide layer. Preferably, the gate dielectric layer 7 is formed by a thermal oxidation process and then annealed in a nitrogen atmosphere to improve the mobility of channel carriers.

[0118] The gate conductive material layer 6 is made of polysilicon.

[0119] The maximum depth of the gate trench is more than 1 micron. Figure 6 The layout structure shown is helpful to reduce the difficulty of etching the gate conductive material layer 6 .

[0120] Preferably, the first dielectric layer 8a is composed of the interlayer film 8, so that the step of separately forming the first dielectric layer 8a can be omitted.

[0121] In the embodiment of the present invention, in addition to the first through hole 14 , corresponding through holes are also formed on the top of the source region 5 and the gate conductive material layer 6 , respectively. Each of the through holes passes through the interlayer film 8 . Figure 4A In the embodiment, an ohmic contact region 4 heavily doped with the second conductivity type is also formed at the bottom of the through hole of the source region 5 pair, so as to realize the ohmic contact between the through hole and the channel region 3 at the bottom.

[0122] In the embodiment of the present invention, the SiC MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. The P-type doping impurities include aluminum, the N-type doping impurities include nitrogen, and the material of the front metal layer 11 includes TiNiAl.

[0123] The embodiment of the present invention can form a bottom doped region 10 connected to the source at the bottom of the gate trench, thereby reducing the electric field strength of the gate dielectric layer 7 at the bottom surface of the gate trench and improving the reliability of the gate dielectric layer 7.

[0124] At the same time, in the embodiment of the present invention, the lead-out structure connecting the bottom doped region 10 to the source is achieved by removing the gate conductive material layer 6 in a partial area of ​​the gate trench, then filling the first dielectric layer 8a and forming a first through hole 14 at the bottom passing through the first dielectric layer 8a. This lead-out structure does not require high-energy ion implantation, so it is easy to implement and the final process cost will also be reduced.

[0125] The manufacturing method of the SiC MOSFET device according to the embodiment of the present invention:

[0126] In the method for manufacturing a SiC MOSFET device according to an embodiment of the present invention, the step of forming a device unit includes:

[0127] Step 1: forming a SiC epitaxial layer 2 doped with a first conductivity type, wherein a gate trench is formed in the SiC epitaxial layer 2 .

[0128] like Figure 3 As shown, the gate trench adopts Figure 3 The layout graphic definition of the photolithography plate corresponding to Figure 11.

[0129] In the method of the embodiment of the present invention, the SiC epitaxial layer 2 is formed on a SiC substrate 1, and the SiC substrate 1 is heavily doped with a first conductivity type.

[0130] Step 2: Perform second conductivity type ion implantation to form a bottom doped region 10 in the SiC epitaxial layer 2 below the bottom surface of the gate trench.

[0131] Step three: the gate dielectric layer 7 is on the inner surface of the gate trench; the top surface of the bottom doped region 10 is in contact with the bottom surface of the gate dielectric layer 7 at the bottom surface of the gate trench.

[0132] In the method of the embodiment of the present invention, the material of the gate dielectric layer 7 includes an oxide layer. Preferably, the gate dielectric layer 7 is formed by a thermal oxidation process and then annealed in a nitrogen atmosphere to improve the mobility of channel carriers.

[0133] Step 4: Filling the gate conductive material layer 6 in the gate trench formed with the gate dielectric layer 7.

[0134] In the method of the embodiment of the present invention, the material of the gate conductive material layer 6 includes polysilicon. The steps of forming the gate conductive material layer 6 include:

[0135] First, the polysilicon corresponding to the gate conductive material layer 6 is deposited to a thickness of It can also be At this time, it depends on whether the top lead-out structure of the gate conductive material layer 6, i.e., the position of the through hole is inside or outside the gate trench. If it is outside the gate trench, an additional photoresist (Mask) is required. If the through hole at the top of the gate conductive material layer 6 is directly inside the trench, then the chemical mechanical polishing (CMP) of the polysilicon of the gate conductive material layer 6 can be performed to grind off the polysilicon on the surface of the mesa area (Mesa) between the gate trenches, or the polysilicon can be directly etched back.

[0136] Step five: forming a second conductive type doped channel region 3 in the SiC epitaxial layer 2, wherein the channel region 3 extends downward from the top surface of the SiC epitaxial layer 2, and the gate conductive material layer 6 vertically passes through the channel region 3, and the surface of the channel region 3 is covered by the side of the gate conductive material layer 6 to form a conductive channel.

[0137] The SiC epitaxial layer 2 at the bottom of the channel region 3 constitutes a drift region.

[0138] Step six: forming a source region 5 composed of a heavily doped region of the first conductivity type on the surface of the channel region 3 .

[0139] Step seven: removing the gate conductive material layer 6 in the region where the lead-out structure connecting the bottom doped region 10 to the source is formed.

[0140] Step 7 is the most important step in the method of the embodiment of the present invention and requires Figure 3 The pattern 12 in the figure is defined by photolithography and forms a photoresist (PR) pattern. After that, the polysilicon in the area covered by the pattern 12 is completely etched away using the photoresist pattern as a mask.

[0141] Step eight: filling a first dielectric layer 8a in the region of the gate trench where the gate conductive material layer 6 is removed.

[0142] Step nine: forming an interlayer film 8.

[0143] In the method of the embodiment of the present invention, preferably, the first dielectric layer 8a is composed of the interlayer film 8, so that the step of forming the first dielectric layer 8a separately can be omitted. The interlayer film 8 will completely fill the remaining position after the polysilicon corresponding to the pattern 12 of the photoresist is etched away.

[0144] Through hole, front metal layer 9, the front metal layer 9 is patterned to form a source and a gate; the top of the gate conductive material layer 6 is connected to the gate through a corresponding through hole, and the top of the source region 5 is connected to the source through a corresponding through hole.

[0145] The through hole located at the top of the formation area of ​​the lead-out structure is called the first through hole 14, the top of the first through hole 14 is in contact with the front metal layer 9 corresponding to the source, and the bottom of the first through hole 14 passes through the interlayer film 8, the first dielectric layer 8a and the gate dielectric layer 7 and is in contact with the bottom doped region 10.

[0146] The structure in which the bottom doped region 10 is connected to the source makes the voltage borne by the gate dielectric layer 7 at the bottom surface of the gate trench determined by the voltage difference between the source and the gate, thereby reducing the electric field strength borne by the gate dielectric layer 7 at the bottom surface of the gate trench.

[0147] The process for forming the through hole comprises:

[0148] Performing photolithography definition to open the formation area of ​​the through hole;

[0149] After that, etching is performed to form the opening of the through hole. For the through hole at the gate conductive material layer 6 and the top of the source region 5, the corresponding interlayer film 8 needs to be etched to form the opening of the through hole; for the first through hole 14, in addition to etching the interlayer film 8, the first dielectric layer 8a and the gate dielectric layer 7 need to be etched. That is, a relatively large overetch (OverEtch) will be added during the through hole etching, and the insulating layer will be completely etched away, and it will stop at the SiC.

[0150] After step nine, the following backside processes are also included:

[0151] The SiC substrate 1 is thinned.

[0152] A drain region is formed, wherein the drain region is composed of the thinned SiC substrate 1 or is formed by performing back ion implantation on the thinned SiC substrate 1 .

[0153] A back metal layer is formed on the back side of the drain region and the drain electrode is formed by the back metal layer.

[0154] In the method of the embodiment of the present invention, the device unit area of ​​the SiC MOSFET device is formed by connecting a plurality of the device units in parallel.

[0155] In a top view, the device unit is a stripe structure. In other embodiments, the device unit can be a polygonal structure; the polygonal structure includes a square or a hexagon.

[0156] When the device unit is a stripe structure, the gate trench is in a stripe shape. The gate trenches and the mesa regions between the gate trenches are alternately arranged along the width direction of the gate trenches.

[0157] Along the length direction of the gate trench, the formation region of the lead-out structure is located at one or more positions along the length direction of the gate trench, and the formation region of the lead-out structure includes both ends or a middle position of the gate trench along the length direction.

[0158] The width of the gate trench in the region where the lead-out structure is formed is greater than or equal to the width of the gate trench outside the region where the lead-out structure is formed. The maximum depth of the gate trench is more than 1 micron. Figure 6 As shown, by setting the width of the gate trench in the formation area of ​​the lead-out structure to be greater than the width of the gate trench outside the formation area of ​​the lead-out structure, the difficulty of etching the opening of the first through hole 14 can be reduced, because when the width of the gate trench is enlarged, the opening width of the first through hole 14 can also be enlarged, that is, Figure 6 The width of the layout pattern corresponding to the middle pattern 13 will be enlarged, thereby reducing the difficulty of etching the opening of the first through hole 14.

[0159] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A SiC MOSFET device, characterized in that: The device unit includes: A SiC epitaxial layer doped with a first conductivity type, wherein a trench gate is formed in the SiC epitaxial layer; The trench gate comprises a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; A bottom doped region is formed in the SiC epitaxial layer below the bottom surface of the gate trench, the bottom doped region has a second conductivity type doping, and a top surface of the bottom doped region contacts a bottom surface of the gate dielectric layer at the bottom surface of the gate trench; A channel region doped with a second conductivity type is formed in the SiC epitaxial layer, the channel region extends downward from the top surface of the SiC epitaxial layer, the gate conductive material layer vertically passes through the channel region, and the surface of the channel region is covered by the side of the gate conductive material layer to form a conductive channel; The SiC epitaxial layer at the bottom of the channel region constitutes a drift region; A source region composed of a heavily doped region of the first conductivity type is formed on the surface of the channel region; The top of the gate conductive material layer is connected to the gate composed of the front metal layer; The top of the source region is connected to a source electrode composed of a front metal layer; The bottom doped region is connected to the source, so that the voltage borne by the gate dielectric layer at the bottom surface of the gate trench is determined by the voltage difference between the source and the gate, thereby reducing the electric field strength borne by the gate dielectric layer at the bottom surface of the gate trench; The lead-out structure of the bottom doped region connected to the source electrode comprises: The lead-out structure is formed in a region of the gate trench, the gate conductive material layer in the lead-out structure is removed, and a first dielectric layer is filled in the region where the gate conductive material layer is removed; A first through hole is formed at the top of the formation area of ​​the lead-out structure, the top of the first through hole contacts the front metal layer corresponding to the source, and the bottom of the first through hole passes through the interlayer film, the first dielectric layer and the gate dielectric layer and contacts the bottom doped area.

2. The SiC MOSFET device according to claim 1, wherein: The SiC epitaxial layer is formed on a SiC substrate, the SiC substrate is heavily doped with a first conductivity type, and the drain region is composed of the thinned SiC substrate or is formed by back ion implantation of the thinned SiC substrate; A drain electrode composed of a back metal layer is formed on the back side of the drain region.

3. The SiC MOSFET device according to claim 2, characterized in that: The device unit area of ​​the SiC MOSFET device is formed by connecting a plurality of the device units in parallel; In top view, the device unit is a strip structure or a polygonal structure; The polygonal structure includes a square or a hexagon.

4. The SiC MOSFET device according to claim 3, characterized in that: The device unit is a strip-shaped structure, and the gate trench is a strip-shaped structure; The gate trenches and the mesa regions between the gate trenches are alternately arranged along a width direction of the gate trenches.

5. The SiC MOSFET device according to claim 4, characterized in that: Along the length direction of the gate trench, the formation region of the lead-out structure is located at one or more positions along the length direction of the gate trench, and the formation region of the lead-out structure includes both ends or a middle position of the gate trench along the length direction.

6. The SiC MOSFET device according to claim 5, characterized in that: A width of the gate trench in a region where the lead-out structure is formed is greater than or equal to a width of the gate trench outside the region where the lead-out structure is formed.

7. The SiC MOSFET device according to claim 1, wherein: The material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

8. The SiC MOSFET device according to claim 1 or 6, characterized in that: The maximum depth of the gate trench is more than 1 micron.

9. The SiC MOSFET device according to claim 1, wherein: The first dielectric layer is composed of the interlayer film.

10. A method for manufacturing a SiC MOSFET device, characterized in that: The steps of forming a device unit include: Step 1: forming a SiC epitaxial layer doped with a first conductivity type, wherein a gate trench is formed in the SiC epitaxial layer; Step 2: implanting ions of a second conductive type into the SiC epitaxial layer below the bottom surface of the gate trench to form a bottom doped region; Step 3: a gate dielectric layer on the inner surface of the gate trench; a top surface of the bottom doped region contacts a bottom surface of the gate dielectric layer on the bottom surface of the gate trench; Step 4: filling a gate conductive material layer in the gate trench formed with the gate dielectric layer; Step 5: forming a second conductive type doped channel region in the SiC epitaxial layer, wherein the channel region extends downward from the top surface of the SiC epitaxial layer, and the gate conductive material layer vertically passes through the channel region, and the surface of the channel region is covered by the side of the gate conductive material layer to form a conductive channel; The SiC epitaxial layer at the bottom of the channel region constitutes a drift region; Step 6: forming a source region composed of a heavily doped region of the first conductivity type on the surface of the channel region; Step 7, removing the gate conductive material layer in the formation area of ​​the lead-out structure connecting the bottom doped region to the source; Step eight, filling a first dielectric layer in the region of the gate trench where the gate conductive material layer is removed; Step nine, forming an interlayer film, a through hole, and a front metal layer, and patterning the front metal layer to form a source electrode and a gate electrode; the top of the gate conductive material layer is connected to the gate electrode through a corresponding through hole, and the top of the source region is connected to the source electrode through a corresponding through hole; The through hole located at the top of the formation area of ​​the lead-out structure is called a first through hole, the top of the first through hole is in contact with the front metal layer corresponding to the source electrode, and the bottom of the first through hole passes through the interlayer film, the first dielectric layer and the gate dielectric layer and is in contact with the bottom doped region; The structure in which the bottom doped region is connected to the source makes the voltage borne by the gate dielectric layer at the bottom surface of the gate trench determined by the voltage difference between the source and the gate, thereby reducing the electric field strength borne by the gate dielectric layer at the bottom surface of the gate trench.

11. The method for manufacturing a SiC MOSFET device according to claim 10, characterized in that: In step 1, the SiC epitaxial layer is formed on a SiC substrate, and the SiC substrate is heavily doped with a first conductivity type; After step nine, the following backside processes are also included: Thinning the SiC substrate; forming a drain region, wherein the drain region is composed of the thinned SiC substrate or is formed by performing back ion implantation on the thinned SiC substrate; A back metal layer is formed on the back side of the drain region and the drain electrode is formed by the back metal layer.

12. The method for manufacturing a SiC MOSFET device according to claim 11, wherein: The device unit area of ​​the SiC MOSFET device is formed by connecting a plurality of the device units in parallel; In top view, the device unit is a strip structure or a polygonal structure; The polygonal structure includes a square or a hexagon.

13. The method for manufacturing a SiC MOSFET device according to claim 12, wherein: The device unit is a strip-shaped structure, and the gate trench is a strip-shaped structure; The gate trenches and the mesa regions between the gate trenches are alternately arranged along a width direction of the gate trenches.

14. The method for manufacturing a SiC MOSFET device according to claim 13, wherein: Along the length direction of the gate trench, the formation region of the lead-out structure is located at one or more positions along the length direction of the gate trench, and the formation region of the lead-out structure includes both ends or a middle position of the gate trench along the length direction.

15. The method for manufacturing a SiC MOSFET device according to claim 14, wherein: A width of the gate trench in a region where the lead-out structure is formed is greater than or equal to a width of the gate trench outside the region where the lead-out structure is formed.

16. The method for manufacturing a SiC MOSFET device according to claim 10, wherein: The material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

17. The method for manufacturing a SiC MOSFET device according to claim 10 or 15, characterized in that: The maximum depth of the gate trench is more than 1 micron.

18. The method for manufacturing a SiC MOSFET device according to claim 10, wherein: The first dielectric layer is composed of the interlayer film, and step eight is merged into the formation process of the interlayer film in step nine.

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