VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) integrated with channel diode and preparation method of VDMOS

Abstract

The VDMOS comprises a first conductive layer, an N + substrate layer, an N-epitaxial layer and a source gate structure which are sequentially stacked from bottom to top, and further comprises two first P-body regions which are symmetrically arranged at the top of the N-epitaxial layer, and first NSD regions are embedded in the top surfaces of the first P-body regions; the groove structure is arranged in the middle of the top of the N-epitaxial layer, and the two first P-body regions are arranged on the two sides of the groove structure; the trench structure includes a second P-body region, a second NSD region, and a LOCOS oxide layer. According to the invention, the channel of a common VDMOS is not changed and is ensured to participate in the forward conduction process, so that the channel density is not reduced, and the current capability and the conduction resistance of the device are not deteriorated; during reverse conduction, the source electrode and the grid electrode of the channel diode are in short circuit, current flows to the drain electrode from the source electrode of the VDMOS through the opened channel diode, minority carrier injection caused by conduction of the body diode is reduced, reverse recovery charge and reverse recovery time are reduced, and the reverse recovery performance of the device is optimized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a VDMOS with an integrated trench diode and a preparation method thereof. Background Art

[0002] As the operating frequency of MOSFET application circuits increases, the reverse recovery characteristics of the device have an increasingly prominent impact on the switching speed and switching loss. However, the reverse recovery characteristics of the parasitic body diode of ordinary MOSFET devices are very poor, which seriously limits the operating frequency of the device. Integrating a channel diode in a MOSFET primitive is a feasible method to optimize the reverse recovery characteristics of the device. The channel diode does not turn on when the device is forward-conducting, but turns on before the body diode during the reverse recovery phase of the device. Most of the reverse conduction current flows out through it, optimizing the reverse recovery characteristics of the device.

[0003] Patent document CN111769158A, published on October 13, 2020, discloses a dual-channel superjunction VDMOS device with low reverse recovery charge and a manufacturing method. In its technical solution: a source electrode is established above the gate electrode region and the JFET region, respectively, and an N-pillar region, a P-body region, and an N+ source region are newly established above the JFET in sequence, so that the gate electrode of the device is divided into multiple regions. The newly added region, source, and gate separate the entire gate to form a separated gate, and a source electrode is added. Its beneficial effect is that while maintaining the breakdown voltage and on-state current handling capability of the superjunction VDMOS, the stored charge of the parasitic diode in the body is reduced, and the reverse recovery characteristics of the device are improved.

[0004] After analyzing the structure of the current devices with integrated channel diodes, it is not difficult to see that when the channel diode is integrated in the silicon-based MOSFET device, because the channel diode will occupy a channel during forward conduction, it will cause the device channel density to decrease, the current capability to decrease, the characteristic on-resistance to increase and other problems. Therefore, a VDMOS with integrated channel diode and a preparation method thereof are urgently needed to solve the above problems. Summary of the invention

[0005] The object of the present invention is to provide a VDMOS with an integrated trench diode and a method for preparing the same, so as to solve the above-mentioned deficiencies in the prior art.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A VDMOS with an integrated trench diode comprises a first conductive layer, an N+ substrate layer, an N-epitaxial layer and a source-gate structure which are stacked in sequence from bottom to top, and further comprises: a first P-body region, which is symmetrically arranged as two on the top of the N-epitaxial layer, and a first NSD region is embedded in the top surface of the first P-body region; a trench structure, which is arranged in the middle of the top of the N-epitaxial layer, and the two first P-body regions are arranged on both sides of the trench structure; the trench structure comprises a second P-body region, a second NSD region and a LOCOS oxide layer, the second P-body region is located at the bottom of the trench structure, the second NSD region is embedded in the upper part of the second P-body region, and the LOCOS oxide layer covers the upper surface of the second P-body region and is arranged avoiding the second NSD region; the source-gate structure comprises an insulating oxide, a polysilicon gate and a second conductive layer; the insulating oxide is arranged between the first P-body region and the second P-body region, and one end of the insulating oxide extends to the upper surface of the first P-body region and the other end extends to the upper surface of the LOCOS oxide layer; the polysilicon gate is embedded in the insulating oxide; and the second conductive layer is arranged to cover the upper surfaces of the structures on the top of the N-epitaxial layer.

[0008] Preferably, two insulating oxides are symmetrically arranged, and the distance between the two is greater than the width of the upper surface of the trench structure.

[0009] Preferably, the insulating oxide includes GOX at the bottom of the polysilicon gate and BPSG at the top and side surfaces of the polysilicon gate.

[0010] Preferably, the second P-body region, the second NSD region, the LOCOS oxide layer, the N-epitaxial layer and the second conductive layer constitute a channel diode, the N-epitaxial layer is the drain of the channel diode, and the second conductive layer is both the source and the gate of the channel diode.

[0011] Preferably, the source and gate of the channel diode are short-circuited.

[0012] A preparation method for preparing the VDMOS with integrated trench diode, comprising the following steps:

[0013] S1: Prepare substrate and grow epitaxial: grow epitaxial wafer as wafer on top of N-type (100) crystal orientation substrate;

[0014] S2: Initial oxygen, Ring injection, field oxygen growth and Ring push: Grow an oxide layer with a thickness of 500-3000 angstroms on the surface of the wafer; Form a barrier layer for Ring injection by photolithography and etching the oxide layer, and then inject B element on the surface of the wafer with an energy of 50-120kev and a dose of 1E13-5E13; Grow an oxide layer with a thickness of 10000-20000 angstroms on the surface of the wafer as a field plate structure; Form an active area by photolithography and etching the field oxide layer;

[0015] S3: JFET injection, push-in, gate oxidation to form the first layer of gate oxide GOX: P ions are injected into the wafer surface with an energy of 120Kev-160Kev and a dose of 1E12-9E12, and a high-temperature well is pushed through a furnace tube to form a JFET area; a layer of gate oxide GOX of 600-1000 angstroms is grown on the wafer surface;

[0016] S4: Deposition of polysilicon Poly: Depositing a layer of polysilicon with a thickness of 8000 angstroms and a sheet resistance of 8-12 on the surface of the wafer;

[0017] S5: Etching Poly, injecting windows into P-body: photolithography and etching the required areas on polysilicon;

[0018] S6: P-body injection, P-well first push: inject B element on the wafer surface with energy of 40-120Kev and dosage of 4E13-6E13; then push the well at high temperature in the furnace tube to form the P-well of ordinary VDMOS;

[0019] S7: Second Poly etching: Etch a window of appropriate size in the middle of the source region Poly as the AA region of the channel diode, and retain an oxide layer of appropriate thickness;

[0020] S8: Deposit SIN of appropriate thickness and etch away the excess part: Deposit SIN of appropriate thickness on the surface of the wafer, and use photolithography to etch away the excess part of SIN, leaving only a part of SIN in the AA area of ​​the channel diode;

[0021] S9: thermal oxygen growth of LOCOS oxide layer: using a dry oxygen process to grow a LOCOS oxide layer of appropriate thickness in the AA region of the channel diode as the gate oxide of the channel diode;

[0022] S10: inject B and push the well to form the P-body of the channel diode: inject B ions and push the well in the furnace tube to form the P-Well of the channel diode;

[0023] S11: N+ implantation, removal of SIN and surface silicon dioxide in the AA region of the channel diode, N+ annealing, P+ implantation: through photolithography, a window for N+ area implantation is formed; then P ions are implanted on the wafer surface with an energy of 40-80kev and a dose of 6E15-10E15; SIN and excess SIO2 in the AA region of the channel diode are removed, and LPCVD is used to deposit SIN to cover the steps to provide a mask layer for P+ implantation; photoresist is used to block the AA region of the channel diode from P+ implantation, and B elements are implanted with an energy of 80-140kev and a dose of 2-4E15 to further increase the ion concentration;

[0024] S12: BPSG deposition, hole etching: BPSG is deposited to form a dielectric layer, and the dielectric layer and the hole are photolithographically and etched using a mask for the hole. The width of the hole in the trench diode must be greater than the width of the trench diode P-Well.

[0025] S13: Deposit metal on the front side, thin and deposit metal on the back side: deposit 4um thick aluminum, then photoetch the aluminum to form a source and field plate.

[0026] Preferably, the substrate in S1 is doped with arsenic or phosphorus, with a resistivity of 0.001-0.05Ω.cm; the resistivity and thickness of the epitaxy are determined by the withstand voltage of different devices, usually the epitaxy thickness is 40-60um, the resistivity is 15-20Ω.cm, and the withstand voltage of the device is 400V-700V.

[0027] Preferably, before step S3, an oxide layer with a thickness of 500 angstroms is grown on the basis of etching the field oxide to alleviate the lattice damage caused by ion implantation.

[0028] Preferably, in S10, the injection depth of B ions in SIN is deeper than that in SIO2. By adjusting the thickness of SIN and LOCOS oxide layers, B ions pass through SIN but are blocked by LOCOS oxide layers, thereby ensuring the formation of P-Well of the channel diode. The turn-on voltage of the channel diode is less than 0.7V, so the injection dose and energy of B ions in this step are small, and the heat of pushing the well is low, so S10 has no effect on the P-Well of ordinary VDMOS.

[0029] Preferably, in S13, a certain proportion of SiCu may be doped into aluminum to prevent aluminum and silicon from dissolving each other.

[0030] In the above technical solution, the beneficial effects of the present invention are:

[0031] The VDMOS with integrated trench diode ensures that all channels of the ordinary VDMOS participate in the forward conduction process by not changing the channels of the ordinary VDMOS, so the channel density is not reduced, and the current capability and on-resistance of the device will not deteriorate;

[0032] During reverse conduction, the second NSD region is in direct contact with the second conductive layer, causing the source and gate of the channel diode to be short-circuited. When the voltage at the second conductive layer end is greater than the turn-on voltage of the channel diode, the channel diode is turned on, and most of the reverse conduction current flows between the source and drain electrodes through the channel diode, reducing the minority carrier injection caused by the body diode conduction, thereby reducing the reverse recovery charge and reverse recovery time, and optimizing the reverse recovery performance of the device;

[0033] Similarly, because the structure of the channel diode is integrated into the structure of the ordinary VDMOS, the density of the channel diode can increase with the increase of the chip area. A larger channel diode density can improve the current capacity of the channel diode and increase the reverse conduction current flowing through the channel diode.

[0034] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

[0035] This application document provides an overview of various implementations or examples of the technology described in the present disclosure, and is not a comprehensive disclosure of the entire scope or all features of the disclosed technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0037] Figure 1 A schematic diagram of the overall structure of a VDMOS with an integrated trench diode provided in an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of the overall structure of the product obtained by S1 in the preparation method provided in an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the overall structure of the product obtained by S2 in the preparation method provided in an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of the overall structure of the product obtained by S3 in the preparation method provided in an embodiment of the present invention;

[0041] Figure 5A schematic diagram of the overall structure of the product obtained by S4 in the preparation method provided in an embodiment of the present invention;

[0042] Figure 6 A schematic diagram of the overall structure of the product obtained by S5 in the preparation method provided in an embodiment of the present invention;

[0043] Figure 7 A schematic diagram of the overall structure of the product obtained by S6 in the preparation method provided in an embodiment of the present invention;

[0044] Figure 8 A schematic diagram of the overall structure of the product obtained by S7 in the preparation method provided in an embodiment of the present invention;

[0045] Fig. 9 A schematic diagram of the overall structure of the product obtained by S8 in the preparation method provided in an embodiment of the present invention;

[0046] Fig.10 A schematic diagram of the overall structure of the product obtained by S9 in the preparation method provided in an embodiment of the present invention;

[0047] Fig.11 A schematic diagram of the overall structure of the product obtained by S10 in the preparation method provided in an embodiment of the present invention;

[0048] Fig.12 A schematic diagram of the overall structure of the product obtained by S11 in the preparation method provided in an embodiment of the present invention;

[0049] Fig.13 A schematic diagram of the overall structure of the product obtained by S12 in the preparation method provided in an embodiment of the present invention;

[0050] Fig.14 This is a schematic diagram of the overall structure of the product obtained by S13 in the preparation method provided in an embodiment of the present invention.

[0051] Description of reference numerals:

[0052] 1. First conductive layer; 2. N+ substrate layer; 3. N- epitaxial layer; 4. First P-body region; 5. First NSD region; 6. Second P-body region; 7. Second NSD region; 8. LOCOS oxide layer; 9. Insulating oxide; 10. Polysilicon gate; 11. Second conductive layer. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0054] See also Figure 1 A VDMOS with an integrated trench diode provided in an embodiment of the present invention comprises a first conductive layer 1, an N+ substrate layer 2, an N-epitaxial layer 3 and a source-gate structure stacked in sequence from bottom to top, and further comprises: a first P-body region 4, which is symmetrically arranged as two on the top of the N-epitaxial layer 3, and a first NSD region 5 is embedded in the top surface thereof; a trench structure, which is arranged in the middle of the top of the N-epitaxial layer 3, and the two first P-body regions 4 are arranged on both sides of the trench structure; the trench structure comprises a second P-body region 6, a second NSD region 7 and a LOCOS oxide layer 8, and the second P-body region 6 is located at the bottom of the trench structure, The second NSD region 7 is embedded in the upper part of the second P-body region 6, and the LOCOS oxide layer 8 covers the upper surface of the second P-body region (6) and is arranged avoiding the second NSD region 7; the source-gate structure includes an insulating oxide 9, a polysilicon gate 10 and a second conductive layer 11; the insulating oxide 9 is arranged between the first P-body region 4 and the second P-body region 6, and one end extends to the upper surface of the first P-body region 4, and the other end extends to the upper surface of the LOCOS oxide layer 8; the polysilicon gate 10 is embedded in the insulating oxide 9; and the second conductive layer 11 covers the upper surface of each structure on the top of the N-epitaxial layer 3.

[0055] Specifically, the first conductive layer 1 is a metal layer; the N+ substrate layer 2 is made of an N-type single crystal silicon wafer, and the N+ substrate layer 2 is doped with arsenic or phosphorus; the N-epitaxial layer 3 is formed by a layer of single crystal silicon grown on the N+ substrate layer 2. The first P-body region 4 is embedded in the top side of the N-epitaxial layer 3, and the upper surface of the first P-body region 4 is flush with the upper surface of the N-epitaxial layer 3; the upper surface of the first NSD region 5 is flush with the upper surface of the first P-body region 4, and the first P-body region 4 is arranged in a U shape around the first NSD region 5. The trench structure is spaced apart from the first P-body region 4, and the spaced apart portion is the N-epitaxial layer 3; the upper surface of the second P-body region 6 is flush with the lower surface of the LOCOS oxide layer 8, the upper surface of the LOCOS oxide layer 8 is flush with the upper surface of the second NSD region 7, and the upper surface of the LOCOS oxide layer 8 is flush with or lower than the upper surface of the N-epitaxial layer 3; the extension width of the LOCOS oxide layer 8 in the direction of the first P-body region 4 on the same side thereof is greater than that of the second P-body region 6; the second P-body region 6 is arranged in a U-shape surrounding the second NSD region 7. The lower surface of the portion of the insulating oxide 9 extending toward the first P-body region 4 is flush with the upper surface of the first P-body region 4, and the coverage width extends to about half of the upper surface of the first NSD region 5; the portion of the insulating oxide 9 extending toward the second P-body region 6 has a coverage width extending to about half of the upper surface of the LOCOS oxide layer 8 on the same side, and the lower surface of the insulating oxide 9 at this end is flush with the upper surface of the LOCOS oxide layer 8; the coverage width of the polysilicon gate 10 extending toward the first P-body region 4 extends to about half of the upper surface of the second NSD region 5 on the same side. The polysilicon gate 10 is located on the side of the first NSD region 5 and does not overlap with the upper surface of the first NSD region 5. The coverage width of the polysilicon gate 10 extending in the direction of the second P-body region 6 extends to the side of the LOCOS oxide layer 8 on the same side and does not overlap with the upper surface of the LOCOS oxide layer 8. There is a gap between the lower surface of the polysilicon gate 10 and the N-epitaxial layer 3 and the upper surface of the first P-body region 4 covered, and the gap portion is an insulating oxide 9. The second conductive layer 11 is a metal layer, and the upper surface of the second conductive layer 11 is convexly arranged at a portion corresponding to the insulating oxide 9. Among them, the first P-body region 4, the first NSD region 5, the N-epitaxial layer 3, the polysilicon gate 10 and the second conductive layer 11 constitute a common VDMOS, the second conductive layer 11 is the source of the VOMOS, the N-epitaxial layer 3 is the drain of the VOMOS, and the polysilicon gate 10 is the gate of the VOMOS.

[0056] Compared with the prior art, the VDMOS with integrated channel diode proposed in the embodiment of the present invention does not change the channel of the ordinary VDMOS, ensuring that all channels of the ordinary VDMOS participate in the forward conduction process, so the channel density is not reduced, and the current capability and on-resistance of the device will not deteriorate; during reverse conduction, because the second NSD region 7 is in direct contact with the second conductive layer 11, the source and gate of the channel diode are short-circuited. When the voltage of the second conductive layer 11 is greater than the turn-on voltage of the channel diode, the channel diode is turned on, and most of the reverse conduction current flows between the source and drain electrodes through the channel diode, reducing the minority carrier injection caused by the body diode conduction, thereby reducing the reverse recovery charge and reverse recovery time, and optimizing the reverse recovery performance of the device; similarly, because the structure of the channel diode is integrated into the structure of the ordinary VDMOS, the density of the channel diode can increase with the increase of the chip area, and a larger channel diode density can improve the current capacity of the channel diode and increase the reverse conduction current flowing through the channel diode.

[0057] As a preferred technical solution of this embodiment, two insulating oxides 9 are symmetrically arranged, and the spacing between the two is greater than the upper surface width of the trench structure. Specifically, the spacing between the two insulating oxides 9 is the hole of the channel diode, and its width is greater than the width of the second P-body region 6, thereby allowing the width of the channel diode hole to cover the N-epitaxial layer 3, ensuring that the channel diode gate functions effectively.

[0058] As a preferred technical solution of this embodiment, the insulating oxide 9 includes GOX at the bottom of the polysilicon gate 10 and BPSG on the top and side surfaces of the polysilicon gate 10. Specifically, the extension width of GOX is consistent with the extension width of the polysilicon gate 10. GOX is used to insulate and isolate the polysilicon gate 10 from the N-epitaxial layer 3 and the first P-body region 4. GOX and BPSG are deposited and formed in two steps.

[0059] As a preferred technical solution of this embodiment, the second P-body region 6, the second NSD region 7, the LOCOS oxide layer 8, the N-epitaxial layer 3 and the second conductive layer 11 constitute a channel diode, the N-epitaxial layer 3 is the drain of the channel diode, and the second conductive layer 11 is both the source and the gate of the channel diode. Specifically, the channel diode does not occupy the channel of the normal VDMOS, the channel density of the device is not reduced, and the current capability and characteristic on-resistance of the device will not deteriorate due to the integration of the channel diode; each channel diode structure has two channels that can be turned on, and the channel density of the channel diode is greatly increased compared with the traditional device with integrated channel diodes; the channel diode is integrated in the structure of the ordinary VDMOS, and the density of the channel diode increases with the increase of the chip area. A larger channel diode density can improve the current capacity of the channel diode and increase the reverse recovery current flowing through the channel diode. When the body diode is turned on, the number of minority carriers injected is reduced, the reverse recovery charge is reduced, and the reverse recovery capability of the device is enhanced.

[0060] As a preferred technical solution of this embodiment, the source and gate of the channel diode are short-circuited. Specifically, the gate and source of the channel diode are both the second conductive layer 11, which is formed in one step, and there is no need to re-deposit Poly for the channel diode.

[0061] A preparation method, see Figure 2-14 , which is used to prepare the above-mentioned VDMOS with integrated trench diode, comprising the following steps:

[0062] S1: Prepare substrate and grow epitaxy: Grow epitaxial wafer on top of N-type (100) crystal orientation substrate as wafer, dope the substrate with arsenic or phosphorus, resistivity: 0.001-0.05Ω.cm; resistivity and thickness of epitaxy are determined by different device withstand voltage; usually epitaxy thickness: 40-60um, resistivity: 15-20Ω.cm, device withstand voltage: 400V-700V;

[0063] S2: Initial oxygen, Ring injection, field oxygen growth and Ring push: grow an oxide layer with a thickness of 500-3000 angstroms on the wafer surface; form a barrier layer for Ring injection by photolithography and etching of the initial oxygen, and then inject B element on the wafer surface with an energy of 50-120kev and a dose of 1E13-5E13; then grow a thick oxide layer with a thickness of 10000-20000 angstroms on the wafer surface as a field plate structure; form an active area by photolithography and etching of the field oxide layer; grow another oxide layer with a thickness of 500 angstroms on the basis of etching the field oxygen to alleviate the lattice damage caused by ion implantation;

[0064] S3: JFET injection, push-in, gate oxidation to form the first layer of gate oxide GOX: P ions are injected into the wafer surface with an energy of 120Kev-160Kev and a dose of 1E12-9E12. A high-temperature push-in well is performed through a furnace tube to form a JFET region; a layer of gate oxide GOX of 600-1000 angstroms is grown on the wafer surface;

[0065] S4: Deposition of polysilicon Poly: Deposition of a layer of polysilicon with a thickness of 8000 angstroms and a sheet resistance of 8-12;

[0066] S5: Etching Poly, injecting windows into P-body: photolithography and etching the required areas on polysilicon;

[0067] S6: P-Body injection, the first push of the P-well: inject B element on the surface of the wafer with an energy of 40-120Kev and a dose of 4E13-6E13; then push the well at high temperature in the furnace tube to form the P-well of ordinary VDMOS;

[0068] S7: Second Poly etching: Etch a window of appropriate size in the middle of the source region Poly as the AA region of the channel diode, and retain an oxide layer of appropriate thickness;

[0069] S8: Deposit SIN of appropriate thickness and etch away the excess part: Deposit SIN of appropriate thickness on the surface of the wafer, and use photolithography to etch away the excess part of SIN, leaving only a part of SIN in the AA area of ​​the channel diode;

[0070] S9: thermal oxygen growth of LOCOS oxide layer: using a dry oxygen process to grow a LOCOS oxide layer of appropriate thickness in the AA region of the channel diode as the gate oxide of the channel diode;

[0071] S10: Inject B and push the well to form the P-body of the channel diode: inject B ions. Because the injection depth of B ions in SIN is deeper than that in SIO2, the thickness of SIN and LOCOS oxide layers can be adjusted so that B ions pass through SIN but are blocked by the LOCOS oxide layer, and then push the well in the furnace tube to form the P-Well of the channel diode; because the turn-on voltage of the channel diode is less than 0.7V, the injection dose and energy of B ions in this step are small, and the heat of pushing the well is low, so this step has no effect on the P-Well of ordinary VDMOS;

[0072] S11: N+ implantation, removal of SIN and surface silicon dioxide in the AA region of the channel diode, N+ annealing, P+ implantation: through photolithography, a window for N+ region implantation is formed; then P ions are implanted on the wafer surface with an energy of 40-80kev and a dose of 6E15-10E15; during photolithography and development, only the area covered by SIN is opened in the channel diode, so the NSD barrier layer of the channel diode is thicker than that of ordinary VDMOS, so the depth of NSD of the channel diode is shallower and the concentration is lighter; remove SIN and excess SIO2 in the AA region of the channel diode, use LPCVD to deposit SIN to cover the step, and provide a mask layer for P+ implantation; use photoresist to block the AA region of the channel diode from P+ implantation, and inject B element with an energy of 80-140kev and a dose of 2-4E15 to further increase the ion concentration;

[0073] S12: BPSG deposition, hole etching: BPSG is deposited to form a dielectric layer, and the dielectric layer and the hole are photolithographically and etched using a mask for the hole. The width of the hole in the trench diode must be greater than the width of the trench diode P-Well.

[0074] S13: Deposit metal on the front side, thin and deposit metal on the back side: deposit 4um thick metal aluminum, a certain proportion of SiCu can be doped into the aluminum to prevent aluminum and silicon from dissolving each other, then photoetch the aluminum to form a source and field plate.

[0075] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A VDMOS with an integrated trench diode, comprising a first conductive layer (1), an N+ substrate layer (2), an N- epitaxial layer (3) and a source-gate structure stacked in sequence from bottom to top, characterized in that: Also includes: A first P-body region (4), which is symmetrically arranged in two on the top of the N-epitaxial layer (3), and a first NSD region (5) is embedded in the top surface of the first P-body region (4); A trench structure is arranged at a middle position on the top of the N-epitaxial layer (3), and two first P-body regions (4) are arranged on both sides of the trench structure; The trench structure comprises a second P-body region (6), a second NSD region (7) and a LOCOS oxide layer (8), wherein the second P-body region (6) is located at the lower part of the trench structure, the second NSD region (7) is embedded in the upper part of the second P-body region (6), and the LOCOS oxide layer (8) covers the upper surface of the second P-body region (6) and is arranged to avoid the second NSD region (7); The source-gate structure comprises an insulating oxide (9), a polysilicon gate (10) and a second conductive layer (11); the insulating oxide (9) is arranged between a first P-body region (4) and a second P-body region (6), and one end of the insulating oxide (9) extends to the upper surface of the first P-body region (4), and the other end of the insulating oxide (9) extends to the upper surface of the LOCOS oxide layer (8); the polysilicon gate (10) is embedded in the insulating oxide (9); and the second conductive layer (11) covers the upper surface of each structure on the top of the N-epitaxial layer (3).

2. The VDMOS with integrated trench diode according to claim 1, characterized in that: Two insulating oxides (9) are symmetrically arranged, and the distance between the two is greater than the width of the upper surface of the groove structure.

3. The VDMOS with integrated trench diode according to claim 1, characterized in that: The insulating oxide (9) comprises GOX at the bottom of the polysilicon gate (10) and BPSG at the top and side surfaces of the polysilicon gate (10).

4. The VDMOS with integrated trench diode according to claim 1, characterized in that: The second P-body region (6), the second NSD region (7), the LOCOS oxide layer (8), the N-epitaxial layer (3) and the second conductive layer (11) constitute a channel diode, the N-epitaxial layer (3) is the drain of the channel diode, and the second conductive layer (11) is both the source and the gate of the channel diode.

5. The VDMOS with integrated trench diode according to claim 4, characterized in that: The source and gate of the trench diode are short-circuited.

6. A preparation method for preparing the VDMOS with integrated trench diode according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1: Prepare substrate and grow epitaxial: grow epitaxial wafer as wafer on top of N-type (100) crystal orientation substrate; S2: Initial oxygen, Ring injection, field oxygen growth and Ring push: Grow an oxide layer with a thickness of 500-3000 angstroms on the surface of the wafer; Form a barrier layer for Ring injection by photolithography and etching the oxide layer, and then inject B element on the surface of the wafer with an energy of 50-120kev and a dose of 1E13-5E13; Grow an oxide layer with a thickness of 10000-20000 angstroms on the surface of the wafer as a field plate structure; Form an active area by photolithography and etching the field oxide layer; S3: JFET injection, push-in, gate oxidation to form the first layer of gate oxide GOX: P ions are injected into the wafer surface with an energy of 120Kev-160Kev and a dose of 1E12-9E12, and a high-temperature well is pushed through a furnace tube to form a JFET area; a layer of gate oxide GOX of 600-1000 angstroms is grown on the wafer surface; S4: Deposition of polysilicon Poly: Depositing a layer of polysilicon with a thickness of 8000 angstroms and a sheet resistance of 8-12 on the surface of the wafer; S5: Etching Poly, injecting windows into P-body: photolithography and etching the required areas on polysilicon; S6: P-body injection, P-well first push: inject B element on the wafer surface with energy of 40-120Kev and dosage of 4E13-6E13; then push the well at high temperature in the furnace tube to form the P-well of ordinary VDMOS; S7: Second Poly etching: Etch a window of appropriate size in the middle of the source region Poly as the AA region of the channel diode, and retain an oxide layer of appropriate thickness; S8: Deposit SIN of appropriate thickness and etch away the excess part: Deposit SIN of appropriate thickness on the surface of the wafer, and use photolithography to etch away the excess part of SIN, leaving only a part of SIN in the AA area of ​​the channel diode; S9: thermal oxygen growth of LOCOS oxide layer: using a dry oxygen process to grow a LOCOS oxide layer of appropriate thickness in the AA region of the channel diode as the gate oxide of the channel diode; S10: inject B and push the well to form the P-body of the channel diode: inject B ions and push the well in the furnace tube to form the P-Well of the channel diode; S11: N+ implantation, removal of SIN and surface silicon dioxide in the AA region of the channel diode, N+ annealing, P+ implantation: through photolithography, a window for N+ area implantation is formed; then P ions are implanted on the wafer surface with an energy of 40-80Kev and a dose of 6E15-10E15; SIN and excess SIO2 in the AA region of the channel diode are removed, and SIN is deposited using LPCVD to cover the step to provide a mask layer for P+ implantation; Use photoresist to block the AA area of ​​the channel diode from P+ injection, and inject B element with energy of 80-140kev and dose of 2-4E15 to further increase the ion concentration; S12: BPSG deposition, hole etching: BPSG is deposited to form a dielectric layer, and the dielectric layer and the hole are photolithographically and etched using a mask for the hole. The width of the hole in the trench diode must be greater than the width of the trench diode P-Well. S13: Deposit metal on the front side, thin and deposit metal on the back side: deposit 4um thick aluminum, then photoetch the aluminum to form a source and field plate.

7. The preparation method according to claim 6, characterized in that: In S1, the substrate is doped with arsenic or phosphorus, with a resistivity of 0.001-0.05Ω.cm. The resistivity and thickness of the epitaxy are determined by the withstand voltage of different devices. Usually, the epitaxy thickness is 40-60um, the resistivity is 15-20Ω.cm, and the withstand voltage of the device is 400V-700V.

8. The preparation method according to claim 6, characterized in that: Before step S3, an oxide layer with a thickness of 500 angstroms is grown on the basis of etching the field oxide to alleviate the lattice damage caused by ion implantation.

9. The preparation method according to claim 6, characterized in that: In S10, the injection depth of B ions in SIN is deeper than that in SIO2. By adjusting the thickness of SIN and LOCOS oxide layers, B ions pass through SIN but are blocked by LOCOS oxide layers, ensuring the formation of P-Well of the channel diode. The turn-on voltage of the channel diode is less than 0.7V, so the injection dose and energy of B ions in this step are small, and the heat of pushing the well is low, so S10 has no effect on the P-Well of ordinary VDMOS.

10. The preparation method according to claim 6, characterized in that: In S13, a certain proportion of SiCu can be doped into aluminum to prevent aluminum and silicon from dissolving each other.

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