Complementary field effect transistor device, preparation method thereof and logic circuit

Abstract

The invention relates to a complementary field effect transistor device and a preparation method thereof, a logic circuit, a logic NAND gate and a NOR gate circuit. The complementary field effect transistor device comprises at least two layers of field effect transistors which are stacked in the direction perpendicular to the substrate and are connected with each other. Wherein the active layer is used for connecting each field effect transistor of a first power supply voltage end and is located at the topmost layer, and the surface, used for connecting the first power supply voltage end, of the active layer is located at the surface, deviating from the bottommost layer field effect transistor, of the corresponding field effect transistor; the active layer is used for connecting the field effect transistors of the second power supply voltage end and is located at the bottommost layer, and the surface of the active layer used for connecting the second power supply voltage end is located on the surface of the corresponding field effect transistor deviating from the topmost field effect transistor. The complementary field effect transistor device can improve the area utilization efficiency, and facilitates the improvement of the device density of a logic circuit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a complementary field effect transistor device and a preparation method thereof, a logic circuit, and a logic NAND gate and a NOR gate circuit. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) logic circuits are widely used in electronics, the Internet of Things, communications and other fields, and are relatively important logic circuits in the semiconductor industry. CMOS logic circuits include multiple MOS transistors, which are composed of a source, a drain, a gate and a channel.

[0003] In the related art, when optimizing the process design of logic circuits, it is usually required to reduce the occupied area of ​​MOS transistors to improve the device density of the logic circuits. However, currently no reasonable method has been proposed to effectively reduce the occupied area of ​​MOS transistors. Summary of the invention

[0004] Based on this, it is necessary to provide a complementary field effect transistor device and its preparation method, a logic circuit and a logic NAND gate and a NOR gate circuit to address the deficiencies in the prior art.

[0005] The present application provides a complementary field effect transistor device, comprising: at least two layers of field effect transistors stacked and interconnected in a direction perpendicular to a substrate; wherein:

[0006] The field effect transistors of the active layer used for connecting to the first power supply voltage terminal are located at the topmost layer, and the surface of the active layer used for connecting to the first power supply voltage terminal is located at the surface of the corresponding field effect transistor away from the field effect transistor of the bottommost layer;

[0007] The field effect transistors of the active layer connected to the second power supply voltage terminal are located at the bottom layer, and the surface of the active layer connected to the second power supply voltage terminal is located on the surface of the corresponding field effect transistor away from the field effect transistor of the top layer.

[0008] In some embodiments, the at least two layers of field effect transistors include at least two first-type field effect transistors located at the top layer, and at least two second-type field effect transistors located at the bottom layer; wherein,

[0009] The first-type field effect transistor comprises: a first first-type active layer, a second-type channel layer and a second first-type active layer sequentially stacked in a direction away from the second-type field effect transistor;

[0010] The second first-type active layer has a first inversion doping region; the first inversion doping region connects the second-type channel layer and the first power supply voltage terminal.

[0011] In some embodiments, the complementary field effect transistor device further comprises:

[0012] The first isolation structure is located at least between the second first type active layer of the first type field effect transistor connected to the first power supply voltage terminal and the second first type active layer of the first type field effect transistor not connected to the first power supply voltage terminal.

[0013] In some embodiments, the complementary field effect transistor device further comprises:

[0014] At least one first contact structure is located on a surface of the first inversion doped region facing away from the second type channel layer;

[0015] The wiring layer is connected correspondingly to the first contact structure.

[0016] In some embodiments, the complementary field effect transistor device further includes a first metal pattern; wherein,

[0017] The first contact structure is a silicided region of the first metal pattern;

[0018] The wiring layer is a non-silicided region of the first metal pattern.

[0019] In some embodiments, the at least two layers of field effect transistors include at least two first-type field effect transistors located at the top layer, and at least two second-type field effect transistors located at the bottom layer; wherein,

[0020] The second-type field effect transistor comprises: a first second-type active layer, a first-type channel layer and a second second-type active layer sequentially stacked in a direction away from the first-type field effect transistor;

[0021] The second second-type active layer has a second inversion doping region; the second inversion doping region is connected to the first-type channel layer and the second power supply voltage terminal.

[0022] In some embodiments, the complementary field effect transistor device further includes an insulating layer disposed on one side of the substrate; wherein,

[0023] The second-type field effect transistor at the bottom layer is arranged on the surface of the insulating layer away from the substrate;

[0024] In some embodiments, the complementary field effect transistor device further comprises:

[0025] The second contact structure is disposed in the trench of the insulating layer and penetrates the insulating layer, and is respectively connected to the substrate and the corresponding second inversion doping region.

[0026] In some embodiments, the second contact structure is ring-shaped;

[0027] The second-type field effect transistor further includes: a gate column sequentially penetrating the first second-type active layer, the first-type channel layer and the second second-type active layer; the gate column is insulated from the first second-type active layer, the first-type channel layer and the second second-type active layer;

[0028] The gate pillar is insulated from the second contact structure, and an orthographic projection of the gate pillar on the substrate is located within the orthographic projection range of the inner ring area of ​​the second contact structure on the substrate.

[0029] In some embodiments, the first-type field effect transistor and the second-type field effect transistor located directly above the second-type field effect transistor share the same gate column.

[0030] The present application also provides a method for preparing a complementary field effect transistor device, comprising: forming at least two layers of field effect transistors stacked and interconnected in a direction perpendicular to a substrate; wherein:

[0031] The active layer is used to connect each field effect transistor of the first power supply voltage terminal and is formed at the top layer, and the surface of the active layer used to connect the first power supply voltage terminal is formed on the surface of the corresponding field effect transistor away from the field effect transistor of the bottom layer; the active layer is used to connect each field effect transistor of the second power supply voltage terminal and is formed at the bottom layer, and the surface of the active layer used to connect the second power supply voltage terminal is formed on the surface of the corresponding field effect transistor away from the field effect transistor of the top layer.

[0032] In some embodiments, the at least two layers of field effect transistors include at least two first-type field effect transistors located at the top layer, and at least two second-type field effect transistors located at the bottom layer; wherein forming the first-type field effect transistors includes:

[0033] forming a first first-type active layer, a second-type channel layer, and a second first-type active layer in sequence in a direction away from the substrate;

[0034] A first inversion doping region is formed in the second first-type active layer; the first inversion doping region is used to connect the second-type channel layer and the first power supply voltage terminal.

[0035] In some embodiments, the method for preparing the complementary field effect transistor device further comprises:

[0036] forming a first metal pattern on a surface of the first inversion doped region away from the second type channel layer;

[0037] A silicided region is formed on a portion of the first metal pattern close to the first inversion doped region; the silicided region of the first metal pattern serves as a first contact structure, and a non-silicided region of the first metal pattern serves as a wiring layer.

[0038] In some embodiments, the at least two layers of field effect transistors include at least two first-type field effect transistors located at the top layer, and at least two second-type field effect transistors located at the bottom layer; forming the second-type field effect transistors includes:

[0039] sequentially forming a first second-type active layer, a first-type channel layer, and a second second-type active layer in a direction toward the substrate;

[0040] A second inversion doping region is formed in the second second-type active layer; the second inversion doping region is used to connect the first-type channel layer and the second power supply voltage terminal.

[0041] In some embodiments, the method for preparing the complementary field effect transistor device further comprises:

[0042] An insulating material layer, the second second-type active layer, the first second-type channel layer and the first second-type active layer are sequentially formed on the substrate; wherein the second second-type active layer has the second inversion doping region;

[0043] Forming a first through hole penetrating the second second-type active layer, the first type channel layer and the first second-type active layer, and removing a portion of the insulating material layer to form a first opening exposing the substrate surface; wherein the orthographic projection of the first opening on the substrate surface includes the orthographic projection of the first through hole on the substrate surface;

[0044] filling the second contact material layer in the first opening;

[0045] A portion of the second contact material layer is removed to form a second opening exposing the surface of the substrate, the orthographic projection of the retained second contact material layer on the substrate at least partially overlaps with the orthographic projection of the second inversion doped region on the substrate, and the retained second contact material layer serves as a second contact structure.

[0046] The present application also provides a logic circuit, comprising at least one complementary field effect transistor device as described in any of the aforementioned embodiments.

[0047] The present application also provides a logic NAND gate circuit, comprising: a first first-type field effect transistor, a second first-type field effect transistor, a first second-type field effect transistor, and a second second-type field effect transistor;

[0048] The first second-type field effect transistor and the first first-type field effect transistor are stacked from bottom to top in a direction perpendicular to the substrate by using a shared first gate column, and the first gate column is connected to the first input terminal; the second second-type field effect transistor and the second first-type field effect transistor are stacked from bottom to top in a direction perpendicular to the substrate by using a shared second gate column, and the second gate column is connected to the second input terminal;

[0049] The first first-type field effect transistor and the second first-type field effect transistor each include: a first first-type active layer, a second-type channel layer and a second first-type active layer sequentially stacked in a direction away from the substrate and surrounding the circumference of the corresponding gate column; the first first-type active layer of the first first-type field effect transistor and the second first-type field effect transistor are connected, and the first first-type active layer is also connected to the output through hole; the second-type channel layer of the first first-type field effect transistor and the second first-type field effect transistor are connected; the second first-type active layer of the first first-type field effect transistor and the second first-type field effect transistor are connected, and the second first-type active layer has a first inversion doping region, and the first inversion doping region connects the second-type channel layer with the first power supply voltage terminal;

[0050] The first second-type field effect transistor and the second second-type field effect transistor both include: a second second-type active layer, a first type channel layer and a first second-type active layer stacked in sequence in a direction away from the substrate and surrounding the circumference of the corresponding gate column; the first second-type active layer of the first second-type field effect transistor and the second second-type field effect transistor are connected; the first type channel layer of the first second-type field effect transistor and the second second-type field effect transistor are connected; the second second-type active layer of the first second-type field effect transistor has a second inversion doping region, and the second inversion doping region connects the first type channel layer and the second power supply voltage terminal; the second second-type active layer of the second second-type field effect transistor is connected to the output through hole.

[0051] The present application also provides a logic NOR gate circuit, comprising: a first first-type field effect transistor, a second first-type field effect transistor, a first second-type field effect transistor, and a second second-type field effect transistor;

[0052] The first second-type field effect transistor and the first first-type field effect transistor are stacked from bottom to top in a direction perpendicular to the substrate by using a shared first gate column, and the first gate column is connected to the first input terminal; the second second-type field effect transistor and the second first-type field effect transistor are stacked from bottom to top in a direction perpendicular to the substrate by using a shared second gate column, and the second gate column is connected to the second input terminal;

[0053] The first first-type field effect transistor and the second first-type field effect transistor each include: a first first-type active layer, a second-type channel layer and a second first-type active layer sequentially stacked in a direction away from the substrate and surrounding the circumference of the corresponding gate column; the first first-type active layer of the first first-type field effect transistor and the second first-type field effect transistor are connected; the second-type channel layer of the first first-type field effect transistor and the second first-type field effect transistor are connected; the second first-type active layer of the first first-type field effect transistor has a first inversion doping region, and the first inversion doping region connects the second-type channel layer and the first power supply voltage terminal; the second first-type active layer of the second first-type field effect transistor is connected to the output through hole;

[0054] The first second-type field effect transistor and the second second-type field effect transistor both include: a second second-type active layer, a first type channel layer and a first second-type active layer stacked in sequence along a direction away from the substrate and surrounding the circumference of the corresponding gate column; the first second-type active layer of the first second-type field effect transistor and the second second-type field effect transistor is connected, and the first second-type active layer is also connected to the output through hole; the first second-type channel layer of the first second-type field effect transistor and the second second-type field effect transistor is connected; the second second-type active layer of the first second-type field effect transistor and the second second-type field effect transistor is connected, and the second second-type active layer has a second inversion doping region, and the second inversion doping region connects the first type channel layer with the second power supply voltage terminal.

[0055] The complementary field effect transistor device, logic circuit, and logic NAND gate and NOR gate circuit provided by the present application have at least the following beneficial effects:

[0056] In the complementary field effect transistor device and its preparation method provided by the present application, the field effect transistors whose active layer is used to connect to the first power supply voltage terminal are all arranged at the top layer of the device, and the field effect transistors whose active layer is used to connect to the second power supply voltage terminal are all arranged at the bottom layer of the device. Therefore, compared with the traditional complementary field effect transistor device in the related art that requires more through holes to connect the active layer and the channel layer to the first power supply voltage terminal or the second power supply voltage terminal, the complementary field effect transistor device provided by the present application does not need to occupy additional space in order to connect the first power supply voltage terminal and the second power supply voltage terminal, which reduces the occupied area of ​​the complementary field effect transistor device, effectively improves the area utilization efficiency, and is conducive to improving the device density of the logic circuit. In addition, the preparation method of the complementary field effect transistor device structure as above is also relatively simple and easy to implement.

[0057] The logic circuit provided in the present application includes the complementary field effect transistor devices described in the aforementioned embodiments. Therefore, the technical effects that can be achieved by the complementary field effect transistor devices described in the aforementioned embodiments can also be achieved by the logic circuit provided in the present application, and will not be repeated here.

[0058] In the logic NAND gate circuit provided by the present application, the field effect transistor of the active layer used to connect the first power supply voltage terminal is arranged at the topmost layer of the device (the active layer in this case refers to the second first type active layer), and the field effect transistor of the active layer used to connect the second power supply voltage terminal is arranged at the bottommost layer of the device (the active layer in this case refers to the second second type active layer). Therefore, compared with the traditional logic NAND gate circuit in the related art that requires more through holes to connect the active layer and the channel layer to the first power supply voltage terminal or the second power supply voltage terminal, the logic NAND gate circuit provided by the present application does not need to occupy additional space in order to connect the first power supply voltage terminal and the second power supply voltage terminal, which reduces the occupied area of ​​the logic NAND gate circuit, effectively improves the area utilization efficiency, and is conducive to improving the device density of the logic NAND gate circuit. In addition, the preparation method of the above logic NAND gate circuit is also relatively simple and easy to implement.

[0059] In the logic or gate circuit provided by the present application, the field effect transistor of the active layer used to connect the first power supply voltage terminal is arranged at the topmost layer of the device (the active layer in this case refers to the second first type active layer), and the field effect transistor of the active layer used to connect the second power supply voltage terminal is arranged at the bottommost layer of the device (the active layer in this case refers to the second second type active layer). Therefore, compared with the traditional logic or gate circuit in the related art that requires more through holes to connect the active layer and the channel layer to the first power supply voltage terminal or the second power supply voltage terminal, the logic or gate circuit provided by the present application does not need to occupy additional space in order to connect the first power supply voltage terminal and the second power supply voltage terminal, thereby reducing the occupied area of ​​the logic or gate circuit, effectively improving the area utilization efficiency, and thus facilitating the improvement of the device density of the logic or gate circuit. In addition, the preparation method of the above logic or gate circuit is also relatively simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0061] Figure 1 A schematic diagram of a three-dimensional structure of a logic circuit provided in some embodiments of the present application; Figure 1 It is also a three-dimensional structural schematic diagram of a logic NOR gate circuit provided in some embodiments of the present application;

[0062] Figure 2 A schematic diagram of a three-dimensional structure of a logic circuit provided in some other embodiments of the present application; Figure 2 It is also a three-dimensional structural schematic diagram of a logic NAND gate circuit provided in some embodiments of the present application;

[0063] Figure 3 A schematic diagram of a cross-sectional structure of a first type of field effect transistor in a complementary field effect transistor device provided in some embodiments of the present application; Figure 3 It is also a schematic diagram of the cross-sectional structure of a field effect transistor provided in some embodiments of the present application;

[0064] Figure 4 A schematic diagram of a cross-sectional structure of a first type of field effect transistor in a complementary field effect transistor device provided in some other embodiments of the present application;

[0065] Figure 5 A schematic cross-sectional view of a structure obtained after forming an insulating material layer, a second first-type active layer, a second-type channel layer and a first first-type active layer on a substrate in the process of preparing a complementary field effect transistor device provided in some embodiments of the present application; Figure 5 It is also a schematic diagram of the cross-sectional structure of a field effect transistor provided in some other embodiments of the present application;

[0066] Figure 6 A schematic diagram of a cross-sectional structure of a structure obtained after forming a first through hole and a first opening in a process of preparing a complementary field effect transistor device provided in some embodiments of the present application;

[0067] Figure 7 A schematic diagram of a cross-sectional structure of a structure obtained after filling a second contact material layer in a process of preparing a complementary field effect transistor device provided in some embodiments of the present application;

[0068] Figure 8 A schematic cross-sectional view of a structure obtained after forming a second contact structure in a process of preparing a complementary field effect transistor device provided in some embodiments of the present application.

[0069] Description of reference numerals:

[0070] 1. first type field effect transistor; 2. second type field effect transistor; 11. first first type active layer; 11A. first extension; 12. second type channel layer; 13. second first type active layer; 13A. third extension; 131. first inversion doping region; 14. first metal pattern; 15. covering dielectric layer; 21. first second type active layer; 21A. fourth extension; 22. first type channel layer; 23. second second type active layer; 23A. second extension; 231. second inversion doping region; 24. Second contact structure; 24', second contact material layer; 251, first gate column; 252, second gate column; 26, filling dielectric layer; 3, substrate; 4, insulating layer; 4', insulating material layer; 5, gate dielectric layer; 6, output through hole; P1, first first-type field effect transistor; P2, second first-type field effect transistor; N1, first second-type field effect transistor; N2, second second-type field effect transistor; I1, first input terminal; I2, second input terminal; O, output terminal; T1, first through hole; T2, first opening. DETAILED DESCRIPTION

[0071] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0073] It should be understood that when an element or layer is referred to as being "located above" or "connected to," it may be directly located on or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first power supply voltage terminal may be referred to as the second power supply voltage terminal, and similarly, the second power supply voltage terminal may be referred to as the first power supply voltage terminal; the first power supply voltage terminal and the second power supply voltage terminal are different power supply voltage terminals, for example, the first power supply voltage terminal may be a ground terminal and the second power supply voltage terminal may be a power supply terminal, or the first power supply voltage terminal may be a power supply terminal and the second power supply voltage terminal may be a ground terminal.

[0074] Spatial relationship terms such as "located above..." may be used here to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "located above..." will be oriented "below" other elements or features. Therefore, the exemplary term "located above..." can include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0075] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0076] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques, and the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0077] In the related art, when optimizing the process design of logic circuits, it is usually required to reduce the occupied area of ​​MOS transistors to improve the device density of the logic circuits. However, currently no reasonable method has been proposed to effectively reduce the occupied area of ​​MOS transistors.

[0078] In view of the above-mentioned deficiencies in the prior art, the present application provides a complementary field effect transistor device and a logic circuit. It can be understood that the complementary field effect transistor device provided in the present application can be used to construct the logic circuit provided in the present application, and by making different electrical connections and combinations of the complementary field effect transistor devices, the logic circuit for realizing different logic functions can be constructed.

[0079] For example Figure 1 As shown, a logic NOR gate circuit is constructed by connecting and combining the complementary field effect transistor devices; for example Figure 2 As shown, a logic NAND gate circuit is constructed by connecting and combining the complementary field effect transistor devices, and the details will be explained in subsequent embodiments.

[0080] It should be noted that the above connection method is only an example. In actual embodiments, logic circuits such as NOT gates and multiplexers can be constructed by making different electrical connections and combinations of the complementary field effect transistor devices, and are not limited to the above connection method.

[0081] According to some embodiments, the present application provides a complementary field effect transistor device.

[0082] In some embodiments, the complementary field effect transistor device comprises: at least two layers of field effect transistors stacked and interconnected in a direction perpendicular to the substrate. It can be understood that each field effect transistor comprises an active layer.

[0083] The active layer is used to connect the field effect transistors of the first power supply voltage terminal at the top layer, and the surface of the active layer used to connect the first power supply voltage terminal is located on the surface of the corresponding field effect transistor away from the field effect transistor at the bottom layer. The active layer is used to connect the field effect transistors of the second power supply voltage terminal at the bottom layer, and the surface of the active layer used to connect the second power supply voltage terminal is located on the surface of the corresponding field effect transistor away from the field effect transistor at the top layer.

[0084] In the complementary field effect transistor device provided in the above embodiment, the field effect transistors whose active layer is used to connect to the first power supply voltage terminal are all arranged at the top layer of the device, and the field effect transistors whose active layer is used to connect to the second power supply voltage terminal are all arranged at the bottom layer of the device. Therefore, compared with the traditional complementary field effect transistor device in the related art that requires more through holes to connect the active layer and the channel layer to the first power supply voltage terminal or the second power supply voltage terminal, the complementary field effect transistor device provided in the present application does not need to occupy additional space in order to connect the first power supply voltage terminal and the second power supply voltage terminal, thereby reducing the occupied area of ​​the complementary field effect transistor device, effectively improving the area utilization efficiency, and thus facilitating the improvement of the device density of the logic circuit. In addition, the preparation method of the complementary field effect transistor device structure as above is also relatively simple and easy to implement.

[0085] The embodiment of the present application does not specifically limit the voltage magnitudes of the first power supply voltage terminal and the second power supply voltage terminal. As an example, the first power supply voltage terminal may be the power supply voltage terminal VDD of the complementary field effect transistor device; in this case, the second power supply voltage terminal may be the ground terminal GND of the complementary field effect transistor device.

[0086] The following embodiments take the field effect transistor used in the active layer to connect the first power supply voltage terminal as a first type field effect transistor, and the field effect transistor used in the active layer to connect the second power supply voltage terminal as a second type field effect transistor as an example, and combine Figures 1 to 8 That is to say, in the following embodiments, the at least two layers of field effect transistors may include at least two first-type field effect transistors 1 located at the top layer, and at least two second-type field effect transistors 2 located at the bottom layer.

[0087] It can be understood that the embodiments of the present application do not specifically limit the types of the first type field effect transistor 1 and the second type field effect transistor 2. In some embodiments, the first type field effect transistor 1 is a P-type MOS transistor, and the second type field effect transistor 2 is an N-type MOS transistor; in other embodiments, the first type field effect transistor 1 can be an N-type MOS transistor, and the second type field effect transistor 2 can be a P-type MOS transistor, which is also allowed.

[0088] like Figure 1 and Figure 2 As shown, the first type field effect transistor 1 for connecting the first power supply voltage terminal is located at the top layer of the multilayer field effect transistor, and the surface of the active layer for connecting the first power supply voltage terminal is located on the surface of the first type field effect transistor 1 away from the bottom layer field effect transistor.

[0089] Please continue reading Figure 1 and Figure 2In some embodiments, the first-type field effect transistor 1 may include: a first first-type active layer 11, a second-type channel layer 12, and a second first-type active layer 13 sequentially stacked in a direction away from the second-type field effect transistor 2. The second first-type active layer 13 has a first inversion doping region 131, and the first inversion doping region 131 connects the second-type channel layer 12 with the first power supply voltage terminal.

[0090] It can be understood that in some embodiments, a plurality of first-type field effect transistors 1 are disposed in the same layer at the topmost layer of the multilayer field effect transistor. As an example, the first inversion doping region 131 is also used to isolate the second first-type active layer 13 corresponding to the adjacent first-type field effect transistor 1. In this way, by isolating the second first-type active layer 13 corresponding to the adjacent first-type field effect transistor 1 by providing the first inversion doping region 131, the lateral coupling between the two second first-type active layers 13 corresponding to the adjacent first-type field effect transistor 1 can be effectively reduced, thereby avoiding the adverse effects between the adjacent first-type field effect transistors 1.

[0091] As an example, see Figure 3 In the process of preparing the first type field effect transistor 1, the following steps may be used to form the first inversion doping region 131 in the second first type active layer 13, for example:

[0092] Inverse doping ions are implanted into the first preset region in the second first-type active layer 13, so that the first preset region is inverted from the first type to the second type (for example, from the P type to the N type), forming a first inverse doping region 131, thereby connecting the second-type channel layer 12 with the first power supply voltage terminal. It can be understood that the first preset region should be adaptively set according to the region of the second-type channel layer 12 that needs to be connected to the first power supply voltage terminal.

[0093] In some embodiments, the complementary field effect transistor device may further include a first isolation structure.

[0094] The first isolation structure may be located at least between the second first type active layer 13 of the first type field effect transistor 1 connected to the first power supply voltage terminal and the second first type active layer 13 of the first type field effect transistor 1 not connected to the first power supply voltage terminal.

[0095] See also Figure 4 In some embodiments, the complementary field effect transistor device may further include at least one first contact structure and a wiring layer.

[0096] The first contact structure is at least located on a surface of the corresponding first inversion doping region 131 away from the second channel layer 12. The wiring layer is connected to the first contact structure accordingly.

[0097] In the complementary field effect transistor device provided in the above embodiment, various pins used for power supply, for example, can be connected together through metal wires in the wiring layer to form a power supply network.

[0098] The embodiment of the present application does not specifically limit the forms of the first contact structure and the wiring layer.

[0099] In some embodiments, the complementary field effect transistor device may include a first metal pattern 14 including a silicided region and a non-silicided region.

[0100] The silicided region of the first metal pattern 14 may be used as a first contact structure; correspondingly, the non-silicided region of the first metal pattern 14 may be used as a wiring layer.

[0101] The present embodiment of the application does not specifically limit the constituent material of the first metal pattern 14. As an example, the constituent material of the first metal pattern 14 may include, but is not limited to, metal materials such as titanium (Ti), cobalt (Co), and nickel (Ni).

[0102] As an example, the silicided region of the first metal pattern may be prepared by, but is not limited to, a method of high-temperature heating to cause a metal material to react with silicon.

[0103] Please continue reading Figure 4 In some embodiments, the complementary field effect transistor device may further include a covering dielectric layer 15 .

[0104] As an example, the covering dielectric layer 15 may cover the surface of the second first-type active layer 13 not covered by the first metal pattern. In addition, the covering dielectric layer 15 may also cover the surface of the second first-type active layer 13 where, for example, a through hole is formed in a subsequent process.

[0105] like Figure 1 and Figure 2 As shown, the second type field effect transistor 2 for connecting the second power supply voltage terminal is located at the bottom layer of the multilayer field effect transistor, and the surface of the active layer for connecting the second power supply voltage terminal is located on the surface of the second type field effect transistor 2 away from the top layer field effect transistor.

[0106] Please continue reading Figure 1 and Figure 2 In some embodiments, the second-type field effect transistor 2 may include: a first second-type active layer 21, a first-type channel layer 22, and a second second-type active layer 23 sequentially stacked in a direction away from the first-type field effect transistor 1. The second second-type active layer 23 has a second inversion doping region 231, and the second inversion doping region 231 connects the first-type channel layer 22 and the second power supply voltage terminal.

[0107] It can be understood that in some embodiments, a plurality of second-type field effect transistors 2 are disposed in the same layer at the bottom layer of the multilayer field effect transistor. As an example, the second inverted doping region 231 is also used to isolate the second second-type active layer 23 corresponding to the adjacent second-type field effect transistor 2. In this way, by isolating the second second-type active layer 23 corresponding to the adjacent second-type field effect transistor 2 by arranging the second inverted doping region 231, the lateral coupling between the two second second-type active layers 23 corresponding to the adjacent second-type field effect transistor 2 can be effectively reduced, thereby avoiding the adverse effects between the adjacent second-type field effect transistors 2.

[0108] As an example, Figure 5 As shown, in the process of preparing the second-type field effect transistor 2, the second inversion doping region 231 can be formed in the second-type active layer 23 by the following steps, for example:

[0109] The second preset region in the second second-type active layer 23 is subjected to inversion ion implantation to invert the second preset region from the second type to the first type (for example, from the N type to the P type), forming a second inversion doping region 231, thereby connecting with the first-type channel layer 22. It can be understood that the second preset region should be adaptively set according to the region of the first-type channel layer 22 that needs to be connected to the second power supply voltage terminal.

[0110] See also Figures 5 to 8 In some embodiments, the complementary field effect transistor device may further include a substrate 3 and an insulating layer 4 disposed on one side of the substrate 3 .

[0111] like Figure 8 As shown, the bottom-most second-type field effect transistor 2 may be disposed on the surface of the insulating layer 4 facing away from the substrate 3 .

[0112] Please continue reading Figure 8 In some embodiments, the complementary field effect transistor device may further include a second contact structure 24 .

[0113] The second contact structure 24 may be disposed in the trench of the insulating layer 4 and penetrate the insulating layer 4 , and be connected to the substrate 3 and the corresponding second inversion doped region 231 , respectively.

[0114] The present embodiment of the application does not specifically limit the constituent material of the second contact structure 24. As an example, the constituent material of the second contact structure 24 may include, but is not limited to, a metal silicide material.

[0115] The embodiment of the present application does not specifically limit the form of the second contact structure 24. As an example, Figure 8 As shown, the second contact structure 24 may be ring-shaped.

[0116] Please continue reading Figure 1 to Figure 2In some embodiments, the second-type field effect transistor 2 may further include: a gate column sequentially penetrating the first second-type active layer 21, the first-type channel layer 22, and the second second-type active layer 23, and the gate column is insulated from the first second-type active layer 21, the first-type channel layer 22, and the second second-type active layer 23. The gate column may be specifically represented as Figure 1 and Figure 2 The first gate pillar 251 and the second gate pillar 252 are shown in FIG.

[0117] Specifically, the gate pillar is insulated from the second contact structure 24 , and the orthographic projection of the gate pillar on the substrate 3 is located within the orthographic projection range of the inner ring region of the second contact structure 24 on the substrate 3 .

[0118] Please continue reading Figure 1 to Figure 2 In some embodiments, the second-type field effect transistor 2 can share the same gate column with the first-type field effect transistor 1 located directly above it.

[0119] The gate column also sequentially penetrates the first first-type active layer 11 , the second type channel layer 12 and the second first-type active layer 13 , and is insulated from the first first-type active layer 11 , the second type channel layer 12 and the second first-type active layer 13 .

[0120] Please continue reading Figure 1 to Figure 2 The complementary field effect transistor device may further include a gate dielectric layer 5.

[0121] For the second-type field effect transistor 2, the gate dielectric layer 5 may be located between the first second-type active layer 21, the first-type channel layer 22, the second second-type active layer 23 and the gate pillar. For the first-type field effect transistor 1, the gate dielectric layer 5 may be located between the first first-type active layer 11, the second-type channel layer 12, the second first-type active layer 13 and the gate pillar.

[0122] The embodiment of the present application does not specifically limit the method for forming the first through hole T1. As an example, the first through hole T1 can be formed in the second second-type active layer 23, the first-type channel layer 22 and the first second-type active layer 21 by, but not limited to, dry etching.

[0123] The embodiment of the present application does not specifically limit the method for forming the first opening T2. As an example, the first opening T2 exposing the surface of the substrate 3 may be formed by, but is not limited to, a wet etching process.

[0124] Furthermore, in some embodiments, the first through hole T1 and the first opening T2 can be prepared by a one-step process, which is helpful to simplify the process flow, thereby improving the production efficiency of complementary field effect transistor devices.

[0125] In some embodiments, the constituent material of the second contact material layer 24 ′ may include a metal material.

[0126] After removing part of the second contact material layer 24' to form a second opening exposing the surface of the substrate 3 and retaining the annular second contact material layer 24', the following steps may also be included: high-temperature heating to allow the metal material to react with silicon to form a metal silicide material; the retained metal silicide material serves as the second contact structure 24.

[0127] In some embodiments, the gate column of the second-type field effect transistor 2 may be formed in the first through hole T1 .

[0128] Please continue reading Figure 8 In some embodiments, the complementary field effect transistor device may further include a filling dielectric layer 26 filled in the second opening.

[0129] The present application also provides a field effect transistor according to some embodiments.

[0130] Please continue reading Figure 3 The field effect transistor may include the first type field effect transistor 1 as described in any of the aforementioned embodiments.

[0131] The present application also provides another field effect transistor according to some embodiments.

[0132] Please continue reading Figure 5 The field effect transistor may include the second type field effect transistor 2 as described in any of the aforementioned embodiments.

[0133] According to some embodiments, the present application also provides a method for preparing a complementary field effect transistor device.

[0134] In some embodiments, the method for preparing the complementary field effect transistor device may specifically include: forming at least two layers of field effect transistors that are stacked and interconnected in a direction perpendicular to the substrate.

[0135] Among them, the active layer is used to connect the field effect transistors of the first power supply voltage terminal and is formed on the top layer, and the surface of the active layer used to connect to the first power supply voltage terminal is formed on the surface of the corresponding field effect transistor away from the bottom layer field effect transistor; the active layer is used to connect the field effect transistors of the second power supply voltage terminal and is formed on the bottom layer, and the surface of the active layer used to connect to the second power supply voltage terminal is formed on the surface of the corresponding field effect transistor away from the top layer field effect transistor.

[0136] In the preparation method of the complementary field effect transistor device provided in the above embodiment, the field effect transistors of the active layer used to connect the first power supply voltage terminal are all formed at the top layer of the device, and the field effect transistors of the active layer used to connect the second power supply voltage terminal are all formed at the bottom layer of the device. Therefore, compared with the traditional complementary field effect transistor device in the related art that requires more through holes to connect the active layer and the channel layer to the first power supply voltage terminal or the second power supply voltage terminal, the complementary field effect transistor device prepared by the preparation method provided in the present application does not need to occupy additional space in order to connect the first power supply voltage terminal and the second power supply voltage terminal, which reduces the occupied area of ​​the complementary field effect transistor device, effectively improves the area utilization efficiency, and is conducive to improving the device density of the logic circuit. In addition, the preparation method of the complementary field effect transistor device structure as above is also relatively simple and easy to implement.

[0137] Please combine Figures 1 to 8 It is understood that, in some embodiments, the at least two layers of field effect transistors may include at least two first-type field effect transistors 1 located at the top layer, and at least two second-type field effect transistors 2 located at the bottom layer.

[0138] Please continue reading Figures 1 to 4 In some embodiments, the first type field effect transistor 1 may be formed by the following steps, for example:

[0139] A first first-type active layer 11 , a second-type channel layer 12 , and a second first-type active layer 13 are sequentially formed in a direction away from the substrate 3 .

[0140] A first inversion doping region 131 is formed in the second first-type active layer 13 ; the first inversion doping region 131 is used to connect the second-type channel layer 12 and the first power supply voltage terminal.

[0141] Please continue reading Figure 4 In some embodiments, the method for preparing the complementary field effect transistor device may further include the following steps:

[0142] like Figure 4 As shown, a first metal pattern 14 is formed on the surface of the second type channel layer 12 corresponding to the first inversion doping region 131; a silicided region is formed on the portion of the first metal pattern 14 close to the first inversion doping region 131; the silicided region of the first metal pattern 14 serves as a first contact structure, and the non-silicided region of the first metal pattern 14 serves as a wiring layer.

[0143] Please continue reading Figure 1 , Figure 2 as well as Figures 5 to 8 In some embodiments, the second type field effect transistor 2 may be formed by the following steps, for example:

[0144] like Figure 5As shown, a first second-type active layer 21, a first-type channel layer 22 and a second second-type active layer 23 are sequentially formed along the direction toward the substrate 3; a second inversion doping region 231 is formed in the second second-type active layer 23; the second inversion doping region 231 is used to connect the first-type channel layer 22 with the second power supply voltage terminal.

[0145] Please continue reading Figures 5 to 8 In some embodiments, the method for preparing the complementary field effect transistor device may further include the following steps:

[0146] like Figure 5 As shown, an insulating material layer 4 ′, a second second-type active layer 23 , a first type channel layer 22 and a first second-type active layer 21 are sequentially formed on a substrate 3 ; wherein the second second-type active layer 23 has a second inversion doping region 231 .

[0147] like Figure 6 As shown, a first through hole T1 is formed penetrating the second second-type active layer 23, the first type channel layer 22 and the first second-type active layer 21, and a portion of the insulating material layer 4' is removed to form a first opening T2 exposing the surface of the substrate 3; wherein the orthographic projection of the first opening T2 on the surface of the substrate 3 includes the orthographic projection of the first through hole T1 on the surface of the substrate 3.

[0148] like Figure 7 As shown, the second contact material layer 24 ′ is filled in the first opening T2 .

[0149] like Figure 8 As shown, part of the second contact material layer 24 ′ is removed to form a second opening exposing the surface of the substrate 3 , the orthographic projection of the retained second contact material layer 24 ′ on the substrate 3 at least partially overlaps with the orthographic projection of the second inversion doped region 231 on the substrate 3 , and the retained second contact material layer 24 ′ serves as the second contact structure 24 .

[0150] According to some embodiments, the present application also provides a logic circuit, comprising at least one complementary field effect transistor device as described in any of the aforementioned embodiments.

[0151] The logic circuit provided in the embodiment of the present application includes the complementary field effect transistor devices described in the aforementioned embodiments. Therefore, the technical effects that can be achieved by the complementary field effect transistor devices described in the aforementioned embodiments can also be achieved by the logic circuit provided in the present application, and will not be repeated here.

[0152] The present application also provides a logic NOR gate circuit according to some embodiments.

[0153] Please combine Figure 1It is understood that in some embodiments, the logic NOR gate circuit may include: a first first-type active layer 11, a second type channel layer 12 and a second first-type active layer 13 located at the top layer and stacked sequentially from bottom to top; and a second second-type active layer 23, a first type channel layer 22 and a first second-type active layer 21 located at the bottom layer and stacked sequentially from bottom to top.

[0154] The second first-type active layer 13 has a first inversion doping region 131 . The first inversion doping region 131 is connected to the second-type channel layer 12 and is used to connect to the first power supply voltage terminal.

[0155] The second second-type active layer 23 has a second inversion doping region 231 ; the second inversion doping region 231 is connected to the first-type channel layer 22 and is used to connect to the second power supply voltage terminal.

[0156] In the above embodiment, the logic NOR gate circuit may further include: a first gate column 251 and a second gate column 252 .

[0157] The first gate pillar 251 and the second gate pillar 252 both penetrate the first first-type active layer 11, the second-type channel layer 12 and the second first-type active layer 13, the second second-type active layer 23, the first-type channel layer 22 and the first second-type active layer 21. It should be noted that the second first-type active layer 13 corresponding to the first gate pillar 251 is insulated from the second first-type active layer 13 corresponding to the second gate pillar 252.

[0158] In the above embodiment, the logic NOR gate circuit may further include: a first input terminal I1, a second input terminal I2 and an output terminal O.

[0159] The first input terminal I1 is electrically connected to the first gate column 251 ; the second input terminal I2 is electrically connected to the second gate column 252 ; and the output terminal O is electrically connected to the second first-type active layer 13 and the first second-type active layer 21 .

[0160] In some embodiments, the second first type active layer 13 corresponding to the first gate column 251 is used to connect the first power supply voltage terminal, the second first type active layer 13 corresponding to the second gate column 252 has a third extension portion 13A, and the first second type active layer 21 has a fourth extension portion 21A.

[0161] Please continue reading Figure 1 In some embodiments, the logic NOR gate circuit may further include: an output through hole 6. The output through hole 6 passes through the third extension portion 13A and the fourth extension portion 21A, and is electrically connected to the third extension portion 13A, the fourth extension portion 21A and the output end O.

[0162] It should be noted that, in the embodiment of the present application, the output through hole 6 includes a through hole and a conductive material filled in the through hole.

[0163] As an example, Figure 1 As shown, the logic NOR gate circuit may include at least two layers of field effect transistors stacked in a direction perpendicular to the substrate. The at least two layers of field effect transistors may include at least two first-type field effect transistors 1 located at the top layer, and at least two second-type field effect transistors 2 located at the bottom layer.

[0164] In the following, at least two first-type field effect transistors 1 located at the top layer are P-type MOS transistors. Figure 1 The first first-type field effect transistor P1 and the second first-type field effect transistor P2 are shown; and at least two second-type field effect transistors 2 located at the bottom are N-type MOS transistors, such as Figure 1 Taking the first second-type field effect transistor N1 and the second second-type field effect transistor N2 as examples, some possible embodiments of the present application are described.

[0165] See also Figure 1 The first second-type field effect transistor N1 and the first first-type field effect transistor P1 can be stacked from bottom to top in a direction perpendicular to the substrate by sharing a first gate column 251; the first gate column 251 is connected to the first input terminal I1. The second second-type field effect transistor N2 and the second first-type field effect transistor P2 can also be stacked from bottom to top in a direction perpendicular to the substrate by sharing a second gate column 252; the second gate column 252 is connected to the second input terminal I2.

[0166] Among them, the first first-type field effect transistor P1 is connected in series with the second first-type field effect transistor P2, the first second-type field effect transistor N1 is connected in parallel with the second second-type field effect transistor N2 and is respectively connected in series with the first first-type field effect transistor P1 and the second first-type field effect transistor P2 to form a logic NOR gate circuit.

[0167] It can be understood that the first first-type field effect transistor P1 and the second first-type field effect transistor P2 both include a first first-type active layer 11, a second-type channel layer 12, and a second first-type active layer 13 that are sequentially stacked along a direction away from the substrate and surround the circumference of the corresponding gate column. The first second-type field effect transistor N1 and the second second-type field effect transistor N2 both include a second second-type active layer 23, a first-type channel layer 22, and a first second-type active layer 21 that are sequentially stacked along a direction away from the substrate and surround the circumference of the corresponding gate column.

[0168] As an example, the electrical connection relationship between the first first-type field effect transistor P1, the second first-type field effect transistor P2, the first second-type field effect transistor N1 and the second second-type field effect transistor N2 can be implemented in the following manner but is not limited to:

[0169] The first first-type active layer 11 of the first first-type field effect transistor P1 and the second first-type field effect transistor P2 are connected. The second first-type channel layer 12 of the first first-type field effect transistor P1 and the second first-type field effect transistor P2 are connected. The second first-type active layer 13 of the first first-type field effect transistor P1 and the second first-type field effect transistor P2 are spaced from each other; wherein, the second first-type active layer 13 of the first first-type field effect transistor P1 has a first inversion doping region 131, and the first inversion doping region 131 connects the second-type channel layer 12 and the first power supply voltage terminal; the second first-type active layer 13 of the second first-type field effect transistor P2 is connected to the output through hole 6.

[0170] The first second-type active layer 21 of the first second-type field effect transistor N1 and the second second-type field effect transistor N2 are connected, and the first second-type active layer 21 is also connected to the output through hole 6; the first second-type field effect transistor N1 and the second second-type field effect transistor N2 have a first type channel layer 22 connected; the first second-type field effect transistor N1 and the second second-type field effect transistor N2 have a second second-type active layer 23 connected, and the second second-type active layer 23 has a second inversion doping region 231, and the second inversion doping region 231 connects the first type channel layer 22 and the second power supply voltage terminal.

[0171] In some embodiments, the first first-type active layer 11 of the first first-type field effect transistor P1 and the second first-type field effect transistor P2 can be disposed in the same layer. In some embodiments, the second-type channel layer 12 of the first first-type field effect transistor P1 and the second first-type field effect transistor P2 can also be disposed in the same layer.

[0172] In some embodiments, the first second type active layer 21 of the first second type field effect transistor N1 and the second second type field effect transistor N2 can be disposed in the same layer. In some embodiments, the first type channel layer 22 of the first second type field effect transistor N1 and the second second type field effect transistor N2 can also be disposed in the same layer. In some embodiments, the second second type active layer 23 of the first second type field effect transistor N1 and the second second type field effect transistor N2 can also be disposed in the same layer.

[0173] The present application also provides a logic NAND gate circuit according to some embodiments.

[0174] Please combine Figure 2 It is understood that in some embodiments, the logic NAND gate circuit may include: a first first-type active layer 11, a second type channel layer 12, and a second first-type active layer 13 located at the top layer and stacked sequentially from bottom to top; and a second second-type active layer 23, a first type channel layer 22, and a first second-type active layer 21 located at the bottom layer and stacked sequentially from bottom to top.

[0175] The second first-type active layer 13 has a first inversion doping region 131 . The first inversion doping region 131 is connected to the second-type channel layer 12 and is used to connect to the first power supply voltage terminal.

[0176] The second second-type active layer 23 has a second inversion doping region 231 ; the second inversion doping region 231 is connected to the first-type channel layer 22 and is used to connect to the second power supply voltage terminal.

[0177] In the above embodiment, the logic NAND gate circuit may further include: a first gate column 251 and a second gate column 252 .

[0178] The first gate pillar 251 and the second gate pillar 252 both penetrate the first first-type active layer 11, the second type channel layer 12 and the second first-type active layer 13, the second second-type active layer 23, the first type channel layer 22 and the first second-type active layer 21, and the second second-type active layer 23 corresponding to the first gate pillar 251 is insulated from the second second-type active layer 23 corresponding to the second gate pillar 252.

[0179] In the above embodiment, the logic NAND gate circuit may further include: a first input terminal I1, a second input terminal I2 and an output terminal O.

[0180] The first input terminal I1 is electrically connected to the first gate column 25 ; the second input terminal I2 is electrically connected to the second gate column 25 ; the output terminal O is electrically connected to the first first-type active layer 11 and the second second-type active layer 23 .

[0181] In some embodiments, the first first-type active layer 11 has a first extension portion 11A, the second second-type active layer 23 corresponding to the first gate column 251 is used to connect the second power supply voltage terminal, and the second second-type active layer 23 corresponding to the second gate column 252 has a second extension portion 23A.

[0182] Please continue reading Figure 2 In some embodiments, the logic NAND gate circuit may further include: an output through hole 6, which passes through the first extension portion 11A and the second extension portion 23A, and is electrically connected to the first extension portion 11A, the second extension portion 23A and the output end O.

[0183] As an example, Figure 2 As shown, the logic NAND gate circuit may also include at least two layers of field effect transistors stacked in a direction perpendicular to the substrate. The at least two layers of field effect transistors may include at least two first-type field effect transistors 1 located at the top layer, and at least two second-type field effect transistors 2 located at the bottom layer.

[0184] In the following, at least two first-type field effect transistors 1 located at the top layer are P-type MOS transistors. Figure 2The first first-type field effect transistor P1 and the second first-type field effect transistor P2 are shown; and at least two second-type field effect transistors 2 located at the bottom are N-type MOS transistors, such as Figure 2 Taking the first second-type field effect transistor N1 and the second second-type field effect transistor N2 as examples, some possible embodiments of the present application are described.

[0185] See also Figure 1 The first second-type field effect transistor N1 and the first first-type field effect transistor P1 are stacked from bottom to top in a direction perpendicular to the substrate by sharing a first gate column 251; as an example, the first gate column 251 can be connected to the first input terminal I1. The second second-type field effect transistor N2 and the second first-type field effect transistor P2 are stacked from bottom to top in a direction perpendicular to the substrate by sharing a second gate column 252; as an example, the second gate column 252 can be connected to the second input terminal I2.

[0186] Among them, the first second-type field effect transistor N1 is connected in series with the second second-type field effect transistor N2; the first first-type field effect transistor P1 is connected in parallel with the second first-type field effect transistor P2 and is respectively connected in series with the first second-type field effect transistor N1 and the second second-type field effect transistor N2 to form a logic NAND gate circuit.

[0187] It can be understood that the first first-type field effect transistor P1 and the second first-type field effect transistor P2 both include a first first-type active layer 11, a second-type channel layer 12, and a second first-type active layer 13 that are sequentially stacked in a direction away from the substrate and surround the corresponding gate column. The first second-type field effect transistor N1 and the second second-type field effect transistor N2 both include a second second-type active layer 23, a first-type channel layer 22, and a first second-type active layer 21 that are sequentially stacked in a direction away from the substrate and surround the corresponding gate column.

[0188] As an example, the electrical connection relationship between the first first-type field effect transistor P1, the second first-type field effect transistor P2, the first second-type field effect transistor N1 and the second second-type field effect transistor N2 can be implemented in the following manner but is not limited to:

[0189] The first first-type field effect transistor P1 and the first first-type field effect transistor P2 are connected to the first first-type active layer 11, and the first first-type active layer 11 is also connected to the output through hole 6. The first first-type field effect transistor P1 and the second first-type field effect transistor P2 are connected to the second first-type channel layer 12. The first first-type field effect transistor P1 and the second first-type field effect transistor P2 are connected to the second first-type active layer 13, and the second first-type active layer 13 has a first inversion doping region 131, and the first inversion doping region 131 connects the second type channel layer 12 and the first power supply voltage terminal.

[0190] The first second type field effect transistor N1 and the first second type field effect transistor N2 are connected to the first type channel layer 22. The first second type field effect transistor N1 and the second second type field effect transistor N2 are connected to the second second type active layer 23. The second second type active layer 23 of the first second type field effect transistor N1 and the second second type field effect transistor N2 are spaced apart from each other; wherein, the second second type active layer 23 of the first second type field effect transistor N1 has a second inversion doping region 231, and the second inversion doping region 231 connects the first type channel layer 22 and the second power supply voltage terminal; the second second type active layer 23 of the second second type field effect transistor N22 is connected to the output through hole 6.

[0191] In some embodiments, the first second type active layer 21 of the first second type field effect transistor N1 and the second second type field effect transistor N2 can be disposed in the same layer. In some embodiments, the first second type channel layer 22 of the first second type field effect transistor N1 and the second second type field effect transistor N2 can also be disposed in the same layer.

[0192] In some embodiments, the first first-type active layer 11 of the first first-type field effect transistor P1 and the second first-type field effect transistor P2 can be arranged in the same layer. In some embodiments, the second type channel layer 12 of the first first-type field effect transistor P1 and the second first-type field effect transistor P2 can also be arranged in the same layer. In some embodiments, the first first-type field effect transistor P1 and the second first-type field effect transistor P2 can also be arranged in the same layer.

[0193] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0194] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A complementary field effect transistor device, characterized in that: include: At least two layers of field effect transistors are stacked and interconnected in a direction perpendicular to the substrate; wherein, The field effect transistors of the active layer used for connecting to the first power supply voltage terminal are located at the top layer, and the surface of the active layer used for connecting to the first power supply voltage terminal is located at the surface of the corresponding field effect transistor away from the field effect transistor of the bottom layer; The field effect transistors of the active layer connected to the second power supply voltage terminal are located at the bottom layer, and the surface of the active layer connected to the second power supply voltage terminal is located on the surface of the corresponding field effect transistor away from the field effect transistor of the top layer.

2. The complementary field effect transistor device according to claim 1, characterized in that: The at least two layers of field effect transistors include at least two first-type field effect transistors located at the top layer, and at least two second-type field effect transistors located at the bottom layer; wherein, The first-type field effect transistor comprises: a first first-type active layer, a second-type channel layer and a second first-type active layer sequentially stacked in a direction away from the second-type field effect transistor; The second first-type active layer has a first inversion doping region; the first inversion doping region connects the second-type channel layer and the first power supply voltage terminal.

3. The complementary field effect transistor device according to claim 2, characterized in that: Also includes: The first isolation structure is located at least between the second first type active layer of the first type field effect transistor connected to the first power supply voltage terminal and the second first type active layer of the first type field effect transistor not connected to the first power supply voltage terminal.

4. The complementary field effect transistor device according to claim 2 or 3, characterized in that: Also includes: At least one first contact structure is located on a surface of the first inversion doped region facing away from the second type channel layer; The wiring layer is connected correspondingly to the first contact structure.

5. The complementary field effect transistor device according to claim 4, characterized in that: Also includes a first metal pattern; wherein, The first contact structure is a silicided region of the first metal pattern; The wiring layer is a non-silicided region of the first metal pattern.

6. The complementary field effect transistor device according to claim 1, characterized in that: The at least two layers of field effect transistors include at least two first-type field effect transistors located at the top layer, and at least two second-type field effect transistors located at the bottom layer; wherein, The second-type field effect transistor comprises: a first second-type active layer, a first-type channel layer and a second second-type active layer sequentially stacked in a direction away from the first-type field effect transistor; The second second-type active layer has a second inversion doping region; the second inversion doping region is connected to the first-type channel layer and the second power supply voltage terminal.

7. The complementary field effect transistor device according to claim 6, characterized in that: It also includes an insulating layer disposed on one side of the substrate; wherein, The second-type field effect transistor at the bottom layer is arranged on the surface of the insulating layer away from the substrate; The complementary field effect transistor device also includes: The second contact structure is disposed in the trench of the insulating layer and penetrates the insulating layer, and is respectively connected to the substrate and the corresponding second inversion doping region.

8. The complementary field effect transistor device according to claim 7, characterized in that: The second contact structure is ring-shaped; The second-type field effect transistor further includes: a gate column sequentially penetrating the first second-type active layer, the first-type channel layer and the second second-type active layer; the gate column is insulated from the first second-type active layer, the first-type channel layer and the second second-type active layer; The gate pillar is insulated from the second contact structure, and an orthographic projection of the gate pillar on the substrate is located within the orthographic projection range of the inner ring area of ​​the second contact structure on the substrate.

9. The complementary field effect transistor device according to claim 8, characterized in that: The first-type field effect transistor and the second-type field effect transistor located directly above the second-type field effect transistor share the same gate column.

10. A method for preparing a complementary field effect transistor device, characterized in that: include: At least two layers of field effect transistors are stacked and interconnected in a direction perpendicular to the substrate; wherein, The active layer is used to connect each of the field effect transistors of the first power supply voltage terminal and is formed on the topmost layer, and the surface of the active layer used to connect the first power supply voltage terminal is formed on the surface of the corresponding field effect transistor away from the field effect transistor of the bottommost layer; The active layer is used to connect each field effect transistor of the second power supply voltage terminal and is formed at the bottom layer, and the surface of the active layer used to connect the second power supply voltage terminal is formed at the surface of the corresponding field effect transistor away from the field effect transistor of the top layer.

11. The method for preparing a complementary field effect transistor device according to claim 10, characterized in that: The at least two layers of field effect transistors include at least two first-type field effect transistors located at the top layer, and at least two second-type field effect transistors located at the bottom layer; wherein, The first type field effect transistor is formed, comprising: forming a first first-type active layer, a second-type channel layer, and a second first-type active layer in sequence in a direction away from the substrate; A first inversion doping region is formed in the second first-type active layer; the first inversion doping region is used to connect the second-type channel layer and the first power supply voltage terminal.

12. The method for preparing a complementary field effect transistor device according to claim 11, characterized in that: Also includes: forming a first metal pattern on a surface of the first inversion doped region away from the second type channel layer; A silicided region is formed on a portion of the first metal pattern close to the first inversion doped region; the silicided region of the first metal pattern serves as a first contact structure, and a non-silicided region of the first metal pattern serves as a wiring layer.

13. The method for preparing a complementary field effect transistor device according to claim 10, characterized in that: The at least two layers of field effect transistors include at least two first-type field effect transistors located at the top layer, and at least two second-type field effect transistors located at the bottom layer; The second type field effect transistor is formed, comprising: sequentially forming a first second-type active layer, a first-type channel layer, and a second second-type active layer in a direction toward the substrate; A second inversion doping region is formed in the second second-type active layer; the second inversion doping region is used to connect the first-type channel layer and the second power supply voltage terminal.

14. The method for preparing a complementary field effect transistor device according to claim 13, characterized in that: Also includes: An insulating material layer, the second second-type active layer, the first second-type channel layer and the first second-type active layer are sequentially formed on the substrate; wherein the second second-type active layer has the second inversion doping region; Forming a first through hole penetrating the second second-type active layer, the first type channel layer and the first second-type active layer, and removing a portion of the insulating material layer to form a first opening exposing the substrate surface; wherein the orthographic projection of the first opening on the substrate surface includes the orthographic projection of the first through hole on the substrate surface; filling the second contact material layer in the first opening; A portion of the second contact material layer is removed to form a second opening exposing the surface of the substrate, the orthographic projection of the retained second contact material layer on the substrate at least partially overlaps with the orthographic projection of the second inversion doped region on the substrate, and the retained second contact material layer serves as a second contact structure.

15. A logic circuit, characterized in that: The method comprises at least one complementary field effect transistor device according to any one of claims 1 to 9.

16. A logic NAND gate circuit, characterized in that: include: A first first-type field effect transistor, a second first-type field effect transistor, a first second-type field effect transistor, and a second second-type field effect transistor; The first second-type field effect transistor and the first first-type field effect transistor are stacked from bottom to top in a direction perpendicular to the substrate by using a shared first gate column, and the first gate column is connected to the first input terminal; the second second-type field effect transistor and the second first-type field effect transistor are stacked from bottom to top in a direction perpendicular to the substrate by using a shared second gate column, and the second gate column is connected to the second input terminal; The first first-type field effect transistor and the second first-type field effect transistor each include: a first first-type active layer, a second-type channel layer and a second first-type active layer sequentially stacked in a direction away from the substrate and surrounding the circumference of the corresponding gate column; the first first-type active layer of the first first-type field effect transistor and the second first-type field effect transistor are connected, and the first first-type active layer is also connected to the output through hole; the second-type channel layer of the first first-type field effect transistor and the second first-type field effect transistor are connected; the second first-type active layer of the first first-type field effect transistor and the second first-type field effect transistor are connected, and the second first-type active layer has a first inversion doping region, and the first inversion doping region connects the second-type channel layer with the first power supply voltage terminal; The first second-type field effect transistor and the second second-type field effect transistor both include: a second second-type active layer, a first type channel layer and a first second-type active layer stacked in sequence in a direction away from the substrate and surrounding the circumference of the corresponding gate column; the first second-type active layer of the first second-type field effect transistor and the second second-type field effect transistor are connected; the first type channel layer of the first second-type field effect transistor and the second second-type field effect transistor are connected; the second second-type active layer of the first second-type field effect transistor has a second inversion doping region, and the second inversion doping region connects the first type channel layer and the second power supply voltage terminal; the second second-type active layer of the second second-type field effect transistor is connected to the output through hole.

17. A logic NOR gate circuit, characterized in that: include: A first first-type field effect transistor, a second first-type field effect transistor, a first second-type field effect transistor, and a second second-type field effect transistor; The first second-type field effect transistor and the first first-type field effect transistor are stacked from bottom to top in a direction perpendicular to the substrate by using a shared first gate column, and the first gate column is connected to the first input terminal; the second second-type field effect transistor and the second first-type field effect transistor are stacked from bottom to top in a direction perpendicular to the substrate by using a shared second gate column, and the second gate column is connected to the second input terminal; The first first-type field effect transistor and the second first-type field effect transistor each include: a first first-type active layer, a second-type channel layer and a second first-type active layer sequentially stacked in a direction away from the substrate and surrounding the circumference of the corresponding gate column; the first first-type active layer of the first first-type field effect transistor and the second first-type field effect transistor are connected; the second-type channel layer of the first first-type field effect transistor and the second first-type field effect transistor are connected; the second first-type active layer of the first first-type field effect transistor has a first inversion doping region, and the first inversion doping region connects the second-type channel layer and the first power supply voltage terminal; the second first-type active layer of the second first-type field effect transistor is connected to the output through hole; The first second-type field effect transistor and the second second-type field effect transistor both include: a second second-type active layer, a first type channel layer and a first second-type active layer stacked in sequence along a direction away from the substrate and surrounding the circumference of the corresponding gate column; the first second-type active layer of the first second-type field effect transistor and the second second-type field effect transistor is connected, and the first second-type active layer is also connected to the output through hole; the first second-type channel layer of the first second-type field effect transistor and the second second-type field effect transistor is connected; the second second-type active layer of the first second-type field effect transistor and the second second-type field effect transistor is connected, and the second second-type active layer has a second inversion doping region, and the second inversion doping region connects the first type channel layer with the second power supply voltage terminal.

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