SOI device preparation method and SOI device structure
By forming a second trench on the HR-SOI substrate and injecting opposite types of ions to form a buried diode, the problem of surface parasitic conduction of the HR-SOI substrate in high-frequency applications is solved, and the radio frequency performance of the SOI device is achieved Improvement.
Patent Information
- Application Number
- CN202411530550.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-14
AI Technical Summary
HR-SOI substrates are prone to surface parasitic conduction in high-frequency applications, resulting in a decrease in resistivity and a decrease in RF performance of SOI devices.
A second trench is formed on the HR-SOI substrate, exposing the surface of the underlying silicon and injecting it with ions opposite to the type of doped ions in the underlying silicon to form a buried diode to inhibit surface parasitic conduction.
It effectively suppresses the surface parasitic conduction effect of SOI devices, maintains the DC performance of the device, and improves the RF performance.
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Figure CN119451221A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing an SOI device and an SOI device structure. Background Art
[0002] The silicon-on-insulator (SOI, Resistivity-Silicon-On-Insulator) technology introduces a buried oxide layer between the top silicon and the bottom silicon. The buried oxide layer isolates the semiconductor region of the top silicon circuit from the bottom silicon as an electrical insulation layer, reducing parasitic capacitance. Therefore, SOI substrates are widely used in RF, MEMS and other fields. In order to further improve the RF performance of SOI devices and reduce the loss of SOI substrates, the high-resistivity silicon-on-insulator (HR-SOI, High Resistivity-Silicon-On-Insulator) technology is used in the prior art to replace SOI technology. However, in high-frequency applications, HR-SOI substrates are prone to surface parasitic conduction, which causes the resistivity of the HR-SOI substrate to decrease, thereby causing the RF performance of SOI devices to decrease.
[0003] Therefore, how to solve the problem of degradation of RF performance of SOI devices caused by parasitic surface conduction of HR-SOI substrate has become a technical problem that urgently needs to be solved in the industry. Summary of the invention
[0004] The present invention provides a method for preparing an SOI device and an SOI device structure, aiming to solve the problem that the radio frequency performance of the SOI device is reduced due to parasitic surface conduction of an HR-SOI substrate.
[0005] According to a first aspect of the present invention, an embodiment of the present invention provides a method for preparing an SOI device, the method comprising:
[0006] A HR-SOI substrate is provided, wherein a plurality of device active regions are formed on the HR-SOI substrate, and adjacent device active regions are isolated by a shallow trench isolation structure; a gate structure is formed in each device active region, and ion implantation of source and drain regions is completed; wherein the shallow trench isolation structure comprises a first trench and a first oxide layer filled in the first trench; the HR-SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top, and the bottom silicon layer is doped with first type ions;
[0007] forming a second trench at a preset position of the first oxide layer of the shallow trench isolation structure to expose the surface of the underlying silicon;
[0008] Second type ions of a type opposite to the first type ions are implanted into the surface of the underlying silicon exposed at the bottom of the second trench to form an ion implantation region, wherein a buried diode is formed between the ion implantation region and the underlying silicon.
[0009] Optionally, forming a second trench at a preset position of the first oxide layer of the shallow trench isolation structure to expose the surface of the underlying silicon specifically includes:
[0010] forming a first patterned mask layer on the HR-SOI substrate, wherein the first patterned mask layer comprises a second trench pattern;
[0011] The first oxide layer of the shallow trench isolation structure and the corresponding HR-SOI substrate area are etched using the first patterned mask layer as a mask, and the etching is stopped after reaching the surface of the underlying silicon to form a second trench, which is smaller than the first trench and penetrates the first oxide layer of the first trench.
[0012] Optionally, implanting second type ions of a type opposite to the first type ions into the surface of the underlying silicon exposed at the bottom of the second trench to form an ion implantation region comprises:
[0013] Using the first patterned mask layer as a mask, second type ions of a type opposite to the first type ions are implanted into the surface of the underlying silicon exposed at the bottom of the second trench.
[0014] Optionally, after the step of using the first patterned mask layer as a mask to implant second type ions opposite to the first type ions into the surface of the underlying silicon exposed at the bottom of the second trench, the method further comprises:
[0015] removing the first patterned mask layer;
[0016] The ion implantation region is annealed.
[0017] Optionally, implanting second type ions of a type opposite to the first type ions into the surface of the underlying silicon exposed at the bottom of the second trench to form an ion implantation region comprises:
[0018] removing the first patterned mask layer;
[0019] forming a second patterned mask layer on the HR-SOI substrate, wherein the second patterned mask layer comprises an ion implantation region pattern corresponding to the second groove pattern;
[0020] Using the second patterned mask layer as a mask, second type ions of a type opposite to the first type ions are implanted into the surface of the underlying silicon exposed at the bottom of the second trench.
[0021] Optionally, after the step of using the second patterned mask layer as a mask to implant second type ions opposite to the first type ions into the surface of the underlying silicon exposed at the bottom of the second trench, the method further comprises:
[0022] removing the second patterned mask layer;
[0023] The ion implantation region is annealed.
[0024] Optionally, the first type of ions is P + ions, the second type of ions is N + ions; or, the first type of ions is N + ions, the second type of ions is P + ion.
[0025] Optionally, after forming the ion implantation region, the method further includes:
[0026] Depositing a SAB oxide layer on the HR-SOI substrate, wherein the SAB oxide layer fills the second trench and covers a surface of the HR-SOI substrate and a surface of the gate structure;
[0027] Etching the SAB oxide layer to expose the gate structure and the source and drain regions;
[0028] forming a metal silicide layer on the gate structure and the source and drain regions; and
[0029] An interlayer dielectric layer is formed.
[0030] Optionally, etching the SAB oxide layer to expose the gate structure and the source and drain regions includes:
[0031] forming a third patterned mask layer on the surface of the SAB oxide layer;
[0032] Using the third patterned mask layer as a mask, etching the SAB oxide layer to expose the gate structure and the source and drain regions;
[0033] The third patterned mask layer is removed.
[0034] According to a second aspect of the present invention, there is provided an SOI device structure, which is prepared by using the method for preparing an SOI device according to any one of the first aspects, and the SOI device structure comprises:
[0035] An HR-SOI substrate, wherein the HR-SOI substrate comprises a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked in sequence from bottom to top, wherein the bottom silicon layer is doped with first type ions;
[0036] A plurality of device active regions are formed on the HR-SOI substrate; adjacent device active regions are isolated by a shallow trench isolation structure, and each device active region has formed a gate structure and completed source and drain region ion implantation; wherein the shallow trench isolation structure includes a first trench and a first oxide layer filled in the first trench;
[0037] A second trench is formed in the first oxide layer of the shallow trench isolation structure, and the bottom of the second trench exposes the surface of the bottom silicon; and
[0038] An ion implantation region is formed on the surface of the underlying silicon exposed at the bottom of the second trench, and second type ions are implanted in the ion implantation region, the second type ions being of opposite type to the first type ions; a buried diode is formed between the ion implantation region and the underlying silicon.
[0039] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0040] The present invention provides a method for preparing an SOI device and an SOI device structure. After completing the preparation of the device active area, a first oxide layer of a shallow trench isolation structure between adjacent device active areas on an HR-SOI substrate is etched to form a second trench to expose the underlying silicon; then, second type ions are injected into the surface of the underlying silicon exposed at the bottom of the second trench to form a buried diode on the surface of the underlying silicon; thereby, the surface parasitic conduction effect of the SOI device is effectively suppressed while retaining the DC performance of the SOI device.
[0041] Furthermore, the buried diode is formed between the ion implantation area of the second type of ions and the bottom silicon, and thus, only one ion implantation is required to complete the process, which is simple.
[0042] Furthermore, since the active region of the device has been prepared before the second type of ion implantation to form the buried diode, the device performance will not be affected. In addition, the buried oxide layer under the device will not be affected by the ion implantation due to protection, ensuring that the RF performance of the device is basically unaffected.
[0043] Furthermore, the surface of the bottom silicon is exposed through the second trench, so only a small amount of energy is needed to complete the ion implantation of the buried diode. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0045] Figure 1 A schematic diagram of a device structure corresponding to each step of a method for preparing an SOI device in an example;
[0046] Figure 2A-2B A flow chart of a method for preparing an SOI device provided in one embodiment of the present invention;
[0047] Figure 3-Figure 12 It is a schematic diagram of the device structure corresponding to each step of the method for preparing an SOI device provided in an embodiment of the present invention.
[0048] Description of reference numerals:
[0049] 10-Trap-Rich-SOI substrate;
[0050] 11-Trap-Rich-SOI substrate corresponding to the underlying silicon;
[0051] 12-Trap-Rich-SOI substrate corresponding to the trap-rich layer;
[0052] 13-Buried oxide layer corresponding to Trap-Rich-SOI substrate;
[0053] 14-Trap-Rich-SOI substrate corresponding to the top silicon;
[0054] 20-HR-SOI substrate;
[0055] 21-The underlying silicon corresponding to the HR-SOI substrate;
[0056] 22-Buried oxide layer corresponding to HR-SOI substrate;
[0057] 23-The top silicon corresponding to the HR-SOI substrate;
[0058] 24- first oxide layer;
[0059] 25- source and drain region;
[0060] 26-gate structure;
[0061] 27-second groove;
[0062] 281-a first patterned mask layer;
[0063] 282-a second patterned mask layer;
[0064] 283-a third patterned mask layer;
[0065] 291-SAB oxide layer;
[0066] 292-metal silicide layer;
[0067] 211-Ion implantation area. DETAILED DESCRIPTION
[0068] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0069] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0070] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
[0071] As described in the background technology, since the buried oxide layer of the SOI substrate has good insulation properties, the charges (usually positive charges) accumulated during the semiconductor device process cannot be effectively and completely released, which causes the positive charges to easily accumulate in the buried oxide layer, forming a parasitic electric field. The high-resistivity silicon material in the HR-SOI substrate is easily affected by the local electric field. Therefore, the high-resistivity silicon material near the buried oxide layer interface is easy to conduct positive charges under the influence of the parasitic electric field, forming a high-conductivity channel, so that the resistivity of the HR-SOI substrate decreases. This phenomenon is the parasitic surface conduction of the HR-SOI substrate. In high-frequency applications, the resistivity of the HR-SOI substrate will decrease more, which will seriously affect the RF performance of the formed SOI device. The parasitic surface conduction of the HR-SOI substrate will cause the RF performance of the SOI device to decrease.
[0072] In view of the above problems, some solutions have been provided by technicians in this field. For example, please refer to Figure 1 In order to reduce the problem of radio frequency performance degradation of SOI devices caused by parasitic surface conduction, the prior art provides a Trap-Rich-SOI substrate 10, which includes a bottom silicon 11, a trap rich layer (Trap Rich Layer) 12, a buried oxide layer 13 and a top silicon 14 stacked in sequence from bottom to top, wherein the trap rich layer 12 is an amorphous silicon layer.
[0073] This method introduces an amorphous silicon layer between the bottom silicon and the buried oxide layer to form a Trap-Rich-SOI substrate; the Fermi level is fixed near the mid-gap of the interface through the trap-rich layer of amorphous silicon, effectively counteracting the parasitic surface conduction effect in a high-resistance state, so that the RF performance of the Trap-Rich-SOI device will not be greatly reduced. However, since the price of the Trap-Rich-SOI substrate is about 50% more expensive than that of the HR-SOI substrate, the manufacturing cost of the SOI device is too high.
[0074] In view of this, the present invention provides a method for preparing an SOI device, the method comprising:
[0075] A HR-SOI substrate is provided, wherein a plurality of device active regions are formed on the HR-SOI substrate, and adjacent device active regions are isolated by a shallow trench isolation structure; a gate structure is formed in each device active region, and ion implantation of source and drain regions is completed; wherein the shallow trench isolation structure comprises a first trench and a first oxide layer filled in the first trench; the HR-SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top, and the bottom silicon layer is doped with first type ions;
[0076] forming a second trench at a preset position of the first oxide layer of the shallow trench isolation structure to expose the surface of the underlying silicon;
[0077] Second type ions of a type opposite to the first type ions are implanted into the surface of the underlying silicon exposed at the bottom of the second trench to form an ion implantation region, wherein a buried diode is formed between the ion implantation region and the underlying silicon.
[0078] The method for preparing an SOI device provided by the present invention comprises the following steps: after the preparation of the device active area is completed, a second trench is formed by etching the first oxide layer of a shallow trench isolation structure between adjacent device active areas on an HR-SOI substrate to expose the underlying silicon; second type ions are then implanted into the surface of the underlying silicon exposed at the bottom of the second trench to form an ion implantation area, wherein a buried diode is formed between the ion implantation area and the underlying silicon; thereby effectively suppressing the surface parasitic conduction effect of the SOI device while retaining the DC performance of the SOI device.
[0079] Furthermore, compared with the aforementioned method of using Trap-Rich-SOI substrate to prepare devices, the cost is greatly reduced, and the preparation cost of SOI devices is effectively controlled.
[0080] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0081] Figure 2A-2B A schematic diagram of a process for preparing a SOI device provided in one embodiment of the present invention; Figure 3-Figure 12 A schematic diagram of the device structure corresponding to each step of the method for preparing an SOI device provided in an embodiment of the present invention.
[0082] Please refer to Figure 2A-2B , and combined with reference Figure 3-Figure 12 The method for preparing a SOI device provided by an embodiment of the present invention comprises:
[0083] S1: providing a HR-SOI substrate 20, on which a plurality of device active regions have been formed, and adjacent device active regions are isolated by a shallow trench isolation structure; a gate structure 26 has been formed in each device active region, and source and drain region ion implantation has been completed to form source and drain regions 25; wherein the shallow trench isolation structure comprises a first trench and a first oxide layer 24 filled in the first trench; the HR-SOI substrate 20 comprises a bottom silicon 21, a buried oxide layer 22 and a top silicon 23 stacked in sequence from bottom to top, and the bottom silicon 21 is doped with a first type of ions; Figure 3 shown.
[0084] The HR-SOI substrate 20 can be understood as a buried oxide layer 22 added between a bottom silicon layer 21 and a top silicon layer 23 .
[0085] The bottom silicon 21 has a high resistivity characteristic and is a high resistivity bottom silicon, and its resistivity usually reaches 20-10000 ohm·cm. Of course, the present invention is not limited to this. In the embodiment of the present invention, the resistivity can reach, for example, 20-20000 ohm·cm. In the embodiment of the present invention, the substrate can also be other types of high resistivity substrates, such as a high resistivity germanium substrate on an insulator.
[0086] The ions implanted into the source and drain regions may be N + ions (N-type doping ions). Of course, the present invention is not limited to this. In the embodiment of the present invention, the ions injected into the source and drain regions may also be P + ions (P-type doping ions).
[0087] S2: forming a second trench 27 at a preset position of the first oxide layer 24 of the shallow trench isolation structure to expose the surface of the bottom silicon 21; Figure 5 As shown;
[0088] As an implementation manner, S2 may specifically include:
[0089] S21: forming a first patterned mask layer 281 on the HR-SOI substrate 20, wherein the first patterned mask layer 281 includes a second groove pattern;
[0090] S22 : using the first patterned mask layer 281 as a mask, etching the first oxide layer 24 of the shallow trench isolation structure and the corresponding HR-SOI substrate region, and stopping after etching reaches the surface of the bottom silicon 21 to form a second trench 27 .
[0091] The method of forming the first patterned mask layer 281 in S21 specifically includes:
[0092] S211: forming a first mask layer on the HR-SOI substrate 20;
[0093] S212: Patterning the first mask layer to form a first patterned mask layer 281, wherein the first patterned mask layer 281 includes a first blocking region and a first opening region, the first opening region is a second trench pattern, the second trench pattern is smaller than the first trench, and a portion of the first oxide layer 24 in the shallow trench isolation structure is exposed through the first opening region, such as Figure 4 shown.
[0094] The patterning process for the first mask layer specifically includes exposing and developing the first mask layer using a first photomask to form a first patterned mask layer 281 .
[0095] As an example, the material of the first patterned mask layer 281 may be photoresist. Of course, it should be appreciated that the first patterned mask layer 281 may also be other materials and may also be formed in other ways, and the present invention is not limited thereto.
[0096] S3: implanting second type ions opposite to the first type ions into the surface of the underlying silicon 21 exposed at the bottom of the second trench to form an ion implantation region 211 on the surface of the underlying silicon 30, wherein a buried diode is formed between the ion implantation region 211 and the underlying silicon 21; Figure 6 shown.
[0097] in, Figure 6 The ion implantation in is the second type of ion implantation.
[0098] The second type of ions have different ion types or different implantation energies, and the implantation depths of the second type of ions into the bottom silicon are different. Generally, the implantation depths of the second type of ions into the bottom silicon range from 0 to 2 microns.
[0099] Among them, since the second type of ions are opposite to the first type of ions, the ion injection area at the bottom of the second trench will form a diode with the underlying silicon. The depletion junction of the buried diode can interrupt the conduction channel of the parasitic surface conduction effect, so that the resistivity of the underlying silicon will not drop significantly in the vertical direction, thereby effectively suppressing the parasitic surface conduction effect, so that the RF performance of the finally formed SOI device will not be significantly reduced.
[0100] Furthermore, the buried diode in the embodiment of the present invention is formed between the ion implantation region and the bottom silicon, and thus only one ion implantation is required to complete the process, which is simple.
[0101] Since the second trench has been formed between adjacent device active regions and the surface of the bottom silicon 21 is exposed through the second trench, the energy for injecting the second type of ions into the bottom silicon 21 does not need to be very high. The energy for injecting the second type of ions can be, for example, less than 10 keV, and the injection dose can be, for example, 1×10 12 ~1x10 16 / cm 2 In addition, since the active region of the device has been prepared before the second type of ion implantation forms a buried diode with the bottom silicon 21, the implantation of the second type of ion will not affect the performance of the device. The buried oxide layer under the device will not be affected by the ion implantation due to protection, ensuring that the RF performance of the device is basically unaffected.
[0102] As a preferred implementation, step S3 may include:
[0103] S31 : using the first patterned mask layer 281 as a mask, injecting second type ions opposite to the first type ions into the surface of the underlying silicon 21 exposed at the bottom of the second trench 27 .
[0104] As a preferred embodiment, after step S31, the following steps are further included:
[0105] S32: removing the first patterned mask layer 281;
[0106] S33: Annealing the ion implantation region 211 to repair the lattice damage caused by the ion implantation and stimulate the implanted impurities, thereby improving the conductivity and stability of the formed buried diode, so that the buried diode can effectively suppress the parasitic surface conduction effect.
[0107] In another embodiment, step S3 may include:
[0108] S31: removing the first patterned mask layer 281;
[0109] S32: forming a second patterned mask layer 282 on the HR-SOI substrate 20, wherein the second patterned mask layer 282 includes a second blocking region and a second opening region, wherein the second opening region corresponds to the first opening region; wherein the second opening region is an ion implantation region pattern; Figure 7 As shown;
[0110] S33: Using the second patterned mask layer 282 as a mask, injecting second type ions opposite to the first type ions into the surface of the exposed bottom silicon 21 at the bottom of the second trench, such as Figure 8 shown.
[0111] in, Figure 8 The ion implantation in is the second type of ion implantation.
[0112] Furthermore, in a specific implementation manner, after step S33, the following steps are further included:
[0113] S34: removing the second patterned mask layer;
[0114] S35: Annealing the ion implantation region 211 to repair the lattice damage caused by the ion implantation and stimulate the implanted impurities, thereby improving the conductivity and stability of the formed buried diode, so that the buried diode can effectively suppress the parasitic surface conduction effect.
[0115] In one embodiment, the first type of ions is P + ions, the second type of ions is N +Of course, the present invention is not limited thereto, and the first type of ions and the second type of ions may also be N + Ions and P + Ions, as long as the ion types of the first type ions and the second type ions are opposite, a buried diode can be formed.
[0116] As an embodiment, after forming the ion implantation region, the method further includes:
[0117] S4: Depositing a SAB oxide layer 291 on the HR-SOI substrate 20, wherein the SAB oxide layer 291 fills the second trench 27 and covers the surface of the HR-SOI substrate 20 and the surface of the gate structure 26; Fig. 9 shown.
[0118] The SAB oxide layer 291 may be made of silicon oxide or other materials, wherein the area blocked by the SAB oxide layer 291 will not form metal silicide, and since the SAB oxide layer also covers the ion implantation area, it can also protect the ion implantation area.
[0119] S5: Etching the SAB oxide layer 291 to expose the gate structure 26 and the source and drain regions 25. Fig.10 shown.
[0120] In one specific implementation, etching the SAB oxide layer 291 to expose the gate structure 26 and the source and drain regions 25 may include:
[0121] S51: forming a third patterned mask layer 283 on the surface of the SAB oxide layer 291;
[0122] S52: using the third patterned mask layer 283 as a mask to etch the SAB oxide layer 291 to expose the gate structure 26 and the source and drain regions 25;
[0123] The SAB oxide layer 291 is etched to expose the gate structure 26 and the source / drain region 25 , which can be understood as preparing for forming a metal silicide layer on the gate structure 26 and the source / drain region 25 .
[0124] S53: removing the third patterned mask layer;
[0125] The third patterned mask layer is removed to facilitate deposition of an interlayer dielectric layer in a subsequent process.
[0126] S6: forming a metal silicide layer 292 on the gate structure 26 and the source / drain region 25; Fig.11 shown.
[0127] As a specific implementation, forming a metal silicide layer 292 on the gate structure 26 and the source / drain region 25 includes:
[0128] S61: depositing metal on the gate structure 26 and the source / drain region 25;
[0129] The deposited metal may be nickel (Ni). Of course, the present invention is not limited thereto. In an embodiment of the present invention, the deposited metal may also be cobalt (Co), titanium (Ti), platinum (Pt), and the like.
[0130] In a specific embodiment, the method of depositing the metal may be physical vapor deposition. Of course, the present invention is not limited thereto, and the deposition method may also be a metal deposition method such as chemical vapor deposition or sputtering.
[0131] S62 : annealing the deposited metal to form the metal silicide layer 292 .
[0132] S7: forming an interlayer dielectric layer 293; Fig.12 shown.
[0133] In one example, the interlayer dielectric layer 293 may be a silicon dioxide layer. Of course, the present invention is not limited thereto, and may also be other materials with a lower dielectric constant.
[0134] At this point, the front-end process of the SOI device is completed. Of course, in practical applications, the back-end process is also included later. The back-end process is consistent with the conventional practice, and the present invention will not be described in detail here.
[0135] In addition, another embodiment of the present invention further provides an SOI device structure, which is prepared using the method for preparing the SOI device of the aforementioned embodiment, such as Figure 8 As shown, the SOI device structure includes:
[0136] An HR-SOI substrate 20, wherein the HR-SOI substrate 20 comprises a bottom silicon layer 21, a buried oxide layer 22 and a top silicon layer 23 stacked in sequence from bottom to top, wherein the bottom silicon layer 21 is doped with first type ions;
[0137] A plurality of device active regions are formed on the HR-SOI substrate 20; adjacent device active regions are isolated by a shallow trench isolation structure, and a gate structure 26 is formed in each device active region, and ion implantation of source and drain regions has been completed; wherein the shallow trench isolation structure includes a first trench and a first oxide layer 24 filled in the first trench;
[0138] A second trench 27 is formed in the first oxide layer 24 of the shallow trench isolation structure, and the bottom of the second trench 27 exposes the surface of the bottom silicon 21; and
[0139] An ion implantation region 211 is formed on the surface of the underlying silicon 21 exposed at the bottom of the second trench, and second-type ions are implanted in the ion implantation region 211, and the type of the second-type ions is opposite to that of the first-type ions; a buried diode is formed between the ion implantation region 211 and the underlying silicon 21. In the SOI device structure provided by the embodiment of the present invention, an ion implantation region is formed on the surface of the underlying silicon, and the ion implantation region is implanted with second-type ions opposite to the first-type ions in the underlying silicon, so that a buried diode is formed between the ion implantation region and the underlying silicon; thereby effectively suppressing the surface parasitic conduction effect of the SOI device while retaining the DC performance of the SOI device.
[0140] The materials, formation process, working principle, specific implementation method and beneficial effects involved in the SOI device structure in this embodiment can all be found in the preparation method of the SOI device in the embodiment of the present invention, and will not be described in detail here.
[0141] In summary, an embodiment of the present invention provides a method for preparing an SOI device and an SOI device structure. After completing the preparation of the device active area, the first oxide layer of the shallow trench isolation structure between adjacent device active areas on the HR-SOI substrate is etched to form a second trench to expose the underlying silicon; then, the second type of ions are injected into the surface of the underlying silicon exposed at the bottom of the second trench to form a buried diode on the surface of the underlying silicon; thereby, the surface parasitic conduction effect of the SOI device is effectively suppressed while retaining the DC performance of the SOI device.
[0142] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for preparing a SOI device, characterized in that: The method comprises: A HR-SOI substrate is provided, wherein a plurality of device active regions are formed on the HR-SOI substrate, and adjacent device active regions are isolated by a shallow trench isolation structure; a gate structure is formed in each device active region, and ion implantation of source and drain regions is completed; wherein the shallow trench isolation structure comprises a first trench and a first oxide layer filled in the first trench; the HR-SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer stacked in sequence from bottom to top, and the bottom silicon layer is doped with first type ions; forming a second trench at a preset position of the first oxide layer of the shallow trench isolation structure to expose the surface of the underlying silicon; Second type ions of a type opposite to the first type ions are implanted into the surface of the underlying silicon exposed at the bottom of the second trench to form an ion implantation region, wherein a buried diode is formed between the ion implantation region and the underlying silicon.
2. The method for preparing an SOI device according to claim 1, characterized in that: Forming a second trench at a preset position of the first oxide layer of the shallow trench isolation structure to expose the surface of the underlying silicon specifically includes: forming a first patterned mask layer on the HR-SOI substrate, wherein the first patterned mask layer comprises a second groove pattern; The first oxide layer of the shallow trench isolation structure and the corresponding HR-SOI substrate area are etched using the first patterned mask layer as a mask, and the etching is stopped after reaching the surface of the underlying silicon to form a second trench, which is smaller than the first trench and penetrates the first oxide layer of the first trench.
3. The method for preparing an SOI device according to claim 2, characterized in that: Implanting second type ions opposite to the first type ions into the surface of the underlying silicon exposed at the bottom of the second trench to form an ion implantation region, comprising: Using the first patterned mask layer as a mask, second type ions of a type opposite to the first type ions are implanted into the surface of the underlying silicon exposed at the bottom of the second trench.
4. The method for preparing an SOI device according to claim 3, characterized in that: After the step of using the first patterned mask layer as a mask to implant second type ions opposite to the first type ions into the surface of the underlying silicon exposed at the bottom of the second trench, the method further comprises: removing the first patterned mask layer; The ion implantation region is annealed.
5. The method for preparing an SOI device according to claim 2, characterized in that: Implanting second type ions opposite to the first type ions into the surface of the underlying silicon exposed at the bottom of the second trench to form an ion implantation region, comprising: removing the first patterned mask layer; forming a second patterned mask layer on the HR-SOI substrate, wherein the second patterned mask layer comprises an ion implantation region pattern corresponding to the second groove pattern; Using the second patterned mask layer as a mask, second type ions of a type opposite to the first type ions are implanted into the surface of the underlying silicon exposed at the bottom of the second trench.
6. The method for preparing a SOI device according to claim 5, characterized in that: After the step of implanting second type ions opposite to the first type ions into the surface of the underlying silicon exposed at the bottom of the second trench using the second patterned mask layer as a mask, the method further comprises: removing the second patterned mask layer; The ion implantation region is annealed.
7. The method for preparing an SOI device according to claim 1, characterized in that: The first type of ions is P + ions, the second type of ions is N + ions; or, the first type of ions is N + ions, the second type of ions is P + ion.
8. The method for preparing a SOI device according to claim 1, characterized in that: After forming the ion implantation area, the method further comprises: Depositing a SAB oxide layer on the HR-SOI substrate, wherein the SAB oxide layer fills the second trench and covers a surface of the HR-SOI substrate and a surface of the gate structure; Etching the SAB oxide layer to expose the gate structure and the source and drain regions; forming a metal silicide layer on the gate structure and the source and drain regions; and An interlayer dielectric layer is formed.
9. The method for preparing a SOI device according to claim 8, characterized in that: The SAB oxide layer is etched to expose the gate structure and the source and drain regions, including: forming a third patterned mask layer on the surface of the SAB oxide layer; Using the third patterned mask layer as a mask, etching the SAB oxide layer to expose the gate structure and the source and drain regions; The third patterned mask layer is removed.
10. A SOI device structure, characterized in that: Prepared by the method for preparing an SOI device according to any one of claims 1 to 9, the SOI device structure comprises: An HR-SOI substrate, wherein the HR-SOI substrate comprises a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked in sequence from bottom to top, wherein the bottom silicon layer is doped with first type ions; A plurality of device active regions are formed on the HR-SOI substrate; adjacent device active regions are isolated by a shallow trench isolation structure, and each device active region has formed a gate structure and completed source and drain region ion implantation; wherein the shallow trench isolation structure includes a first trench and a first oxide layer filled in the first trench; A second trench is formed in the first oxide layer of the shallow trench isolation structure, and the bottom of the second trench exposes the surface of the bottom silicon; and An ion implantation region is formed on the surface of the underlying silicon exposed at the bottom of the second trench, and second type ions are implanted in the ion implantation region, the second type ions being of opposite type to the first type ions; a buried diode is formed between the ion implantation region and the underlying silicon.