Display panel and display panel manufacturing method

Abstract

A display panel according to the present invention includes: a partition wall including a first partition wall layer and a second partition wall layer disposed on the first partition wall layer and defining a partition wall opening portion and an inspection opening portion; and an inspection pattern disposed within the inspection opening, the partition opening including: a first region defined by an inner surface of the first partition layer; and a second region defined by an inner surface of the second partition layer and having a smaller width than the first region, the inspection pattern including the same material as the first partition layer.

Description

Technical Field

[0001] The present invention relates to a display panel and a method for manufacturing the same, and more particularly, to a display panel with improved process reliability and a method for manufacturing the same. Background Art

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include display panels that display images. Various display panels are being developed as display panels, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0003] An organic light emitting display panel may include an anode, a cathode and a light emitting pattern. The light emitting pattern may be separated according to each light emitting area, and the cathode provides a common voltage according to each light emitting area. Summary of the invention

[0004] An object of the present invention is to provide a display panel and a method for manufacturing the same that improves process reliability in a display panel in which light-emitting elements are formed without using a metal mask.

[0005] The display panel according to the present invention includes: a partition wall, including a first partition wall layer and a second partition wall layer arranged on the first partition wall layer, and defining a partition wall opening and an inspection opening; and an inspection pattern, arranged in the inspection opening, the partition wall opening including: a first area defined by the inner side surface of the first partition wall layer; and a second area defined by the inner side surface of the second partition wall layer and having a width smaller than that of the first area, and the inspection pattern includes the same substance as the first partition wall layer.

[0006] It may be characterized in that the inspection opening portion includes: a third area defined by the inner side surface of the first partition layer; and a fourth area defined by the inner side surface of the second partition layer, and the inspection pattern is arranged in the third area and not arranged in the fourth area.

[0007] The method may be characterized in that each of the inspection openings and the inspection patterns is provided in plural, and one inspection pattern is arranged in each of the inspection openings.

[0008] The method may be characterized in that each of the inspection opening and the inspection pattern is provided in plural, and a plurality of the inspection patterns having mutually different widths are arranged in each of the inspection openings.

[0009] It may be characterized in that the display panel further includes: a light emitting element including an anode, a light emitting pattern and a cathode, and is arranged in the partition wall opening, and the cathode is in contact with the partition wall in the partition wall opening.

[0010] It may be characterized in that the display panel further comprises: a thin film encapsulation layer, which is arranged on the light emitting element, and the inspection pattern is in contact with the thin film encapsulation layer.

[0011] The display panel manufacturing method according to the present invention includes: a step of forming a preliminary partition wall including a first preliminary partition wall layer and a second preliminary partition wall layer arranged on the first preliminary partition wall layer; a step of etching the preliminary partition wall once; and a step of etching the preliminary partition wall twice to form a partition wall including a first partition wall layer and a second partition wall layer arranged on the first partition wall layer, an initial inspection pattern is formed in the step of etching the preliminary partition wall once, and an inspection pattern is formed from the initial inspection pattern in the step of etching the preliminary partition wall twice, and the inspection pattern includes the same substance as the first partition wall layer.

[0012] It may be characterized in that the step of etching the preliminary partition wall once includes the step of etching the first preliminary partition wall layer and the second preliminary partition wall layer, and the step of etching the preliminary partition wall twice includes the step of etching the first preliminary partition wall layer.

[0013] It may be characterized in that each of the initial inspection patterns includes: a first initial inspection pattern layer patterned from the first preliminary partition wall layer; and a second initial inspection pattern layer patterned from the second preliminary partition wall layer.

[0014] It may be characterized in that the initial check pattern includes a first initial check pattern and a second initial check pattern having a width wider than the first initial check pattern, and in the step of etching the preliminary partition twice, the first initial check pattern is removed, and the second initial check pattern layer in the second initial check pattern is removed, and a portion of the first initial check pattern layer in the second initial check pattern remains, thereby forming the check pattern.

[0015] The method may be characterized in that, in the step of etching the preliminary partition wall twice, an end portion defined as a portion where the second partition wall layer protrudes beyond the first partition wall layer is formed on the partition wall.

[0016] It may be characterized in that the display panel manufacturing method further includes: a step of inspecting the end portion after the step of etching the preliminary partition wall twice, and in the step of inspecting the end portion, the length of the end portion is identified by determining whether the initial inspection pattern is removed in the step of etching the preliminary partition wall twice.

[0017] It may be characterized in that, before the step of forming the preliminary partition wall, the display panel manufacturing method further includes: the step of forming a preliminary measurement pattern including a first preliminary measurement layer containing the same substance as the first preliminary partition wall layer and a second preliminary measurement layer containing the same substance as the second preliminary partition wall layer and arranged on the first preliminary measurement layer; the step of etching the preliminary measurement pattern to form an initial measurement pattern; the step of etching the initial measurement pattern to form a measurement pattern; and the step of predicting the length of the end portion, the initial measurement patterns having widths different from each other.

[0018] It may be characterized in that the step of etching the preliminary measurement pattern is performed under substantially the same etching conditions as the step of etching the preliminary partition once, and the step of etching the initial measurement pattern is performed under substantially the same etching conditions as the step of etching the preliminary partition twice.

[0019] It may be characterized in that each of the initial measurement patterns includes: a first initial measurement layer patterned from the first preliminary measurement layer; and a second initial measurement layer patterned from the second preliminary measurement layer.

[0020] It may be characterized in that the initial measurement pattern includes a first type pattern and a second type pattern, and in the step of etching the initial measurement pattern, the first type pattern is removed, and the second initial measurement layer in the second type pattern is removed, and a part of the first initial measurement layer in the second type pattern remains, thereby forming the measurement pattern.

[0021] It may be characterized in that, in the step of predicting the length of the end portion, a lower limit value of the length of the end portion is predicted as a width of the first type of pattern to be removed.

[0022] In the step of predicting the length of the end portion, the length of the end portion is predicted as a difference between a width of the second type pattern and a width of the measurement pattern.

[0023] The display panel manufacturing method according to the present invention includes: a step of forming a plurality of initial measurement patterns, each including a first initial measurement layer and a second initial measurement layer arranged on the first initial measurement layer; a step of forming a measurement pattern from the initial measurement patterns; a step of predicting the length of an end portion by means of the measurement pattern; and a step of forming a partition wall including a first partition wall layer and a second partition wall layer arranged on the first partition wall layer and defining the end portion, wherein the first initial measurement layer includes the same substance as the first partition wall layer, the second initial measurement layer includes the same substance as the second partition wall layer, and the measurement pattern is formed by leaving the first initial measurement layer of any one of the initial measurement patterns and removing the second initial measurement layer of any one of the initial measurement patterns.

[0024] It may be characterized in that the step of forming the partition wall includes: the step of forming a preliminary partition wall including a first preliminary partition wall layer and a second preliminary partition wall layer arranged on the first preliminary partition wall layer; the step of performing a first etching on the preliminary partition wall so as to etch the first preliminary partition wall layer and the second preliminary partition wall layer; and the step of performing a second etching on the preliminary partition wall so as to etch the first preliminary partition wall layer, the step of forming the initial measurement pattern is performed under substantially the same etching conditions as the step of etching the preliminary partition wall once, and the step of forming the measurement pattern is performed under substantially the same etching conditions as the step of etching the preliminary partition wall twice. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1a is a perspective view of a display device according to an embodiment of the present invention.

[0026] Figure 1b is an exploded perspective view of a display device according to an embodiment of the present invention.

[0027] Figure 2 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0028] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0029] Figure 4 FIG. 1 is a plan view showing an enlarged portion of a display area of ​​a display panel according to an embodiment of the present invention.

[0030] Figure 5 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention.

[0031] Figure 6 It is along Figure 4 A cross-sectional view of a display panel according to an embodiment of the present invention taken along line II'.

[0032] Figure 7 is a plan view of a part of the structure of a display panel according to an embodiment of the present invention.

[0033] Figure 8 It is along Figure 7 A cross-sectional view of a display panel according to an embodiment of the present invention is taken along line II-II'.

[0034] Fig. 9 It is along Figure 7 A cross-sectional view of a display panel according to an embodiment of the present invention is taken along line II-II'.

[0035] Fig.10 is a flow chart showing a method for manufacturing a display panel according to an embodiment of the present invention.

[0036] Figures 11a to 11e is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0037] Figures 12a to 12c is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0038] Fig.13 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present invention.

[0039] Fig.14 is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0040] Fig.15a is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0041] Fig.15b FIG. 1 is a plan view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0042] Fig.16a is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0043] Fig.16b FIG. 1 is a plan view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0044] (Explanation of Reference Numerals)

[0045] DP: Display Panel PW: Next Door

[0046] OP-P: Next door opening OP-IN: Inspection opening

[0047] INP: Inspection pattern MSP: Measurement pattern DETAILED DESCRIPTION

[0048] In this specification, when it is mentioned that a certain constituent element (or region, layer, part, etc.) is "on" other constituent elements, "connected to" or "combined to" other constituent elements, it means that the certain constituent element can be directly configured / connected / combined on other constituent elements or a third constituent element can be configured between them.

[0049] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. "And / or" includes all combinations that can be defined by the associated components.

[0050] The terms first, second, etc. may be used to describe various constituent elements, but the constituent elements are not limited by the terms. The terms are only used to distinguish one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. Singular expressions include plural expressions unless otherwise expressly indicated in the context.

[0051] In addition, terms such as “below”, “lower side”, “above”, and “upper side” are used to explain the relationship between components shown in the drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0052] The terms "including" or "having" should be understood as being used to specify the existence of the features, numbers, steps, tasks, constituent elements, parts or their combinations recorded in the specification, and do not preclude the existence or additional possibilities of one or more other features or numbers, steps, tasks, constituent elements, parts or their combinations.

[0053] In this specification, "direct configuration" may mean that there is no additional layer, film, region, disk, component, etc. between a structure such as a layer, film, region, disk, component, etc. and another member. For example, "direct configuration" may mean that no additional component such as a bonding component is used between two layers or two components.

[0054] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. In addition, terms such as terms defined in commonly used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, and should not be interpreted as too idealistic or too formalistic unless explicitly defined herein.

[0055] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0056] Figure 1a is a perspective view of a display device according to an embodiment of the present invention. Figure 1b is an exploded perspective view of a display device according to an embodiment of the present invention. Figure 2 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0057] In one embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an external advertising board. In addition, the display device DD may be a small or medium-sized electronic device such as a personal computer, a notebook computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet, and a camera. These are only presented as embodiments, and other display devices may also be used as long as they do not deviate from the concept of the present invention. In this embodiment, the display device DD is exemplarily shown as a smart phone.

[0058] Reference Figure 1a , Figure 1b as well as Figure 2 The display device DD can display an image IM toward the third direction DR3 on a display surface FS that is parallel to each of the first direction DR1 and the second direction DR2. The image IM may include a dynamic image, and of course, may also include a still image. Figure 1a , a clock window and an icon are shown as an example of the image IM. The display surface FS displaying the image IM may correspond to the front surface of the display device DD.

[0059] In this embodiment, the front side (or top side) and the back side (or bottom side) of each component are defined based on the direction in which the image IM is displayed. The front side and the back side may be opposite to each other in the third direction DR3, and the normal direction of each of the front side and the back side may be substantially parallel to the third direction DR3. On the other hand, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and may be transformed into other directions. In this specification, "on a plane" may be defined as a state observed in the third direction DR3.

[0060] like Figure 1bAs shown, the display device DD according to this embodiment may include a window WP, a display module DM and a housing HAU. The window WP and the housing HAU may be combined with each other to form the appearance of the display device DD.

[0061] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front side of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0062] The frame area BZA may be an area with a relatively low light transmittance compared to the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA. On the other hand, it is shown as an example, and the frame area BZA may be omitted in the window WP according to an embodiment of the present invention. The window WP may include at least one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0063] The display module DM may be disposed below the window WP. The display module DM may be a structure that substantially generates an image IM. The image IM generated in the display module DM is displayed on the display surface IS of the display module DM and is recognized by the user externally through the transmission area TA.

[0064] The display surface IS of the display module DM includes a display area DA and a non-display area NDA. The display area DA may be an area activated according to an electrical signal. The non-display area NDA is adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA, as an area covered by the frame area BZA, may not be recognized from the outside.

[0065] like Figure 2 As shown, the display module DM may include a display panel DP and an input sensor INS. Although not shown separately, a display device DD according to an embodiment of the present invention (see Figure 1a ) may also include a protective component arranged under the display panel DP or an anti-reflection component and / or a window component arranged on the input sensor INS.

[0066] The display panel DP may be a light-emitting display panel. However, this is merely illustrative and is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0067] The display panel DP may include a base layer BL, a circuit element layer DP-CL configured on the base layer BL, a display element layer DP-OL, and a thin film encapsulation layer TFE. The input sensor INS may be directly configured on the thin film encapsulation layer TFE. In this specification, "the A structure is directly configured on the B structure" means that no adhesive layer is configured between the A structure and the B structure.

[0068] The base layer BL may include at least one plastic film. The base layer BL as a flexible substrate may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1b The display area DA and the non-display area NDA described in the figure may be defined in the same manner on the base layer BL.

[0069] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, and the like.

[0070] The display element layer DP-OL may include a partition wall and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0071] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be configured to improve optical efficiency, and some of which may be configured to protect the organic light emitting diode.

[0072] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single-layer or multi-layer conductive layer. In addition, the input sensor INS may include a single-layer or multi-layer insulating layer. The input sensor INS may sense the external input in a capacitive manner. However, this is merely illustrative and is not limited thereto. For example, in one embodiment, the input sensor INS may also sense the external input in an electromagnetic induction manner or a pressure sensing manner. On the other hand, the input sensor INS may be omitted in another embodiment of the present invention.

[0073] like Figure 1bAs shown, the housing HAU can be combined with the window WP. The housing HAU can be combined with the window WP to provide a predetermined internal space. The display module DM can be accommodated in the internal space.

[0074] The housing HAU may include a relatively rigid material. For example, the housing HAU may include glass, plastic, or metal, or may include a plurality of frames and / or plates formed by a combination thereof. The housing HAU may stably protect the structure of the display device DD accommodated in the internal space from external impacts.

[0075] Figure 3 is a plan view of a display panel according to an embodiment of the present invention.

[0076] Reference Figure 3 , a display area DA and a non-display area NDA around the display area DA may be defined in the display panel DP. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a drive circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished by the presence or absence of the pixel PX. The pixel PX may be configured in the display area DA. The drive circuit GDC and the pad portion PLD may be configured in the non-display area NDA.

[0077] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0078] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding pixel in the pixels PX, and each of the data lines DL may be connected to a corresponding pixel in the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the drive circuit GDC and provide control signals to the drive circuit GDC.

[0079] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate line GL. The gate driving circuit may also output another control signal to the pixel driving circuit.

[0080] The pad portion PLD may be a portion for connecting a flexible circuit substrate. The pad portion PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit substrate to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line in the signal line SGL. The pixel pad D-PD may be connected to the corresponding pixel PX through the signal line SGL. In addition, any one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0081] In addition, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit substrate to the input sensor INS (see Figure 2 However, the input pad may be configured on the input sensor INS (refer to Figure 2 ) and connected to the pixel pad D-PD and a separate circuit substrate. Alternatively, the input sensor INS can be omitted (refer to Figure 2 ), and may not include input pads.

[0082] Figure 4 FIG. 1 is a plan view showing an enlarged portion of a display area of ​​a display panel according to an embodiment of the present invention. Figure 4 The display module DM (refer to Figure 1b ) display surface IS (refer to Figure 1b ) is a plane of the display module DM observed from above, and shows the arrangement of the light-emitting areas PXA-R, PXA-G, and PXA-B.

[0083] Reference Figure 4 The display area DA may include first to third light emitting areas PXA-R, PXA-G, PXA-B and a peripheral area NPXA surrounding the first to third light emitting areas PXA-R, PXA-G, PXA-B. The first to third light emitting areas PXA-R, PXA-G, PXA-B may be connected to the light emitting elements ED1, ED2, ED3 (refer to Figure 6 ) corresponding to the area of ​​light provided by the first to third light emitting areas PXA-R, PXA-G, PXA-B according to the direction of the display module DM (refer to Figure 2 ) are distinguished by the color of the light emitted from the outside.

[0084] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may respectively provide light of first to third colors having different colors from each other. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the examples of the first to third colors of light are not necessarily limited to the examples.

[0085] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be defined as a region where the upper surface of the anode is exposed through a light emitting opening to be described later. The peripheral region NPXA may set the boundary of the first to third light emitting regions PXA-R, PXA-G, and PXA-B and prevent color mixing between the first to third light emitting regions PXA-R, PXA-G, and PXA-B.

[0086] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be provided in plurality and have a predetermined arrangement form in the display area DA and are repeatedly configured. For example, the first and third light emitting regions PXA-R and PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light emitting region PXA-G may be arranged along the first direction DR1 to form a "second group". Each of the "first group" and the "second group" may be provided in plurality, and the "first group" and the "second group" may be alternately arranged with each other along the second direction DR2.

[0087] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0088] on the other hand, Figure 4 The arrangement of the first to third light emitting regions PXA-R, PXA-G, and PXA-B is exemplarily shown, but is not limited thereto and may be arranged in various forms. Figure 4 As shown, in one embodiment, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have a pentile arrangement. Alternatively, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may also have a stripe arrangement or a diamond (Diamond PixelTM) arrangement.

[0089] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have various shapes on a plane, for example, polygonal, circular, or elliptical shapes. Figure 4 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a rhombus shape) on a plane and the second light emitting region PXA-G having an octagonal shape are exemplarily shown.

[0090] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same shape as each other on a plane, or at least a portion thereof may have a different shape from each other. Figure 4 The first and third light emitting regions PXA-R and PXA-B having the same shape as each other on a plane and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-R and PXA-B are exemplarily shown.

[0091] At least a portion of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have different areas on a plane. In one embodiment, the area of ​​the first light-emitting region PXA-R emitting red light may be larger than the area of ​​the second light-emitting region PXA-G emitting green light, and smaller than the area of ​​the third light-emitting region PXA-B emitting blue light. However, the size relationship between the first to third light-emitting regions PXA-R, PXA-G, and PXA-B according to the light-emitting color is not limited thereto, and may be determined according to the display module DM (refer to Figure 2 ) design. In addition, not limited to this, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may also have the same area as each other on a plane.

[0092] On the other hand, the display module DM of the present invention (refer to Figure 2 The shapes, areas, and arrangements of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B can be determined according to the color of the light emitted or the display module DM (see Figure 2 ) size, structure and various designs are carried out, not limited to Figure 4 The embodiment shown.

[0093] Figure 5 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. Figure 5 Reference Figure 2 The description will be given below, and the description of the same figure numerals will be omitted.

[0094] Figure 5 The display area DA is shown in an enlarged manner (see Figure 4 ) within a light emitting area PXA, Figure 5 The light emitting area PXA can be Figure 4 Corresponding to any one of the first to third light emitting areas PXA-R, PXA-G, PXA-B.

[0095] Reference Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OL, and a thin film encapsulation layer TFE.

[0096] The display panel DP may include a plurality of insulating layers and semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers may be formed by coating, evaporation, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OL may be formed.

[0097] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transfer region SCL, first to fifth insulating layers 10, 20, 30, 40, 50, an upper electrode EE, and a plurality of connection electrodes CNE1, CNE2.

[0098] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0099] A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, it is not limited thereto, and the semiconductor pattern may also include amorphous silicon or metal oxide. Figure 5 Only a part of the semiconductor pattern is shown exemplarily, and in the plurality of light emitting regions PXA-R, PXA-G, PXA-B (refer to Figure 4 ) can also be configured with a semiconductor pattern. The semiconductor pattern can be arranged in a specific rule through multiple light-emitting areas PXA-R, PXA-G, and PXA-B. The semiconductor pattern can have different electrical properties depending on whether it is doped or not. The semiconductor pattern may include a first area with a large doping concentration and a second area with a small doping concentration. The first area may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a first area doped with a P-type dopant.

[0100] The first region may be more conductive than the second region and may substantially function as an electrode or a signal line. The second region may substantially correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be the active region of a transistor, another portion may be the source or drain of the transistor, and another portion may be a conductive region.

[0101] The source S, the active electrode A, and the drain D of the transistor TR1 may be formed from a semiconductor pattern. Figure 5 2 shows a portion of a signal transmission region SCL formed from a semiconductor pattern. Although not shown separately, the signal transmission region SCL may be connected to the drain D of the transistor TR1 in a plane.

[0102] The first to fifth insulating layers 10, 20, 30, 40, 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, 50 may be inorganic layers or organic layers.

[0103] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active A, the drain D, and the signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The upper electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the upper electrode EE.

[0104] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 penetrating the first to third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0105] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0106] The display element layer DP-OL may be disposed on the circuit element layer DP-CL. The display element layer DP-OL may include a light emitting element ED, a sacrificial pattern SP, a pixel defining layer PDL, a partition wall PW, and a dummy pattern DMP.

[0107] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode). Each of the first to third light emitting elements ED1, ED2, ED3 to be described later may include Figure 5 The description of the anode AE, the emission pattern EP, and the cathode CE can be applied to all of the anodes, emission patterns, and cathodes of each of the first to third light emitting elements.

[0108] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 by the connection contact hole CNT-3 defined by penetrating the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transfer region SCL through the first and second connection electrodes CNE1 and CNE2, thereby being electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer or multi-layer structure. The anode AE ​​may include multiple layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (or a lower ITO layer), a layer including Ag (or an Ag layer) disposed on the lower ITO layer, and a layer including ITO (or an upper ITO layer) disposed on the Ag layer.

[0109] The sacrificial pattern SP may be disposed between the anode AE ​​and the pixel defining film PDL. The sacrificial pattern SP may correspond to a portion of a layer provided to prevent the anode AE ​​from being damaged in the formation process of the partition opening OP-P to be described later. The sacrificial opening OP-S that exposes a portion of the top of the anode AE ​​may be defined in the sacrificial pattern SP. The sacrificial opening OP-S may overlap with the light emitting opening OP-E to be described later. The sacrificial pattern SP may include an amorphous transparent conductive oxide. For example, the sacrificial pattern SP may be zinc oxide (ZnO) doped with aluminum (Al). x ).

[0110] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel defining film PDL may define a light emitting opening OP-E. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0111] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to this embodiment, the upper surface of the anode AE ​​may be separated from the pixel defining film PDL in a cross section via the sacrificial pattern SP, thereby preventing the anode AE ​​from being damaged during the formation process of the light emitting opening OP-E.

[0112] On a plane, the area of ​​the light-emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. That is, the inner side surface of the pixel defining film PDL defining the light-emitting opening OP-E may be closer to the center of the anode AE ​​than the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, this is not limited to this, and the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S may also be substantially aligned with the inner side surface of the pixel defining film PDL defining the corresponding light-emitting opening OP-E. At this time, the light-emitting area PXA may also be regarded as the area of ​​the anode AE ​​exposed from the corresponding sacrificial opening OP-S.

[0113] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ) in any one of the following. For example, silicon nitride (SiN x ). The pixel defining film PDL may be disposed between the anode AE ​​and the partition wall PW, and may block the electrical connection between the anode AE ​​and the partition wall PW. However, not limited thereto, the pixel defining film PDL may also include an organic insulating material. In addition, the pixel defining film PDL may also be provided as a single film, or the pixel defining film PDL may also be provided as a plurality of films. In the case where the pixel defining film PDL is provided as a plurality of films, the plurality of films may also include different substances from each other.

[0114] The partition wall PW may be disposed on the pixel defining layer PDL. The partition wall PW may define a partition wall opening OP-P. The partition wall opening OP-P may correspond to the light emitting opening OP-E and expose at least a portion of the anode AE.

[0115] The partition wall PW may have an undercut shape in cross section. The partition wall PW may include a plurality of layers stacked in sequence, and at least one of the plurality of layers may be recessed compared to the other layers. At least one of the plurality of layers included in the partition wall PW may be protruding compared to the other layers. Thus, the partition wall PW may include an end portion TP.

[0116] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition layer PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. With the light emitting area PXA as a reference, the first partition wall layer L1 may be relatively recessed compared to the second partition wall layer L2. That is, the first partition wall layer L1 may be formed by undercutting the second partition wall layer L2.

[0117] On the other hand, although the accompanying drawings only show the state in which the partition wall PW is configured with the first partition wall layer L1 and the second partition wall layer L2, it is not limited to this. A third partition wall layer can be configured on the second partition wall layer L2 or under the first partition wall layer L1. It is not limited to any one embodiment.

[0118] The first partition layer L1 may have conductivity. The first partition layer L1 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (Transparent Conductive Oxide, TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (Induim Gallium Zinc Oxide, IGZO) or aluminum zinc oxide (Aluminuin Zinc Oxide).

[0119] The second partition layer L2 is disposed on the first partition layer L1. The second partition layer L2 may include a material having the same etching selectivity as the first partition layer L1. As an example, for the chemical solution EC described later (refer to Fig.11d ) The reactivity of the second partition layer L2 may be lower than that of the first partition layer L1. The first partition layer L1 is relatively recessed relative to the light emitting area PXA compared to the second partition layer L2. The second partition layer L2 may be defined at the end TP formed at the partition PW.

[0120] The end TP of the partition wall PW can be defined as a portion of the second partition wall layer L2 that protrudes from the first partition wall layer L1 toward the light emitting region PXA. The length d-TP of the end TP can be defined as a length of the second partition wall layer L2 that protrudes from the upper surface U-L1 of the first partition wall layer L1 toward the light emitting region PXA. In the present embodiment, the upper surface of the second partition wall layer L2 can form the uppermost portion of the partition wall PW and is defined as being formed on the upper surface of the end TP of the partition wall PW.

[0121] In one embodiment, the second partition layer L2 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a transparent conductive oxide (Transparent Conductive Oxide, TCO) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (ZincOxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (Induim Gallium Zinc Oxide, IGZO) or aluminum zinc oxide (Aluminuin Zinc Oxide).

[0122] Alternatively, in another embodiment of the present invention, the second partition layer L2 may include an insulating material. For example, the second partition layer L2 may include an inorganic insulating material, and as an example, may include a silicon compound. For example, the second partition layer L2 may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y )

[0123] The partition opening OP-P defined in the partition PW may include a first area A1 (see Fig.11e ) and the second area A2 (refer to Fig.11e The first partition layer L1 may include a first region A1 defining the partition opening OP-P (see Fig.11e ) of the first inner side surface S1-P, the second partition layer L2 may include a second area A2 (refer to Fig.11e )'s second inner side surface S2-P.

[0124] The first inner side surface S1-P of the first partition layer L1 may be arranged to be relatively recessed inwardly relative to the second inner side surface S2-P of the second partition layer L2. Fig.11e ) can be compared to the second inner side surface S2-P of the second partition layer L2 defining the first area A1 (refer to Fig.11e ) of the first partition layer L1 protrudes and is adjacent to the center of the anode AE. Fig.11e ) can be the same width as the second area A2 (refer to Fig.11e ) are different in width. The second area A2 (refer to Fig.11e ) may be wider than the first area A1 (refer to Fig.11e ) is narrow in width.

[0125] On the other hand, Figure 5 illustratively shows that the first inner side surface S1-P of the first partition layer L1 has a tapered shape relative to the upper surface of the pixel defining layer PDL, but is not limited thereto. For example, the first inner side surface S1-P may also have a vertically extending side wall, or may have an inverted tapered shape. Figure 5 The second inner side surface S2 -P of the second partition layer L2 is exemplarily shown to extend perpendicularly to the upper surface of the pixel defining film PDL, but the present invention is not limited thereto. For example, the second inner side surface S2 -P may also have a tapered shape or an inverse tapered shape relative to the upper surface of the pixel defining film PDL.

[0126] The light-emitting pattern EP may be arranged on the anode AE. The light-emitting pattern EP may include a light-emitting layer including a light-emitting substance. The light-emitting pattern EP may also include a hole injection layer (HIL) and a hole transport layer (HTL) arranged between the anode AE ​​and the light-emitting layer, and may also include an electron transport layer (ETL) and an electron injection layer (EIL) arranged on the light-emitting layer. The light-emitting pattern EP may also be called an "organic layer" or an "intermediate layer".

[0127] The light emitting pattern EP may be patterned by being defined at the end of the partition wall PW. The light emitting pattern EP may be disposed inside the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL exposed from the partition wall opening OP-P.

[0128] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned by being defined at an end portion of the partition wall PW. The cathode CE may be in contact with the first inner side surface S1 -P of the first partition wall layer L1 .

[0129] The partition wall PW may receive a bias voltage (or a common voltage), and thus the cathode CE may be electrically connected to the partition wall PW and receive the bias voltage (or the common voltage) from the partition wall PW.

[0130] According to an embodiment of the present invention, the display panel DP may further include a capping pattern CP. The capping pattern CP may be disposed in the partition opening OP-P and on the cathode CE. The capping pattern CP may be patterned by being formed at the end of the partition PW.

[0131] exist Figure 5 The capping pattern CP is illustratively shown as being non-contacting with the second inner side surface S2-P of the second partition layer L2, but is not limited thereto. For example, the capping pattern CP may also be formed to be in contact with the second inner side surface S2-P of the second partition layer L2. On the other hand, according to another embodiment of the present invention, the capping pattern CP may be omitted.

[0132] The dummy pattern DMP may be disposed on the partition wall PW. The dummy pattern DMP may include a first layer dummy pattern D1, a second layer dummy pattern D2, and a third layer dummy pattern D3. The first to third layers of dummy patterns D1, D2, and D3 may be sequentially stacked along the third direction DR3 on the upper surface of the second partition wall layer L2 of the partition wall PW.

[0133] The first dummy pattern D1 may include an organic substance. For example, the first dummy pattern D1 may include the same substance as the light emitting pattern EP. The first dummy pattern D1 may be formed simultaneously with the light emitting pattern EP through one process, and may be separated from the light emitting pattern EP by the undercut shape of the partition wall PW.

[0134] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as the cathode CE. The second dummy pattern D2 may be formed simultaneously with the cathode CE through one process, and may be separated from the cathode CE by the undercut shape of the partition wall PW.

[0135] The third layer dummy pattern D3 may include the same material as the capping pattern CP. The third layer dummy pattern D3 may be formed simultaneously with the capping pattern CP through one process, and may be formed separately from the capping pattern CP by the undercut shape of the partition wall PW.

[0136] The dummy pattern DMP may define a dummy opening portion OP-D. The dummy opening portion OP-D may overlap with the light emitting opening portion OP-E. The dummy opening portion OP-D may include an area defined by the inner side surface S1-D of the first layer of dummy pattern D1 (hereinafter, the first dummy area), an area defined by the inner side surface S2-D of the second layer of dummy pattern D2 (hereinafter, the second dummy area), and an area defined by the inner side surface S3-D of the third layer of dummy pattern D3 (hereinafter, the third dummy area). On a plane, each of the first to third layers of dummy patterns D1, D2, and D3 may be a closed line shape surrounding the light emitting area PXA.

[0137] exist Figure 5The first to third layers of dummy patterns D1, D2, D3 are exemplarily shown as inner side surfaces aligned with the second inner side surface S2-P of the second partition layer L2, but are not limited thereto. The first to third layers of dummy patterns D1, D2, D3 may also cover the second inner side surface S2-P of the second partition layer L2.

[0138] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OL. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0139] The lower package inorganic pattern LIL may be overlapped with the light emitting opening OP-E. The lower package inorganic pattern LIL may cover the light emitting element ED and the dummy pattern DMP, and a portion thereof may be arranged inside the partition opening OP-P. According to one embodiment, the lower package inorganic pattern LIL may contact each of the first inner side surface S1-P of the first partition layer L1 and the second inner side surface S2-P of the second partition layer L2.

[0140] The encapsulation organic film OL may cover the lower encapsulation inorganic pattern LIL and provide a flat upper surface. The upper encapsulation inorganic film UIL may be disposed on the encapsulation organic film OL.

[0141] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL can protect the display element layer DP-OL from moisture / oxygen, and the encapsulation organic film OL can protect the display element layer DP-OL from foreign objects such as dust particles.

[0142] Figure 6 is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 6 It is along Figure 4 A cross-sectional view taken along the I-I' line. Figure 6 FIG. 1 is an enlarged view showing a first light emitting region PXA-R, a second light emitting region PXA-G, and a third light emitting region PXA-B. Figure 5 The description in the first light emitting region PXA may be equally applicable to each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B.

[0143] Reference Figure 6 According to the present embodiment, the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OL, and a thin film encapsulation layer TFE. The display element layer DP-OL may include light emitting elements ED1, ED2, ED3, sacrificial patterns SP1, SP2, SP3, a pixel defining film PDL, a partition wall PW, and dummy patterns DMP1, DMP2, DMP3.

[0144] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3. The first light-emitting element ED1 may include a first anode AE1, a first light-emitting pattern EP1, and a first cathode CE1. The second light-emitting element ED2 may include a second anode AE2, a second light-emitting pattern EP2, and a second cathode CE2. The third light-emitting element ED3 may include a third anode AE3, a third light-emitting pattern EP3, and a third cathode CE3. The first to third anodes AE1, AE2, and AE3 may be provided by a plurality of patterns. In one embodiment, the first light-emitting pattern EP1 may provide red light, the second light-emitting pattern EP2 may provide green light, and the third light-emitting pattern EP3 may provide blue light.

[0145] The pixel defining film PDL may define the first to third light emitting openings OP1-E, OP2-E, and OP3-E. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The first light emitting region PXA-R may be defined as a region on the top of the first anode AE1 that is exposed through the first light emitting opening OP1-E. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The second light emitting region PXA-G may be defined as a region on the top of the second anode AE2 that is exposed through the second light emitting opening OP2-E. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3. The third light emitting region PXA-B may be defined as a region on the top of the third anode AE3 that is exposed through the third light emitting opening OP3-E.

[0146] The sacrificial patterns SP1, SP2, SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, SP3 may be disposed on the first to third anodes AE1, AE2, AE3, respectively. The first to third sacrificial openings OP1-S, OP2-S, OP3-S corresponding to the first to third light emitting openings OP1-E, OP2-E, OP3-E, respectively, may be defined in the first to third sacrificial patterns SP1, SP2, SP3.

[0147] In this embodiment, first to third partition wall openings OP1-P, OP2-P, and OP3-P corresponding to the first to third light emitting openings OP1-E, OP2-E, and OP3-E, respectively, may be defined in the partition wall PW.

[0148] Each of the first to third partition wall openings OP1-P, OP2-P, and OP3-P may include Figure 5 The first area A1 (see Fig.11e ) and the second area A2 (refer to Fig.11eThe first partition layer L1 may include a first inner side surface S1-P (see FIG. 1 ) that defines a portion of a first area A1 of the first to third partition openings OP1-P, OP2-P, and OP3-P. Figure 5 The second partition layer L2 may include a second inner side surface S2-P (see FIG. 2 ) defining a second area A2 of the first to third partition openings OP1-P, OP2-P, and OP3-P. Figure 5 ).

[0149] The first light emitting pattern EP1 and the first cathode CE1 may be arranged in the first partition wall opening OP1-P, the second light emitting pattern EP2 and the second cathode CE2 may be arranged in the second partition wall opening OP2-P, and the third light emitting pattern EP3 and the third cathode CE3 may be arranged in the third partition wall opening OP3-P. The first to third cathodes CE1, CE2, CE3 may be in contact with the first inner side surface S1-P of the first partition wall layer L1, respectively.

[0150] In this embodiment, the first to third cathodes CE1, CE2, CE3 are physically separated by the second partition layer L2 forming the end TP and formed in each light-emitting opening OP1-E, OP2-E, OP3-E, and contact the first partition layer L1, so that they can be electrically connected to each other and receive a common voltage. The first partition layer L1 in contact has a relatively high conductivity compared to the second partition layer L2, so that each of the first to third cathodes CE1, CE2, CE3 can reduce the contact resistance with the first to third cathodes CE1, CE2, CE3. Thus, a common cathode voltage can be uniformly provided for the light-emitting regions PXA-R, PXA-G, PXA-B.

[0151] According to the present invention, the plurality of light emitting patterns EP1, EP2, EP3 are patterned and deposited in pixel units by defining the ends of the partition walls PW. That is, the plurality of light emitting patterns EP1, EP2, EP3 can be formed together using an open mask or easily divided in pixel units by the partition walls PW.

[0152] On the contrary, when a fine metal mask (FMM) is used to pattern a plurality of light-emitting patterns EP1, EP2, and EP3, a supporting spacer protruding from a conductive partition wall is provided to support the fine metal mask. In addition, as the fine metal mask separates the partition wall and the height of the spacer from the patterned base surface, the realization of high resolution may be limited. In addition, as the fine metal mask contacts the spacer, after the patterning process of the plurality of light-emitting patterns EP1, EP2, and EP3, foreign matter may remain on the spacer, or the spacer may be damaged by the imprint of the fine metal mask. As a result, a poor display panel may be formed.

[0153] According to this embodiment, the partition wall PW is included, so that the light emitting elements ED1, ED2, and ED3 can be easily physically separated, thereby preventing current leakage or driving errors between adjacent light emitting regions PXA-R, PXA-G, and PXA-B, and each light emitting element ED1, ED2, and ED3 can be driven independently.

[0154] In particular, there is no need to connect the display area DA (see Figure 1b ) by patterning a plurality of light emitting patterns EP1, EP2, EP3 using a mask that contacts the internal structure in the display panel DP, thereby providing a display panel DP with reduced defect rate and improved process reliability. Even without providing a separate supporting spacer protruding from the partition wall PW, as patterning is possible, it is possible to provide a display panel DP that can miniaturize the area of ​​the light emitting regions PXA-R, PXA-G, PXA-B and easily achieve high resolution.

[0155] In addition, when manufacturing a large-area display panel DP, by omitting the large-area mask manufacturing, it is possible to provide a display panel DP that can save process costs, is not affected by the adverse effects that may occur in the large-area mask, and improves process reliability.

[0156] The capping patterns CP1, CP2, CP3 may include a first capping pattern CP1, a second capping pattern CP2, and a third capping pattern CP3. The first to third capping patterns CP1, CP2, CP3 may be disposed on the first to third cathodes CE1, CE2, CE3, respectively, and disposed in the first to third partition openings OP1-P, OP2-P, OP3-P.

[0157] The dummy patterns DMP1, DMP2, DMP3 may include a first dummy pattern DMP1, a second dummy pattern DMP2, and a third dummy pattern DMP3. Each of the first dummy pattern DMP1, the second dummy pattern DMP2, and the third dummy pattern DMP3 may include a first layer dummy pattern D1a, D1b, D1c, a second layer dummy pattern D2a, D2b, D2c, and a third layer dummy pattern D3a, D3b, D3c.

[0158] The first dummy pattern DMP1 may include 1-1 to 3-1 dummy patterns D1a, D2a, D3a surrounding the first light emitting region PXA-R on a plane. The 1-1 dummy pattern D1a may include the same material as the first light emitting pattern EP1 and be formed by the same process as the first light emitting pattern EP1. The 2-1 dummy pattern D2a may include the same material as the first cathode CE1 and be formed by the same process as the first cathode CE1. The 3-1 dummy pattern D3a may include the same material as the first capping pattern CP1 and be formed by the same process as the first capping pattern CP1.

[0159] The second dummy pattern DMP2 may include 1-2 to 3-2 dummy patterns D1b, D2b, D3b surrounding the second light emitting region PXA-G on a plane. The 1-2 dummy pattern D1b may include the same material as the second light emitting pattern EP2 and be formed by the same process as the second light emitting pattern EP2. The 2-2 dummy pattern D2b may include the same material as the second cathode CE2 and be formed by the same process as the second cathode CE2. The 3-2 dummy pattern D3b may include the same material as the second capping pattern CP2 and be formed by the same process as the second capping pattern CP2.

[0160] The third dummy pattern DMP3 may include 1-3 to 3-3 dummy patterns D1c, D2c, D3c surrounding the third light emitting region PXA-B on a plane. The 1-3 dummy pattern D1c may include the same material as the third light emitting pattern EP3 and be formed by the same process as the third light emitting pattern EP3. The 2-3 dummy pattern D2c may include the same material as the third cathode CE3 and be formed by the same process as the third cathode CE3. The 3-3 dummy pattern D3c may include the same material as the third capping pattern CP3 and be formed by the same process as the third capping pattern CP3.

[0161] The dummy patterns DMP1, DMP2, and DMP3 may define first to third dummy openings OP1-D, OP2-D, and OP3-D that overlap the first to third light-emitting openings OP1-E, OP2-E, and OP3-E, respectively. The first dummy opening OP1-D may be defined by the inner side surfaces of the dummy patterns D1a, D2a, and D3a of the 1-1 to 3-1 layers, the second dummy opening OP2-D may be defined by the inner side surfaces of the dummy patterns D1b, D2b, and D3b of the 1-2 to 3-2 layers, and the third dummy opening OP3-D may be defined by the inner side surfaces of the dummy patterns D1c, D2c, and D3c of the 1-3 to 3-3 layers.

[0162] The thin film encapsulation layer TFE may include lower encapsulation inorganic patterns LIL1, LIL2, LIL3, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL. In the present embodiment, the lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may include a first lower encapsulation inorganic pattern LIL1, a second lower encapsulation inorganic pattern LIL2, and a third lower encapsulation inorganic pattern LIL3. The first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may correspond to the first to third light emitting openings OP1-E, OP2-E, OP3-E, respectively.

[0163] The first lower package inorganic pattern LIL1 may cover the first light emitting element ED1 and the 1-1 layer, 2-1 layer and 3-1 layer dummy patterns D1a, D2a, D3a, and a portion thereof may be arranged inside the first partition opening OP1-P. The second lower package inorganic pattern LIL2 may cover the second light emitting element ED2 and the 1-2 layer, 2-2 layer and 3-2 layer dummy patterns D1b, D2b, D3b, and a portion thereof may be arranged inside the second partition opening OP2-P. The third lower package inorganic pattern LIL3 may cover the third light emitting element ED3 and the 1-3 layer, 2-3 layer and 3-3 layer dummy patterns D1c, D2c, D3c, and a portion thereof may be arranged inside the third partition opening OP3-P. The first to third lower package inorganic patterns LIL1, LIL2, LIL3 may be provided in the form of patterns separated from each other.

[0164] Figure 7 is a plan view of a part of the structure of a display panel according to an embodiment of the present invention. Figure 8 It is along Figure 7 A cross-sectional view of a display panel according to an embodiment of the present invention is taken along line II-II'. Figure 7 1 is a plan view showing the partition wall PW, and for the convenience of explanation, the first to third light emitting regions PXA-R, PXA-G, and PXA-B are shown together.

[0165] Reference Figure 7 as well as Figure 8 , the next wall PW may define next wall openings OP1-P, OP2-P, OP3-P and an inspection opening OP-IN. In the present embodiment, the next wall PW may further define an inspection opening OP-IN. The next wall openings OP1-P, OP2-P, OP3-P may include a first next wall opening OP1-P overlapping the first light emitting region PXA-R, a second next wall opening OP2-P overlapping the second light emitting region PXA-G, and a third next wall opening OP3-P overlapping the third light emitting region PXA-B.

[0166] The inspection opening OP-IN may provide a space in which an inspection pattern INP described later may be arranged. The inspection opening OP-IN may be arranged apart from the first to third partition openings OP1-P, OP2-P, and OP3-P. The inspection opening OP-IN may not overlap with the first to third light emitting regions PXA-R, PXA-G, and PXA-B, but may overlap with the peripheral region NPXA.

[0167] In one embodiment, the inspection opening OP-IN may be provided in plurality. Figure 7It is exemplarily shown that the inspection opening OP-IN is configured between each first adjacent wall opening OP1-P (or, first light-emitting area PXA-R) and the third adjacent wall opening OP3-P (or, third light-emitting area PXA-B), and the position of the inspection opening OP-IN does not interfere with the adjacent wall openings OP1-P, OP2-P, OP3-P and can provide a space for configuring the inspection pattern INP, which is not limited to any one embodiment.

[0168] On the other hand, Figure 7 The inspection opening OP-IN is exemplarily shown to have a quadrangular shape in a plane, but the plane shape of the inspection opening OP-IN can provide a space in which the inspection pattern INP can be arranged, and is not limited to any one embodiment.

[0169] In this embodiment, the display panel DP may further include an inspection pattern INP. The inspection pattern INP may be disposed in the inspection opening OP-IN. According to this embodiment, one inspection pattern INP may be disposed in one inspection opening OP-IN. The inspection pattern INP may be used to distinguish whether the inspection pattern INP is formed to have a length d-TP within the required range of the end TP of the partition wall PW (refer to Figure 5 ). The detailed description thereof will be given later.

[0170] The inspection pattern INP may be rectangular in a plane. For example, the inspection pattern INP may be rectangular including short sides extending in a first direction DR1 and long sides extending in a second direction DR2 in a plane. However, the extending directions of the long sides and the short sides are not limited thereto.

[0171] exist Figure 8 A portion of the display panel DP corresponding to a portion defining one first partition wall opening OP1 -P and one inspection opening OP-IN in the partition wall PW is shown in an enlarged manner.

[0172] The inspection opening OP-IN may include a third area A3 (see Fig.11e ) and the fourth area A4 (refer to Fig.11e The first partition layer L1 may include a third region A3 defining the inspection opening OP-IN (see Fig.11e ) of the third inner side surface S3-P, the second partition layer L2 may include a fourth area A4 (refer to Fig.11e )'s fourth inner side surface S4-P.

[0173] In one embodiment, the inspection opening OP-IN may be formed simultaneously with at least one of the first to third adjacent wall openings OP1-P, OP2-P, and OP3-P. The first to third adjacent wall openings OP1-P, OP2-P, and OP3-P may also be formed by different etching processes, in which case the inspection opening OP-IN may be formed simultaneously with any one of the first to third adjacent wall openings OP1-P, OP2-P, and OP3-P. Alternatively, all of the first to third adjacent wall openings OP1-P, OP2-P, and OP3-P may also be formed by the same etching process, in which case the inspection opening OP-IN may also be formed simultaneously with all of the first to third adjacent wall openings OP1-P, OP2-P, and OP3-P.

[0174] In one embodiment, an additional end TP-A may be defined in the partition wall PW. The additional end TP-A may be defined as a portion of the second partition wall layer L2 that protrudes from the first partition wall layer L1 toward the inspection pattern INP. The third inner side surface S3-P of the first partition wall layer L1 may be relatively recessed inwardly than the fourth inner side surface S4-P of the second partition wall layer L2. In a plane, the fourth inner side surface S4-P protrudes compared to the third inner side surface S3-P and may be adjacent to the inspection pattern INP in a plane.

[0175] However, the inspection opening OP-IN is not limited thereto and may be connected to the first to third partition openings OP1-P, OP2-P, OP3-P (see Figure 6 In this case, the fourth inner side surface S4-P may not be protruding compared to the third inner side surface S3-P, and the third and fourth inner side surfaces S3-P and S4-P may also be substantially aligned.

[0176] The inspection pattern INP may be disposed on the pixel defining layer PDL. The inspection pattern INP may include the same material as the first partition wall layer L1 of the partition wall PW. The inspection pattern INP may be formed during the process of forming the first partition wall layer L1. In one embodiment, the inspection pattern INP may have substantially the same height as the first partition wall layer L1.

[0177] The inspection pattern INP may be covered by the thin film encapsulation layer TFE. The inspection pattern INP may be in contact with the encapsulation organic film OL.

[0178] The inspection pattern INP may be derived from two or more initial inspection patterns INP-P (refer to Fig.11c ) After the undercut etching process, only one initial inspection pattern remains. In the cross section, more than two initial inspection patterns INP-P (refer to Fig.11c ) may have different widths from each other in a direction (eg, a first direction DR1). After the undercut etching process, the initial inspection pattern INP-P (refer to Fig.11c) is removed and / or remains to determine whether the end portion TP of the partition wall PW is formed to have a length d-TP within the required range (refer to Figure 5 ). The detailed description thereof will be given later.

[0179] Fig. 9 It is along Figure 7 A cross-sectional view of a display panel according to an embodiment of the present invention taken along line II-II'. Fig. 9 When, refer to Figures 1a to 8 The same or similar components will be described using the same or similar reference numerals, and duplicate description will be omitted.

[0180] According to the present embodiment, two inspection patterns INP' may be arranged in one inspection opening OP-IN. The inspection pattern INP' may include a first inspection pattern INP1' and a second inspection pattern INP2'. In a cross section, the width of the first inspection pattern INP1' in one direction (e.g., the first direction DR1) may be different from the width of the second inspection pattern INP2' in one direction (e.g., the first direction DR1).

[0181] The first and second inspection patterns INP1' and INP2' can be selected from three or more initial inspection patterns INP-P' (refer to Figure 12b ) After the undercut etching process, two inspection patterns INP' remain. In the cross section, more than three initial inspection patterns INP-P' (refer to Figure 12b ) may have different widths from each other in a direction (eg, a first direction DR1). After the undercut etching process, the initial inspection pattern INP-P′ (refer to Figure 12b ) is removed and / or remains, and whether it is formed to have a length d-TP within the required range of the end TP of the partition wall PW (refer to Figure 5 ). The detailed description thereof will be given later.

[0182] Fig.10 is a flow chart showing a method for manufacturing a display panel according to an embodiment of the present invention. Figures 11a to 11e FIG. 1 is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 11a to 11e When, refer to Figures 1a to 8 The same or similar components will be described using the same or similar reference numerals, and duplicate description will be omitted.

[0183] According to an embodiment of the present invention, the display panel manufacturing method may include forming a partition wall PW (refer to Fig.11e ) and check the formed next wall PW (refer to Fig.11e ) end TP (refer to Fig.11e) steps. Fig.10 According to an embodiment of the present invention, a display panel manufacturing method may include a step of forming a preliminary partition wall (S100), a step of forming a photoresist layer (S200), a step of performing a first etching on the preliminary partition wall (S300), a step of performing a second etching on the preliminary partition wall to form a partition wall (S400), and a step of inspecting an end portion of the partition wall (S500).

[0184] like Fig.10 as well as Fig.11a As shown, the method for manufacturing a display panel according to the present embodiment may include a step of forming a preliminary partition wall PW-I ( S100 ).

[0185] The preliminary partition wall PW-I may be formed on the preliminary display panel DP-I. The preliminary display panel DP-I provided in this embodiment may include a base layer BL, a circuit element layer DP-CL, an anode AE, a preliminary sacrificial pattern SP-I, and a preliminary pixel defining layer PDL-I.

[0186] The circuit element layer DP-CL can form an insulating layer, a semiconductor layer and a conductive layer by coating, evaporation, etc., and selectively pattern the insulating layer, the semiconductor layer and the conductive layer by photolithography technology and etching process, thereby forming a common circuit element manufacturing process such as forming a semiconductor pattern, a conductive pattern and a signal line.

[0187] The anode AE ​​and the preliminary sacrificial pattern SP-I may be formed by the same patterning process. The preliminary pixel defining film PDL-I may completely cover the anode AE ​​and the preliminary sacrificial pattern SP-I. The preliminary pixel defining film PDL-I may define the above-mentioned pixel opening OP-E (refer to Figure 5 The preliminary sacrificial pattern SP-I may be a state before defining the sacrificial opening OP-S (refer to Figure 5 ) before. Fig.11a The anode AE ​​shown can be connected with Figure 6 The above-mentioned first to third anodes AE1, AE2, AE3 correspond to any one of them. Fig.11a The preparatory sacrificial pattern SP-I shown may be defined in Figure 6 The state before the sacrificial opening portions OP1-S, OP2-S, OP3-S corresponding to any one of the above-mentioned first to third sacrificial patterns SP1, SP2, SP3.

[0188] The step of forming the preliminary partition wall PW-I may include the step of forming a first preliminary partition wall layer L1-I and the step of forming a second preliminary partition wall layer L2-I.

[0189] The first preliminary partition layer L1-I can be formed on the preliminary pixel definition film PDL-I. The step of forming the first preliminary partition layer L1-I can be performed by an evaporation process of a conductive material. For example, the conductive material forming the first preliminary partition layer L1-I may include a metal, a metal nitride, a transparent conductive oxide (Transparent Conductive Oxide, TCO) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (IGZO) or aluminum zinc oxide (Aluminum Zinc Oxide).

[0190] The second preliminary partition layer L2-I can be formed on the first preliminary partition layer L1-I. In one embodiment, the step of forming the second preliminary partition layer L2-I can be performed by an evaporation process of a conductive material. For example, the conductive material forming the second preliminary partition layer L2-I may include a metal, a metal nitride, a transparent conductive oxide (Transparent Conductive Oxide, TCO) or a combination thereof. The metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy. The metal nitride may include titanium nitride (TiN). The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (IndiumGallium Oxide), indium gallium zinc oxide (IGZO) or aluminum zinc oxide (Aluminum Zinc Oxide).

[0191] Alternatively, in another embodiment of the present invention, the second preliminary partition layer L2-I may not include a metal substance, and the second preliminary partition layer L2-I may include an inorganic insulating substance. In this case, the step of forming the second preliminary partition layer L2-I may be performed by a vapor deposition process of an inorganic insulating substance. For example, the second preliminary partition layer L2-I may be formed of a silicon compound. For example, the second preliminary partition layer L2-I may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y )

[0192] As an example, the conductive material forming the first preliminary barrier rib layer L1-I may be aluminum (Al), and the conductive material forming the second preliminary barrier rib layer L2-I may be titanium (Ti).

[0193] The formed preliminary bank PW-I may include a first preliminary bank layer L1-I and a second preliminary bank layer L2-I.

[0194] Afterwards, refer to Fig.10 as well as Fig.11b , the display panel manufacturing method according to the present embodiment may include a step of forming a photoresist layer PRL ( S200 ).

[0195] The photoresist layer PRL may be formed on the preliminary partition wall PW-I. The photoresist layer PRL may be formed by patterning the preliminary photoresist layer using a photomask after forming the preliminary photoresist layer on the preliminary partition wall PW-I. Through the patterning process, a photoresist layer PRL including a first photolithography pattern PR1 and a second photolithography pattern PR2 may be formed. The first photolithography pattern PR1 may define a first photolithography opening OP1-PR and a second photolithography opening OP2-PR. The first photolithography opening OP1-PR may overlap with the anode AE. The second photolithography opening OP2-PR may not overlap with the anode AE.

[0196] exist Fig.11b In the figure, only one first photolithography opening OP1-PR overlapping with one anode AE ​​is exemplarily shown. In one embodiment, a plurality of first photolithography openings OP1-PR are provided. The first photolithography openings OP1-PR can be configured to overlap with the first anode AE1 (see Figure 6 ), the second anode AE2 (refer to Figure 6 ) or the third anode AE3 (refer to Figure 6 Alternatively, in another embodiment of the present invention, the first photolithography openings OP1-PR may also be configured to overlap with the first anode AE1 (see Figure 6 ), the second anode AE2 (refer to Figure 6) or the third anode AE3 (refer to Figure 6 ) all overlap.

[0197] The second photolithography pattern PR2 may be disposed in the second photolithography opening OP2-PR. In this embodiment, the second photolithography pattern PR2 may include a 2-1st photolithography pattern PR2a and a 2-2nd photolithography pattern PR2b. That is, the second photolithography pattern PR2 is provided as two patterns in one second photolithography opening OP2-PR.

[0198] In the cross section, the width of the 2-1st photolithography pattern PR2a in a direction (e.g., the first direction DR1) may be different from the width of the 2-2nd photolithography pattern PR2b in a direction (e.g., the first direction DR1). For example, in the cross section, the width of the 2-2nd photolithography pattern PR2b in the first direction DR1 may be greater than the width of the 2-1st photolithography pattern PR2a in the first direction DR1.

[0199] Afterwards, refer to Fig.10 , Figure 11c to Figure 11e According to the display panel manufacturing method of the present embodiment, the step of etching the preliminary partition wall PW-I so that the partition wall PW is formed from the preliminary partition wall PW-I may be performed twice. The step of etching the preliminary partition wall PW-I may include a step of etching the preliminary partition wall PW-I once (S300) and a step of etching the preliminary partition wall PW-I twice (S400).

[0200] First, refer to Fig.10 as well as Fig.11c , the step (S300) of etching the preliminary partition wall PW-I once may include the step of using the photoresist layer PRL as a mask and dry etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I. By etching the preliminary partition wall PW-I once (S300), a preliminary partition wall opening OP-PI and a preliminary inspection opening OP-INI may be formed in the preliminary partition wall PW-I. The preliminary partition wall opening OP-PI may be formed by the first photolithography opening OP1-PR, and the preliminary inspection opening OP-INI may be formed by the second photolithography opening OP2-PR. The preliminary partition wall opening OP-PI may be defined by the first inner side surface S1-PI of the first preliminary partition wall layer L1-I and the second inner side surface S2-PI of the second preliminary partition wall layer L2-I. The preliminary inspection opening OP-INI may be defined by the third inner side surface S3-PI of the first preliminary partition wall layer L1-I and the fourth inner side surface S4-PI of the second preliminary partition wall layer L2-I.

[0201] The dry etching process in the present embodiment can be formed under an etching environment in which the etching selectivity between the first preliminary partition layer L1-I and the second preliminary partition layer L2-I is substantially the same. Thus, the first inner side surface S1-PI of the first preliminary partition layer L1-I and the second inner side surface S2-PI of the second preliminary partition layer L2-I can be substantially aligned. The second inner side surface S2-PI of the second preliminary partition layer L2-I may not protrude compared to the first inner side surface S1-PI of the first preliminary partition layer L1-I. In addition, the third inner side surface S3-PI of the first preliminary partition layer L1-I and the fourth inner side surface S4-PI of the second preliminary partition layer L2-I can be substantially aligned. The fourth inner side surface S4-PI of the second preliminary partition layer L2-I may not protrude compared to the third inner side surface S3-PI of the first preliminary partition layer L1-I.

[0202] In the step (S300) of etching the preliminary partition wall PW-I once according to the present embodiment, the initial inspection pattern INP-P may be formed together. The initial inspection pattern INP-P may be formed by patterning a portion of the preliminary partition wall PW-I. The initial inspection pattern INP-P may be formed in the preliminary inspection opening OP-INI.

[0203] In this embodiment, the preliminary inspection pattern INP-P may include a first preliminary inspection pattern INP1-P and a second preliminary inspection pattern INP2-P. The first preliminary inspection pattern INP1-P may be formed by a 2-1st photolithography pattern PR2a, and the second preliminary inspection pattern INP2-P may be formed by a 2-2nd photolithography pattern PR2b.

[0204] Each of the first and second initial inspection patterns INP1-P, INP2-P may include a first initial inspection pattern layer L1p1, L1p2 and a second initial inspection pattern layer L2p1, L2p2. The first initial inspection pattern layer L1p1, L1p2 of the first and second initial inspection patterns INP1-P, INP2-P may be formed by patterning a portion of the first preliminary partition layer L1-I. That is, the first initial inspection pattern layer L1p1, L1p2 may include the same substance as the first preliminary partition layer L1-I. The second initial inspection pattern layer L2p1, L2p2 of the first and second initial inspection patterns INP1-P, INP2-P may be formed from the second preliminary partition layer L2-I. That is, the second initial inspection pattern layer L2p1, L2p2 may include the same substance as the second preliminary partition layer L2-I.

[0205] In cross section, the first initial inspection pattern INP1-P may have a first initial width w1-P in a direction (e.g., the first direction DR1), and the second initial inspection pattern INP2-P may have a second initial width w2-P in a direction (e.g., the first direction DR1). The first initial width w1-P and the second initial width w2-P may be different. For example, the second initial width w2-P may be greater than the first initial width w1-P. Each of the first and second initial widths w1-P, w2-P may be defined based on the bottom of the first initial inspection pattern layer L1p1, L1p2.

[0206] Afterwards, refer to Fig.10 , Fig.11d as well as Fig.11e , the step (S400) of etching the preliminary partition wall PW-I twice may include the step of using the photoresist layer PRL as a mask and wet etching the first preliminary partition wall layer L1-I. By etching the preliminary partition wall PW-I twice (S400), the partition wall PW can be formed from the preliminary partition wall PW-I. On the other hand, in this specification, the step (S400) of etching the preliminary partition wall PW-I twice may be referred to as a "undercut etching process".

[0207] In one embodiment, the step of etching the preliminary partition wall PW-I twice (S400) may include providing a chemical solution EC to the preliminary partition wall PW-I defining the preliminary partition wall opening OP-PI and the preliminary inspection opening OP-INI, thereby etching the first preliminary partition wall layer L1-I. On the other hand, in this specification, the chemical solution EC may refer to a processing liquid used in an etching process in a manufacturing process of a display panel.

[0208] The wet etching process in this embodiment can be formed under an environment where the etching selectivity ratio between the first preliminary partition layer L1-I and the second preliminary partition layer L2-I is large. In the undercut etching process, the etching rate of the first preliminary partition layer L1-I can be greater than the etching rate of the second preliminary partition layer L2-I.

[0209] The first preliminary partition wall layer L1-I may be etched to a greater extent than the second preliminary partition wall layer L2-I. Thus, in the step of etching the preliminary partition wall PW-I twice, only the first preliminary partition wall layer L1-I may be etched, and the second preliminary partition wall layer L2-I may not be etched or substantially not etched.

[0210] In the step (S400) of etching the preliminary partition wall PW-I twice, a partition wall PW including a first partition wall layer L1 and a second partition wall layer L2 may be formed. A partition wall opening OP-P and an inspection opening OP-IN may be formed in the partition wall PW. The partition wall opening OP-P may be formed from the preliminary partition wall opening OP-PI of the preliminary partition wall PW-I, and the inspection opening OP-IN may be formed from the preliminary inspection opening OP-INI of the preliminary partition wall PW-I.

[0211] The inner side surface of the partition wall PW defining the partition wall opening OP-P may have an undercut shape in cross section. The first inner side surface S1-P of the first partition wall layer L1 may be formed to be more recessed inwardly than the second inner side surface S2-P of the second partition wall layer L2. An end TP may be formed in the partition wall PW by a portion protruding toward the center direction of the anode AE ​​compared to the first partition wall layer L1 in the second partition wall layer L2.

[0212] The next-wall opening OP-P may include a first region A1 and a second region A2 sequentially arranged in the thickness direction (i.e., the third direction DR3). It may be that the first region A1 of the next-wall opening OP-P is defined by the first inner side S1-P of the first next-wall layer L1, and the second region A2 is defined by the second inner side S2-P of the second next-wall layer L2. In cross section, the width w-A2 of the second region A2 in one direction may be less than the width w-A1 of the first region A1 in one direction. The inner side of the next-wall PW defining the inspection opening OP-IN may have an undercut shape in cross section. The third inner side S3-P of the first next-wall layer L1 may be formed to be more recessed inwardly than the fourth inner side S4-P of the second next-wall layer L2. An additional end TP-A may be formed in the next-wall PW by a portion protruding toward the inspection pattern INP compared to the first next-wall layer L1 in the second next-wall layer L2.

[0213] The inspection opening OP-IN may include a third region A3 and a fourth region A4 sequentially arranged in the thickness direction (i.e., the third direction DR3). The third region A3 of the inspection opening OP-IN may be defined by the third inner side surface S3-P of the first partition layer L1, and the fourth region A4 may be defined by the fourth inner side surface S4-P of the second partition layer L2. In cross section, the fourth region A4 may have a narrower width than the third region A3.

[0214] In the step (S400) of etching the preliminary partition wall PW-I twice according to the present embodiment, the inspection pattern INP can be formed from the initial inspection pattern INP-P. The wet etching process in the present embodiment can be formed under an environment where the etching selectivity between the first initial inspection pattern layer L1p1, L1p2 and the second initial inspection pattern layer L2p1, L2p2 is large. The etching rate of the first initial inspection pattern layer L1p1, L1p2 can be greater than the etching rate of the second initial inspection pattern layer L2p1, L2p2.

[0215] In the step (S400) of etching the preliminary partition wall PW-I twice, the first preliminary inspection pattern INP1-P can be removed. The first preliminary inspection pattern layer L1p1 of the first preliminary inspection pattern INP1-P is removed by etching, thereby, the second preliminary inspection pattern layer L2p1 of the first preliminary inspection pattern INP1-P and the 2-1st photolithography pattern PR2a can be removed from the preliminary display panel DP-I (refer to Fig.11a ) are separated and removed.

[0216] In the step (S400) of etching the preliminary partition wall PW-I twice, the inspection pattern INP can be formed from the second initial inspection pattern INP2-P. In the step (S400) of etching the preliminary partition wall PW-I twice, a portion of the first initial inspection pattern layer L1p2 in the second initial inspection pattern INP2-P is etched, and the second initial inspection pattern layer L2p2 in the second initial inspection pattern INP2-P is removed from the first initial inspection pattern layer L1p2, thereby forming the inspection pattern INP. The first initial inspection pattern layer L1p2 can be etched to have a narrow width, and the second initial inspection pattern layer L2p2 reduces the adhesive force with the etched first initial inspection pattern layer L1p2 and detaches from and is removed from the etched first initial inspection pattern layer L1p2. The inspection pattern INP can be arranged in the third area A3 of the inspection opening OP-IN.

[0217] Afterwards, the display panel manufacturing method according to the present embodiment may include a step of inspecting the end TP of the partition wall PW (S500). The end TP of the partition wall PW can be inspected by the inspection pattern INP. More specifically, by understanding the etching degree of the first initial inspection pattern layer L1p1, L1p2, it can be determined whether the end TP is formed to have a length d-TP within the required range (refer to Figure 5 ).

[0218] The lower limit value of the width of the first preliminary partition layer L1-I etched in the step (S400) of etching the preliminary partition wall PW-I twice can be predicted by removing the first initial inspection pattern INP1-P in the step (S400) of etching the preliminary partition wall PW-I twice. In the present specification, the width of the first preliminary partition layer L1-I etched in the step (S400) of etching the preliminary partition wall PW-I twice can correspond to the degree of depression from the first inner side surface S1-PI of the first preliminary partition layer L1-I before the step (S400) of etching the preliminary partition wall PW-I twice to the first inner side surface S1-P of the first partition layer L1 after the step (S400) of etching the preliminary partition wall PW-I twice.

[0219] The width of the first preliminary partition wall layer L1-I etched in the step (S400) of etching the preliminary partition wall PW-I twice may be more than half the width w1-P of the first initial inspection pattern INP1-P. The length d-TP (refer to Figure 5 ). Therefore, the length d-TP of the end TP formed at the partition wall PW can be predicted by the width w1-P of the first initial inspection pattern INP1-P (refer to Figure 5 ) is the lower limit of the length of the end TP d-TP (refer to Figure 5 ) can be predicted to be more than half of the width w1-P of the first initial inspection pattern INP1-P. Therefore, according to this embodiment, when the end TP is required to have a length above a certain level, it is convenient to confirm whether the end TP has a length above a certain level by whether the first initial inspection pattern INP1-P is removed.

[0220] In addition, the upper limit value of the width of the first preliminary partition layer L1-I etched in the step (S400) of etching the preliminary partition PW-I twice can be predicted by the second initial inspection pattern INP2-P remaining in the step (S400) of etching the preliminary partition PW-I twice.

[0221] In the step (S400) of etching the preliminary partition wall PW-I twice, the width of the first preliminary partition wall layer L1-I etched may be less than half of the width w2-P of the second initial inspection pattern INP2-P. Therefore, the length d-TP of the end TP formed at the partition wall PW can be predicted by the width w2-P of the second initial inspection pattern INP2-P (refer to Figure 5 ) is the upper limit value. The length d-TP of the end TP (refer to Figure 5) can be predicted to be less than half of the width w2-P of the second initial inspection pattern INP2-P. Therefore, according to this embodiment, when the end TP is required to have a length less than a certain level, it is convenient to confirm whether the end TP has a length less than a certain level by whether the second initial inspection pattern INP2-P remains.

[0222] By confirming whether the initial inspection pattern INP-P is removed or remains, it can be determined whether the end portion TP is formed to have a length d-TP within the required range (refer to Figure 5 ). Whether the initial inspection pattern INP-P is removed or remains can be identified by optical inspection, so it is convenient to inspect without destroying the resultant object.

[0223] According to one embodiment, the width of the first preliminary partition layer L1-I etched in the step (S400) of etching the preliminary partition PW-I twice can be confirmed by the second initial inspection pattern INP2-P and the inspection pattern INP. The width of the first preliminary partition layer L1-I etched in the step (S400) of etching the preliminary partition PW-I twice can be determined to be substantially the same as the value obtained by subtracting the width w-INP of the inspection pattern INP from the second initial width w2-P of the second initial inspection pattern INP2-P. By this, the length d-TP (refer to Figure 5 ). The length of the end TP is d-TP (refer to Figure 5 ) can be judged to be substantially the same as half of the value obtained by subtracting the width w-INP of the inspection pattern INP from the second initial width w2-P of the second initial inspection pattern INP2-P.

[0224] As the inspection pattern INP only has a portion of the first initial inspection pattern layer L1p2 remaining, it can be provided as a single layer, and as the second initial inspection pattern layer L2p2 is removed, the end portion may not be included. Thus, it is convenient to inspect the width of the first preliminary partition layer L1-I etched by the optical inspection device, so as not to destroy the formed result and confirm the length d-TP of the end portion TP (refer to Figure 5 In one embodiment, the width of the etched first preliminary partition layer L1-I may be measured by an optical instrument (eg, CD-METER).

[0225] On the other hand, the second partition layer L2 of the partition wall PW may include a conductive material (eg, metal). Since light cannot pass through the second partition layer L2, it is difficult to directly measure the length d-TP of the end TP using an optical instrument (refer to Figure 5 ). In addition, the partition wall PW has an undercut shape, so it is difficult to directly measure the length d-TP of the end TP using an atomic force microscope (AFM) (refer to Figure 5). Therefore, unlike the present embodiment, when the inspection pattern is not formed, it may be difficult to measure the length d-TP of the end portion TP without cutting the partition wall PW (refer to Figure 5 ).

[0226] Figures 12a to 12c FIG. 1 is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 12a to 12c When, refer to Figures 1a to 9 The same or similar components will be described using the same or similar reference numerals, and duplicate description will be omitted.

[0227] Reference Fig.10 as well as Fig.12a , the display panel manufacturing method according to the present embodiment may include the step of forming a photoresist layer PRL' (S200). The photoresist layer PRL' according to the present embodiment may include a first photoresist pattern PR1' and a second photoresist pattern PR2', and the second photoresist pattern PR2' may include a 2-1st photoresist pattern PR2a', a 2-2nd photoresist pattern PR2b', and a 2-3rd photoresist pattern PR2c'. That is, in the present embodiment, the second photoresist pattern PR2' may be provided as three patterns within one second photoresist opening OP2-PR.

[0228] In the cross section, the width of the 2-1st photolithography pattern PR2a' in one direction (e.g., the first direction DR1), the width of the 2-2nd photolithography pattern PR2b' in one direction (e.g., the first direction DR1), and the width of the 2-3rd photolithography pattern PR2c' in one direction (e.g., the first direction DR1) may be different from each other. For example, in the cross section, the width of the 2-2nd photolithography pattern PR2b' in the first direction DR1 may be greater than the width of the 2-1st photolithography pattern PR2a' in the first direction DR1, and smaller than the width of the 2-3rd photolithography pattern PR2c' in the first direction DR1.

[0229] Reference Fig.10 as well as Figure 12b The display panel manufacturing method according to the present embodiment may include a step of etching the preliminary partition wall PW-I once (S300).

[0230] In the step (S300) of etching the preliminary partition wall PW-I once according to the present embodiment, an initial inspection pattern INP-P' may be formed together. In the present embodiment, the initial inspection pattern INP-P' may include a first initial inspection pattern INP1-P', a second initial inspection pattern INP2-P', and a third initial inspection pattern INP3-P'. That is, three initial inspection patterns may be formed in the present embodiment. The first to third initial inspection patterns INP1-P', INP2-P', and INP3-P' may be formed by the 2-1st to 2-3rd photolithography patterns PR2a', PR2b', and PR2c', respectively.

[0231] Each of the first to third initial inspection patterns INP1-P', INP2-P', INP3-P' may include a first initial inspection pattern layer L1p1', L1p2', L1p3' and a second initial inspection pattern layer L2p1', L2p2', L2p3'. The first initial inspection pattern layer L1p1', L1p2', L1p3' may be formed by patterning a portion of the first preliminary partition layer L1-I. The second initial inspection pattern layer L2p1', L2p2', L2p3' may be formed from the second preliminary partition layer L2-I.

[0232] In cross section, the first to third initial inspection patterns INP1-P', INP2-P', INP3-P' may have first to third initial widths w1-P', w2-P', w3-P' in a direction (e.g., first direction DR1), respectively. The first to third initial widths w1-P', w2-P', w3-P' may be different from each other. For example, the second initial width w2-P' may be greater than the first initial width w1-P' and less than the third initial width w3-P'. Figure 12b The difference between the first and second initial widths w1-P', w2-P', and the difference between the second and third initial widths w2-P', w3-P' may be smaller than that in Fig.11c The difference between the first and second initial widths w1-P and w2-P.

[0233] Reference Fig.10 , Figure 12b as well as Fig.12c The display panel manufacturing method according to the present embodiment may include a step of etching the preliminary partition wall PW-I twice (S400) and a step of inspecting the end portion TP of the partition wall PW (S500).

[0234] In the step (S400) of etching the preliminary wall PW-I twice according to the present embodiment, the inspection pattern INP' can be formed from the initial inspection pattern INP-P'. In one embodiment, the first initial inspection pattern INP1-P' is removed, and the second and third initial inspection patterns INP2-P' and INP3-P' remain. By this, in the step (S500) of inspecting the end TP of the wall PW, the length d-TP of the end TP (refer to Figure 5 ) can be predicted to be more than half of the width w1-P' of the first initial inspection pattern INP1-P'. In addition, in the step (S500) of inspecting the end TP of the partition wall PW, the length d-TP of the end TP (refer to Figure 5 ) can be predicted to be smaller than half of the width w2-P' of the second initial inspection pattern INP2-P'.

[0235] In addition, the length d-TP of the end TP can be predicted by the difference between the width w2-P' of the second initial inspection pattern INP2-P' and the width w-INP1' of the first inspection pattern INP1' and the difference between the width w3-P' of the third initial inspection pattern INP3-P' and the width w-INP2' of the second inspection pattern INP2' (see Figure 5 ).

[0236] In this embodiment, three or more initial inspection patterns (INP-P') are provided, which is different from providing two initial inspection patterns INP-P (see Fig.11c ) can more accurately predict the length d-TP of the end TP (refer to Figure 5 ).

[0237] Fig.13 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present invention. Fig.14 is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Fig.15a is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Fig.15b FIG. 1 is a plan view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Fig.16a is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Fig.16b FIG. 1 is a plan view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Figure 13 to Figure 16b When, refer to Figures 1a to 12c The same or similar components will be described using the same or similar reference numerals, and duplicate description will be omitted.

[0238] According to an embodiment of the present invention, the display panel manufacturing method may include forming a partition wall PW (refer to Fig.11e ) before the next PW (refer to Fig.11e ) end TP (refer to Fig.11e ) length steps. Fig.13 According to an embodiment of the present invention, a display panel manufacturing method may include a step of forming a preliminary measurement pattern (S10), a step of forming a photoresist layer for measurement (S20), a step of etching the preliminary measurement pattern to form an initial measurement pattern (S30), a step of etching the initial measurement pattern to form a measurement pattern (S40), and a step of predicting the length of an end portion (S50).

[0239] Reference Fig.14 The display panel manufacturing method according to the present embodiment may include a step of forming a preliminary measurement pattern MSP-I (S10). The preliminary measurement pattern MSP-I may be formed on a measurement substrate BS.

[0240] The step of forming the preliminary measurement pattern MSP-I may include the step of forming a first preliminary measurement layer ML1-I on the measurement substrate BS and the step of forming a second preliminary measurement layer ML2-I on the first preliminary measurement layer ML1-I. The preliminary measurement pattern MSP-I may include the first preliminary measurement layer ML1-I and the second preliminary measurement layer ML2-I.

[0241] The first preliminary measurement layer ML1-I may include the partition wall PW to be manufactured (refer to Fig.11e ) of the first partition layer L1 (refer to Fig.11e ) of the same material. The step of forming the first preliminary measurement layer ML1-I takes into account the first partition layer L1 to be manufactured (refer to Fig.11e ) can be used in the step of forming the first preliminary partition layer L1-I (refer to Fig.11b ) is performed by the same type of evaporation process as in the evaporation process of ). In addition, the first preliminary measurement layer ML1-I can be formed to have the same thickness as the first partition layer L1 to be manufactured (refer to Fig.11e ) have substantially the same thickness.

[0242] The second preliminary measurement layer ML2-I may include the partition wall PW to be manufactured (refer to Fig.11e ) of the second partition layer L2 (refer to Fig.11e The step of forming the second preliminary measurement layer ML2-I takes into account the second partition layer L2 (refer to Fig.11e ) can be used in the step of forming the second preliminary partition layer L2-I (refer to Fig.11b) is performed by the same type of evaporation process as the evaporation process in ). In addition, the second preliminary measurement layer ML2-I can be formed to have the same thickness as the second partition layer L2 to be manufactured (refer to Fig.11e ) have substantially the same thickness.

[0243] Thereafter, the display panel manufacturing method according to the present embodiment may include a step of forming a measurement photoresist layer PRLm ( S20 ).

[0244] The measurement photoresist layer PRLm may be formed on the preliminary measurement pattern MSP-I. The measurement photoresist layer PRLm may be formed by patterning the preliminary photoresist layer using a photomask after forming the preliminary photoresist layer on the preliminary measurement pattern MSP-I. Through the patterning process, the measurement photoresist layer PRLm including a plurality of measurement photoresist patterns may be formed.

[0245] exist Fig.14 The exemplary measurement photolithography pattern includes seven photolithography patterns (hereinafter referred to as the first, second, third, fourth, fifth, sixth and seventh measurement photolithography patterns P1m, P2m, P3m, P4m, P5m, P6m, P7m). In the cross section, the widths of the first to seventh measurement photolithography patterns P1m, P2m, P3m, P4m, P5m, P6m, P7m in the first direction DR1 may be different from each other. For example, the first to seventh measurement photolithography patterns P1m, P2m, P3m, P4m, P5m, P6m, P7m may be formed in a manner that the widths in the first direction DR1 increase from the first measurement photolithography pattern P1m to the seventh measurement photolithography pattern P7m in the cross section.

[0246] Afterwards, refer to Figure 14 to Figure 15b The display panel manufacturing method according to the present embodiment may include a step (S30) of etching the preliminary measurement pattern MSP-I so that the initial measurement pattern MSP-P is formed from the preliminary measurement pattern MSP-I. Fig.15b is a plan view showing the initial measurement pattern MSP-P.

[0247] The step of etching the preliminary measurement pattern MSP-I (S30) may include the step of using the measurement photoresist layer PRLm as a mask and dry etching the first preliminary measurement layer ML1-I and the second preliminary measurement layer ML2-I. The step of etching the preliminary measurement pattern MSP-I (S30) may be performed at the same time as the step of etching the preliminary measurement pattern MSP-I on the partition wall PW (refer to Fig.11e )Preparatory partition PW-I to be made during manufacturing (refer to Fig.11c ) performs one etching step S300 (refer to Fig.10) is performed similarly. For example, in the step (S30) of etching the preliminary measurement pattern MSP-I, a pattern similar to that to be provided on the preliminary partition wall PW-I (refer to Fig.11c ) performs one etching step S300 (refer to Fig.10 ) is manufactured under the same etching conditions (e.g., the injected gas, the time of gas injection, etc.).

[0248] By etching the preliminary measurement pattern MSP-I (S30), a plurality of initial measurement patterns MSP-P may be formed, and the plurality of initial measurement patterns MSP-P may include first, second, third, fourth, fifth, sixth and seventh initial measurement patterns A1, A2, A3, A4, A5, A6, A7. The first to seventh initial measurement patterns A1, A2, A3, A4, A5, A6, A7 may be formed from the first to seventh measurement photolithography patterns P1m, P2m, P3m, P4m, P5m, P6m, P7m, respectively.

[0249] Each of the first to seventh initial measurement patterns A1, A2, A3, A4, A5, A6, A7 may include a first initial measurement layer 11, 12, 13, 14, 15, 16, 17 and a second initial measurement layer 21, 22, 23, 24, 25, 26, 27. The first initial measurement layers 11, 12, 13, 14, 15, 16, 17 may be formed by patterning the first preliminary measurement layer ML1-I, and the second initial measurement layers 21, 22, 23, 24, 25, 26, 27 may be formed by patterning the second preliminary measurement layer ML2-I.

[0250] The step (S30) of etching the preliminary measurement pattern MSP-I may be formed under an etching environment in which the etching selectivity between the first preliminary measurement layer ML1-I and the second preliminary measurement layer ML2-I is substantially the same. Thus, in each of the first to seventh preliminary measurement patterns A1, A2, A3, A4, A5, A6, A7, the outer side surface of the first preliminary measurement layer 11, 12, 13, 14, 15, 16, 17 may be substantially aligned with the outer side surface of the second preliminary measurement layer 21, 22, 23, 24, 25, 26, 27. The outer side surface of the second preliminary measurement layer 21, 22, 23, 24, 25, 26, 27 may not protrude compared to the outer side surface of the first preliminary measurement layer 11, 12, 13, 14, 15, 16, 17.

[0251] The first, second, third, fourth, fifth, sixth, and seventh initial measurement patterns A1, A2, A3, A4, A5, A6, and A7 may have first, second, third, fourth, fifth, sixth, and seventh initial widths w11, w12, w13, w14, w15, w16, and w17 in one direction, respectively. Each of the first to seventh initial widths w11, w12, w13, w14, w15, w16, and w17 may be defined as a width below the first initial measurement layer 11, 12, 13, 14, 15, 16, and 17. The first initial width w11 may gradually increase toward the seventh initial width w17. That is, the first to seventh initial measurement patterns A1, A2, A3, A4, A5, A6, and A7 may be formed in a manner having a width that increases from the first initial measurement pattern A1 toward the seventh initial measurement pattern A7.

[0252] exist Fig.15a as well as Fig.15b Although the first initial measurement layers 11, 12, 13, 14, 15, 16, and 17 are exemplarily formed to have a tapered shape, the present invention is not limited thereto and the first initial measurement layers 11, 12, 13, 14, 15, 16, and 17 may be formed to have a surface perpendicular to the measurement substrate BS.

[0253] Afterwards, refer to Fig.14 , Figures 15a to 16b , the display panel manufacturing method according to the present embodiment may include a step ( S40 ) of etching the initial measurement pattern MSP-P so that at least one measurement pattern MSP is formed from the initial measurement pattern MSP-P. Fig.16b is a plan view showing a pattern remaining after the step ( S40 ) of etching the initial measurement pattern MSP-P.

[0254] The step of etching the initial measurement pattern MSP-P (S40) may include the step of using the measurement photoresist layer PRLm as a mask and wet etching the first initial measurement layers 11, 12, 13, 14, 15, 16, 17. The step of etching the initial measurement pattern MSP-P (S40) may be performed simultaneously with the step of etching the measurement photoresist layer PRLm on the partition wall PW (refer to Fig.11e )Preparatory partition PW-I to be made during manufacturing (refer to Fig.11d ) performs a second etching step (S400) (refer to Fig.10 ) is performed similarly. For example, in the step of etching the initial measurement pattern MSP-P (S40), the same method as in the step of etching the preliminary partition wall PW-I (refer to Fig.11d ) performs a second etching step (S400) (refer to Fig.10 ) The etching conditions to be manufactured are the same as those of the etching conditions to be manufactured (for example, the injected chemical solution, the time for injecting the chemical solution, etc.).

[0255] The measurement pattern MSP may be formed from the initial measurement pattern MSP-P by the step of etching the initial measurement pattern MSP-P. The step of etching the initial measurement pattern MSP-P may be formed under an environment where the etching selectivity ratio between the first initial measurement layer 11, 12, 13, 14, 15, 16, 17 and the second initial measurement layer 21, 22, 23, 24, 25, 26, 27 is large. The etching rate of the first initial measurement layer 21, 22, 23, 24, 25, 26, 27 may be greater than the etching rate of the second initial measurement layer 21, 22, 23, 24, 25, 26, 27.

[0256] In one embodiment, the first to third initial measurement patterns A1, A2, A3 (or referred to as first type patterns) may be removed. In the step of etching the initial measurement pattern MSP-P, the first initial measurement layers 11, 12, 13 of the first to third initial measurement patterns A1, A2, A3 may be etched away. Thus, the second initial measurement layers 21, 22, 23 of the first to third initial measurement patterns A1, A2, A3 may be separated from the measurement substrate BS and removed. The first to third measurement photolithography patterns P1m, P2m, P3m may also be removed together.

[0257] In one embodiment, the measurement pattern MSP may include first and second measurement patterns MSP1, MSP2. The first and second measurement patterns MSP1, MSP2 may be formed from fourth and fifth initial measurement patterns A4, A5 (or referred to as second type patterns), respectively.

[0258] The first measurement pattern MSP1 may be formed by etching a portion of the first initial measurement layer 14 in the fourth initial measurement pattern A4, and the second initial measurement layer 24 in the fourth initial measurement pattern A4 may be removed from the first initial measurement layer 14. The first initial measurement layer 14 may be etched to have a narrow width, and the second initial measurement layer 24 may be separated and removed from the first initial measurement layer 14 by reducing the adhesive force with the partially etched first initial measurement layer 14. The fourth photolithography pattern P4m for measurement may also be removed together.

[0259] The second measurement pattern MSP2 may be formed by etching a portion of the first initial measurement layer 15 in the fifth initial measurement pattern A5, and the second initial measurement layer 25 in the fifth initial measurement pattern A5 is removed from the first initial measurement layer 15. The first initial measurement layer 15 may be etched to have a narrow width, and the second initial measurement layer 25 may be separated and removed from the first initial measurement layer 15 by reducing the adhesive force with the partially etched first initial measurement layer 15. The fifth photolithography pattern P5m for measurement may also be removed together.

[0260] In one embodiment, by etching the initial measurement pattern MSP-P, a non-measurement pattern NMSP may be formed from a portion of the initial measurement pattern MSP-P. The non-measurement pattern NMSP may include a first non-measurement pattern N1 and a second non-measurement pattern N2. The first and second non-measurement patterns N1, N2 may be formed from the sixth and seventh initial measurement patterns A6, A7 (or third type patterns), respectively.

[0261] Each of the first and second non-measurement patterns N1 and N2 may include a first non-measurement pattern layer 16n and 17n and a second non-measurement pattern layer 26n and 27n.

[0262] The first non-measurement pattern layer 16n in the first non-measurement pattern N1 may be a case where a portion of the first initial measurement layer 16 of the sixth initial measurement pattern A6 is etched and remains, and the second non-measurement pattern layer 26n in the first non-measurement pattern N1 may be a case where the second initial measurement layer 26 of the sixth initial measurement pattern A6 remains. The second initial measurement layer 26 of the sixth initial measurement pattern A6 may not be etched or substantially not etched. The sixth measurement photolithography pattern P6m may also remain together.

[0263] The first non-measurement pattern layer 17n in the second non-measurement pattern N2 may be a case where a portion of the first initial measurement layer 17 of the seventh initial measurement pattern A7 is etched and remains, and the second non-measurement pattern layer 27n in the second non-measurement pattern N2 may be a case where the second initial measurement layer 27 of the seventh initial measurement pattern A7 remains. The second initial measurement layer 27 of the seventh initial measurement pattern A7 may not be etched or substantially not etched. The seventh photolithography pattern P7m for measurement may also remain together.

[0264] When the first initial measurement layers 16 and 17 have a width greater than a certain level and remain, the second initial measurement layers 26 and 27 can have sufficient adhesion to the remaining first initial measurement layers 16 and 17 and the second initial measurement layers 26 and 27 can remain.

[0265] The display panel manufacturing method according to this embodiment may include predicting the end portion TP (referring to Fig.11e ) length d-TP (refer to Figure 5 ) step (S50).

[0266] In the partition wall to be manufactured, the lower limit value of the end length can be predicted by removing the initial measurement patterns A1, A2, A3 (or, the first type pattern). The lower limit value of the end length can be predicted by the initial measurement pattern with the widest width among the initial measurement patterns A1, A2, A3 removed. For example, the lower limit value of the end length can be predicted to be half the width of the third initial measurement pattern A3.

[0267] In the partition to be manufactured, the length of the end portion can be predicted by forming the measurement patterns MSP1, MSP2 and the initial measurement patterns A4, A5 (or, the second type pattern) of the measurement patterns MSP1, MSP2. For example, the length of the end portion can be predicted as a value of subtracting the width w21 of the first measurement pattern MSP1 from the fourth initial width w14 of the fourth initial measurement pattern A4. Alternatively, the length of the end portion can be predicted as a value of subtracting the width w22 of the second measurement pattern MSP2 from the fifth initial width w15 of the fifth initial measurement pattern A5. On the other hand, in one embodiment, the length of the end portion can also be predicted as an average value of a value predicted by the first measurement pattern MSP1 and a value predicted by the second measurement pattern MSP2.

[0268] The measurement pattern MSP is different from the non-measurement pattern NMSP (or the third type pattern) in that it may not include the end portion as the second initial measurement layer 24, 25 is removed. Thus, it is convenient to check the width of the first initial measurement layer 14, 15 etched by an optical inspection device, so as not to destroy the formed result and predict the length of the end portion.

[0269] Depending on the length of the inner end of the partition wall, the moisture permeability improvement effect, whether the contact resistance is ensured, the front efficiency, etc. may be different. For example, the longer the length of the end, the more likely it is to obtain a moisture permeability improvement effect and ensure the contact resistance. On the contrary, the narrower the length of the end, the more the area of ​​the light-emitting region may increase, improving the front efficiency. Therefore, depending on the characteristics required by the display panel to be manufactured, it may be necessary to accurately remove the length of the inner end of the partition wall. According to the present invention, it is convenient to check the length of the partition wall to be formed and to predict the length of the partition wall to be formed.

[0270] According to the present invention, an inspection pattern capable of inspecting the end of the partition wall is included, so that the process reliability of the display panel can be improved.

[0271] According to the present invention, the end length of the partition wall can be predicted in advance by measuring a pattern having the same structure as the partition wall.

[0272] The above description is made with reference to the preferred embodiments of the present invention, but it is understood by those skilled in the art or those with common knowledge in the art that various modifications and changes can be made to the present invention within the scope of the concept and technical field of the present invention as described in the attached claims. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display panel, wherein: include: A partition wall includes a first partition wall layer and a second partition wall layer disposed on the first partition wall layer, and defines a partition wall opening and an inspection opening; as well as an inspection pattern, arranged in the inspection opening, The partition opening comprises: a first region defined by the inner side surface of the first partition layer; as well as a second region defined by the inner side surface of the second partition layer and having a smaller width than the first region, The inspection pattern includes the same material as that of the first partition layer.

2. The display panel according to claim 1, wherein: The inspection opening comprises: a third region defined by the inner side surface of the first partition layer; and a fourth region defined by the inner side surface of the second partition layer, The inspection pattern is arranged in the third region and is not arranged in the fourth region.

3. The display panel according to claim 1, wherein: The inspection opening and the inspection pattern are each provided in plurality, One of the inspection patterns is arranged in each of the inspection openings.

4. The display panel according to claim 1, wherein: The inspection opening and the inspection pattern are each provided in plurality, A plurality of the inspection patterns having mutually different widths are arranged in each of the inspection openings.

5. The display panel according to claim 1, wherein: The display panel further includes: The light emitting element includes an anode, a light emitting pattern and a cathode, and is arranged in the partition opening. The cathode is in contact with the barrier rib in the barrier rib opening.

6. The display panel according to claim 5, wherein: The display panel further includes: A thin film encapsulation layer is disposed on the light emitting element. The inspection pattern contacts the thin film encapsulation layer.

7. A method for manufacturing a display panel, wherein: include: forming a preliminary barrier rib including a first preliminary barrier rib layer and a second preliminary barrier rib layer disposed on the first preliminary barrier rib layer; A step of etching the preliminary partition once; as well as a step of etching the preliminary partition wall twice to form a partition wall including a first partition wall layer and a second partition wall layer disposed on the first partition wall layer, In the step of etching the preliminary partition once, an initial inspection pattern is formed. In the step of etching the preliminary partition twice, forming an inspection pattern from the initial inspection pattern, The inspection pattern includes the same material as that of the first partition layer.

8. The method for manufacturing a display panel according to claim 7, wherein: The step of etching the preliminary partition wall once includes the step of etching the first preliminary partition wall layer and the second preliminary partition wall layer. The step of etching the preliminary partition wall twice includes the step of etching the first preliminary partition wall layer.

9. The method for manufacturing a display panel according to claim 8, wherein: Each of the initial inspection patterns comprises: a first initial inspection pattern layer patterned from the first preliminary barrier rib layer; and The second initial inspection pattern layer is patterned from the second preliminary barrier rib layer.

10. The method for manufacturing a display panel according to claim 9, wherein: the preliminary check pattern includes a first preliminary check pattern and a second preliminary check pattern having a width wider than the first preliminary check pattern, In the step of etching the preliminary partition twice, the first initial inspection pattern is removed, and the second initial inspection pattern layer in the second initial inspection pattern is removed, and a portion of the first initial inspection pattern layer in the second initial inspection pattern remains, thereby forming the inspection pattern.

11. The method for manufacturing a display panel according to claim 8, wherein: In the step of etching the preliminary partition wall twice, an end portion defined as a portion where the second partition wall layer protrudes beyond the first partition wall layer is formed on the partition wall.

12. The method for manufacturing a display panel according to claim 11, wherein: The display panel manufacturing method further includes: After the step of etching the preliminary partition twice, the step of inspecting the end portion, In the step of inspecting the end portion, the length of the end portion is determined by determining whether the initial inspection pattern is removed in the step of etching the preliminary partition twice.

13. The method for manufacturing a display panel according to claim 11, wherein: The display panel manufacturing method further includes, before the step of forming the preliminary partition wall: forming a preliminary measurement pattern including a first preliminary measurement layer containing the same substance as the first preliminary partition wall layer and a second preliminary measurement layer containing the same substance as the second preliminary partition wall layer and disposed on the first preliminary measurement layer; a step of etching the preliminary measurement pattern to form an initial measurement pattern; a step of etching the initial measurement pattern so as to form a measurement pattern; and the step of predicting the length of the end, The initial measurement patterns have widths different from each other.

14. The method for manufacturing a display panel according to claim 13, wherein: The step of etching the preliminary measurement pattern is performed under the same etching conditions as the step of etching the preliminary partition once, The step of etching the initial measurement pattern is performed under the same etching conditions as the step of etching the preliminary partition twice.

15. The method for manufacturing a display panel according to claim 13, wherein: Each of the initial measurement patterns comprises: a first initial measurement layer patterned from the first preliminary measurement layer; and The second initial measurement layer is patterned from the second preliminary measurement layer.

16. The method for manufacturing a display panel according to claim 15, wherein: The initial measurement pattern includes a first type pattern and a second type pattern, In the step of etching the initial measurement pattern, the first type pattern is removed, and the second initial measurement layer in the second type pattern is removed, and a portion of the first initial measurement layer in the second type pattern remains, thereby forming the measurement pattern.

17. The method for manufacturing a display panel according to claim 16, wherein: In the step of predicting the length of the end portion, a lower limit value of the length of the end portion is predicted as a width of the first type pattern to be removed.

18. The method for manufacturing a display panel according to claim 16, wherein: In the step of predicting the length of the end portion, the length of the end portion is predicted as a difference between a width of the second type pattern and a width of the measurement pattern.

19. A method for manufacturing a display panel, wherein: include: forming a plurality of initial measurement patterns each including a first initial measurement layer and a second initial measurement layer arranged on the first initial measurement layer; a step of forming a measurement pattern from said initial measurement pattern; The step of predicting the length of the end portion by means of the measurement pattern; as well as forming a partition wall including a first partition wall layer and a second partition wall layer disposed on the first partition wall layer and defining the end portion, The first initial measurement layer includes the same substance as the first partition layer, and the second initial measurement layer includes the same substance as the second partition layer. The measurement pattern is formed by leaving the first initial measurement layer of any one of the initial measurement patterns and removing the second initial measurement layer of the any one of the initial measurement patterns.

20. The method for manufacturing a display panel according to claim 19, wherein: The step of forming the partition wall comprises: forming a preliminary barrier rib including a first preliminary barrier rib layer and a second preliminary barrier rib layer disposed on the first preliminary barrier rib layer; performing a first etching on the preliminary partition wall so as to etch the first preliminary partition wall layer and the second preliminary partition wall layer; and a step of performing a second etching on the preliminary partition wall so as to etch the first preliminary partition wall layer, The step of forming the initial measurement pattern is performed under the same etching conditions as the step of etching the preliminary partition once, The step of forming the measurement pattern is performed under the same etching conditions as the step of etching the preliminary partition twice.

Images