Holding capacitor failure handling in data storage device

Abstract

A data storage device includes a plurality of holding capacitors configured to provide backup power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed holding capacitors of the plurality of holding capacitors; and in response to detecting the one or more failed holding capacitors: performing one or more silence operations, and determining a count of the one or more failed holding capacitors. Based on the count of the one or more failed holding capacitors, the controller is configured to reallocate a write buffer of the write cache for use in one or more subsequent write operations.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 18 / 348,316, filed in the U.S. Patent and Trademark Office on July 6, 2023, entitled “Hold-Up Capacitor Failure Handling in Data Storage Devices,” and is hereby incorporated by reference in its entirety for all purposes, which application claims priority to U.S. Provisional Application No. 63 / 413,131, filed on October 4, 2022. Background Art

[0003] Data storage devices enable users to store and retrieve data. Examples of data storage devices include non-volatile memory devices. Non-volatile memory typically retains data after power cycles. An example of non-volatile memory is flash memory, which may include one or more NAND cell arrays on one or more dies. Flash memory may be found in solid state drives (SSDs), secure digital (SD) cards, and the like.

[0004] Data storage devices such as SSDs may include a set of retention capacitors to prevent unexpected power loss in order to protect user data. If one or more retention capacitors fail during the life of the drive, the drive may not properly power down. This may result in the drive losing functionality and may even lead to a scenario where the user can no longer access the data stored on the drive.

[0005] Some conventional data storage devices may implement various self-protection measures upon detection of a failed retention capacitor in order to prevent the loss of user data stored on the drive. While these measures may have the benefit of preventing data loss, they are often at the expense of severely limited drive performance and / or functionality. Such limitations may be as severe as preventing subsequent writes to the drive, and are often substantial and irreversible. Summary of the invention

[0006] Based on the above discussion and other problems and shortcomings of the related art, there is a need for a system that can handle retention capacitor failures in a data storage device in a more elegant manner that not only prevents data loss but also preserves more performance and functionality of the drive. A data storage device implementing such a system can continue to be usable after one or more retention capacitors fail. In addition, such a data storage device can exhibit improved post-capacitor failure write performance when compared to the write performance of a conventional data storage device.

[0007] According to one or more aspects of the retention capacitor failure handling scheme described herein, upon detecting a failed retention capacitor, a data storage device controller isolates the failed retention capacitor and counts the number of failed retention capacitors. Based on the number of failed retention capacitors, the controller reallocates a write cache of the data storage device before performing a subsequent write operation.

[0008] In some implementations, the reallocation may include reducing the size of the write cache used in the execution of subsequent write operations. The portion of the write cache remaining after the retention capacitor fails may continue to be used for low-latency cached write operations, thereby optimizing the write performance of the data storage device while maintaining reliability after the retention capacitor fails. The size of this reduced portion may depend on the number of retention capacitors that failed.

[0009] In some implementations, in addition to or as an alternative to reducing the size of the write cache used in the execution of subsequent write operations, reallocation may also include dividing the write cache into portions that handle subsequent write operations differently. For example, a first portion may continue to perform low-latency cached write operations while a second portion may perform less efficient but more reliable write-through write operations, thereby optimizing the write performance of the data storage device while maintaining reliability after a retention capacitor failure. The size of each portion may depend on the number of failed retention capacitors.

[0010] In one or more aspects, the aforementioned write cache reallocation scheme optimizes the write performance of the data storage device by allowing more write cache to continue to be useful after the retention capacitor fails. In addition, the aforementioned write cache reallocation scheme maintains the reliability of the data storage device by preventing data loss that may otherwise occur after a subsequent power outage event. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the present disclosure, are incorporated in and constitute a part of the present disclosure, illustrate embodiments of the present disclosure, and together with the description serve to explain the principles of the present disclosure. For ease of understanding, the same components are marked with the same reference numerals.

[0012] Figure 1 is a block diagram illustrating components of an example data storage system according to some implementations.

[0013] Figure 2 is a circuit diagram of an example retention capacitor bank for providing power loss protection in a data storage device according to some implementations.

[0014] FIG. 3A to FIG. 3Cis an example of a state transition diagram for allocation and deallocation operations performed by a write buffer of a write cache of a data storage device according to some implementations.

[0015] Figure 4 is an example state transition diagram of a retention capacitor failure handling scheme for a data storage device according to some specific implementations.

[0016] Figure 5 is an example of a drive operating mode transition scheme illustrating write cache reallocation including a reduction in the size of the write cache according to some implementations.

[0017] Figure 6 is an example of a drive operating mode transition scheme illustrating write cache reallocation including reallocation of portions of the write cache performing cached writes and write-through writes according to some implementations.

[0018] Figure 7 is a flow chart of an example of a retention capacitor failure handling method according to some specific implementations.

[0019] FIG. 8A to FIG. 8B is a chart illustrating example benefits of the retention capacitor failure handling scheme described herein according to some specific implementations.

[0020] In one or more implementations, not all of the components shown in each of the figures are required, and one or more implementations may include additional components not shown in the figures. Changes to the arrangement and types of components may be made without departing from the scope of the disclosure of the present subject matter. Additional components, different components, or fewer components may be utilized within the scope of the disclosure of the present subject matter. DETAILED DESCRIPTION

[0021] The detailed description set forth below is intended to be a description of various specific implementations, and is not intended to represent the only specific implementation that can practice the subject technology. As will be appreciated by those skilled in the art, the specific implementation described can be modified in various different ways, all of which do not depart from the scope of the present disclosure. Therefore, the drawings and descriptions are essentially considered to be illustrative rather than restrictive.

[0022] The present description relates generally to data storage systems and methods, and more particularly to handling retention capacitor failures, for example but not limited to, in data storage devices.

[0023] One or more embodiments of the subject technology provide several performance benefits that improve the functionality of a computer. By reallocating write cache based on the number of failed retention capacitors using the scheme described herein, user data can be protected while optimizing the write performance of a data storage device. In turn, a host computer coupled to the data storage device also receives the benefits of improved performance and security of the data storage device.

[0024] Figure 1 is a block diagram illustrating components of an exemplary data storage system according to aspects of the subject technology. A data storage system may sometimes be referred to as a system, a data storage device, a storage device, a solid-state drive, a drive, or a device. Figure 1 As depicted, in some implementations, a data storage device 100 (e.g., a solid-state drive (SSD)) includes a data storage controller 101, a storage medium 102, and a flash memory array including one or more flash memories 103. The data storage controller 101 may sometimes be referred to as a controller. The controller may include one or more controllers. The controller 101 may use the storage medium 102 to temporarily store data and information for managing the data storage device 100. The controller 101 may include several internal components (not shown), such as a read-only memory, other types of memory, a flash memory component interface (e.g., a multiplexer for managing instructions and data transfer along a serial connection to the flash memory 103), an input / output (I / O) interface, an error correction circuit, etc. In some implementations, some or all of these elements of the controller 101 may be integrated into a single chip. In other aspects, these elements may be separated on their own printed circuit boards (PCBs).

[0025] In some implementations, aspects of the subject disclosure may be implemented in data storage device 100. For example, aspects of the subject disclosure may be integrated with the functionality of data storage controller 101, or may be implemented as separate components used in conjunction with data storage controller 101.

[0026] The controller 101 may also include one or more processors that may be configured to execute code or instructions to perform the operations and functions described herein, manage request flows and address mappings, and perform calculations and generate commands. The one or more processors of the controller 101 may be configured to monitor and / or control the operation of components in the data storage controller 101. The processor may be a microprocessor, a microcontroller, or a digital signal processor (DSP). The processor may be implemented using, for example, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, a gated logic device, a discrete hardware component, or a combination of the foregoing. One or more instruction sequences may be stored as firmware on a read-only memory (ROM) within the controller 101 and / or its processor. One or more instruction sequences may be software stored and read from the storage medium 102, the flash memory 103, or software received from the host device 104 (e.g., via the host interface 105). ROM, storage medium 102, and flash memory 103 represent examples of machine-readable media or computer-readable media that can store instructions / codes executable by the controller 101 and / or its processor. Machine-readable media or computer-readable media may generally refer to any media or media for providing instructions to the controller 101 and / or its processor, including both volatile media such as dynamic memory for the storage medium 102 or for a buffer within the controller 101 and non-volatile media such as electronic media, optical media, and magnetic media. The one or more media may be one or more non-transitory media.

[0027] In some implementations, controller 101 may be configured to store data received from host device 104 in flash memory 103 in response to a write command from host device 104. Controller 101 is also configured to read data stored in flash memory 103 and transmit the read data to host device 104 in response to a read command from host device 104. Host device 104 may sometimes be referred to as a host, a host system, or a host computer.

[0028] The host device 104 represents any device configured to couple to the data storage system 100 and store data in the data storage system 100. The host device 104 may be a computing system, such as a personal computer, a server, a workstation, a laptop computer, a personal digital assistant (PDA), a smart phone, etc. Alternatively, the host device 104 may be an electronic device, such as a digital camera, a digital audio player, a digital video recorder, etc.

[0029] In some implementations, storage medium 102 represents a volatile memory for temporarily storing data and information for managing data storage system 100. According to aspects of the subject technology, storage medium 102 is a random access memory (RAM), such as a double data rate (DDR) RAM. Other types of RAM may also be used to implement storage medium 102. Storage medium 102 may be implemented using a single RAM module or multiple RAM modules. Although storage medium 102 is depicted as being distinct from controller 101, those skilled in the art will appreciate that storage medium 102 may be incorporated into controller 101 without departing from the scope of the subject technology. Alternatively, storage medium 102 may be a non-volatile memory, such as a magnetic disk, flash memory, a peripheral SSD, etc.

[0030] In some implementations, the storage medium 102 includes a write cache 110, which may be configured to temporarily store data corresponding to a write command received from the host 104 for transfer to one or more flash memories 103 for storage. By first storing the data in the write cache 110, the write command may be satisfied with improved performance. The write cache 110 may include multiple buffers for storing data to be written. Multiple buffers may be referred to as a buffer pool. Likewise, the write cache 110 may be referred to as a buffer pool. In some implementations, the write cache 110 may be combined or otherwise include a read cache; therefore, the cache 110 may sometimes be referred to as a read / write cache. In one or more aspects of the present disclosure focused on optimizing write performance, the cache 110 may be referred to as a write cache. The write cache 110 may be a non-volatile write cache, including a non-volatile memory such as a disk, a flash memory, a peripheral SSD, etc. In some implementations, the write cache 110 (or the storage medium 102) may be included in the controller 101. In some implementations, a data storage device including a controller and a write cache (e.g., 100) may represent a data storage device including a controller and a write cache that are external to the controller, or may represent a data storage device including a controller and a write cache that are internal to the controller.

[0031] like Figure 1As further depicted, the data storage system 100 may also include a host interface 105. The host interface 105 may be configured to be operably coupled (e.g., via a wired or wireless connection) to the host device 104 to receive data from the host device 104 and send data to the host device 104. The host interface 105 may include an electrical connection and a physical connection or a wireless connection to operably couple the host device 104 to the controller 101 (e.g., via an I / O interface of the controller 101). The host interface 105 may be configured to transmit data, addresses, and control signals between the host device 104 and the controller 101. Alternatively, the I / O interface of the controller 101 may include the host interface 105 and / or be combined with the host interface. The host interface 105 may be configured to implement a standard interface such as a small computer system interface (SCSI), a serial attached SCSI (SAS), a fiber channel interface, a peripheral component express interconnect (PCIe), a serial advanced technology attachment (SATA), a universal serial bus (USB), a non-volatile express memory (NVMe), etc. The host interface 105 may be configured to implement only one interface. Alternatively, the host interface 105 (and / or the I / O interface of the controller 101) may be configured to implement multiple interfaces, which may be individually selected using configuration parameters selected by the user or programmed at assembly. The host interface 105 may include one or more buffers for buffering transmissions between the host device 104 and the controller 101.

[0032] Flash memory 103 may represent a non-volatile memory device for storing data. According to aspects of the subject technology, flash memory 103 includes, for example, NAND flash memory. Flash memory 103 may include a single flash memory device or chip, or (e.g., Figure 1 The flash memory 103 may include multiple flash memory devices or chips arranged in multiple channels. The flash memory 103 is not limited to any particular capacity or configuration. For example, the number of physical blocks, the number of physical pages per physical block, the number of sectors per physical page, and the size of the sectors may vary within the scope of the subject technology.

[0033] Flash memory can have a standard interface specification so that chips from multiple manufacturers can be used interchangeably (at least to a large extent). The interface hides the internal workings of the flash memory and only returns the data bit values ​​detected internally. In some aspects, the interface of the flash memory 103 is used to access one or more internal registers 106 and an internal flash controller 107 to communicate through an external device (e.g., controller 101). In some specific implementations, registers 106 may include address registers, command registers, and / or data registers, which retrieve necessary data from and output necessary data to NAND memory cell array 108 internally. NAND memory cell array 108 may sometimes be referred to as a NAND array, memory array, or NAND. For example, a data register may include data to be stored in memory array 108, or data after being taken out of memory array 108, and may also be used for temporary data storage and / or act like a buffer. The address register may store a memory address from which data is to be extracted to host device 104 or an address to which data is to be sent and stored. In some specific implementations, a command register is included to control parity, interrupt control, etc. In some implementations, the internal flash controller 107 is accessible via control registers to control the general behavior of the flash memory 103. The internal flash controller 107 and / or control registers may control the number of stop bits, word length, receiver clock source, and may also control switching addressing modes, paging control, coprocessor control, etc.

[0034] In some implementations, register 106 may also include a test register. The test register may be accessed by a specific address and / or data combination provided at the interface of flash memory 103 (e.g., by dedicated software provided by the manufacturer for performing various tests on the internal components of the flash memory). In other aspects, the test register may be used to access and / or modify other internal registers, such as command registers and / or control registers. In some implementations, the test mode accessible via the test register may be used to input or modify certain programming conditions (e.g., read levels) of the flash memory 103 to dynamically change the manner in which data is read from the memory cells of the memory array 108. Register 106 may also include one or more data latches coupled to the flash memory 103.

[0035] It should be understood that in all cases, data may not always be the result of a command received from and / or returned to the host 104. In some embodiments, the controller 101 may be configured to perform read operations independent of the host 104 (e.g., to verify a read level or bit error rate (BER)). As used herein, the predicates "configured to," "operable to," and "programmed to" do not imply any specific tangible or intangible modification of an object, but are intended to be used interchangeably. For example, a processor configured to monitor and control an operation or component may also mean a processor programmed to monitor and control an operation, or a processor operable to monitor and control an operation. Similarly, a processor configured to execute code may be understood as a processor programmed to execute code or operable to execute code.

[0036] Figure 2 is a circuit diagram of an example retention capacitor bank 200 configured to provide power loss protection in a data storage device (e.g., SSD) according to some specific implementations. In this example, the capacitor bank 200 includes n retention capacitors: C1, C2, ..., Cn, which are electrically coupled in parallel with power terminals and ground terminals of the data storage device 100. The number of capacitors and / or the capacitance values ​​of the capacitors can be determined based on the characteristics of the data storage device (e.g., the amount of flash memory, drive capacity, controller design, host write algorithm, indirect table management, performance requirements, various flash transformation layer (FTL) algorithms) and / or the amount of backup power required by the data storage device 100.

[0037] When the data storage device 100 is connected to a power source (e.g., the host 104 or some other external power source), the retention capacitor is charged. When the data storage device 100 is powered off (e.g., unplugged from the host 104 or otherwise removed from the external power source), the retention capacitor is discharged for a period of time that is intended to be long enough for the data storage device 100 to safely power itself off. This amount of time may be referred to as the scram time and depends on the number of retention capacitors in the retention capacitor bank 200 and the capacitance values ​​of the retention capacitors.

[0038] During the emergency stop time, the data storage device 100 safely powers itself off by quickly performing an emergency stop operation while the holding capacitor still has sufficient charge to provide sufficient power to the data storage device 100. The emergency stop operation refers to the processing that occurs when power is removed from the data storage device 100. The power-off condition may occur due to a variety of reasons, such as an unintentional power failure, an operation by a user to remove the data storage device 100 from its external power source, or an operation by a user to deactivate the data storage device 100. A relatively small amount of standby power can be provided by the holding capacitor bank 200 to enable the data storage device 100 to continue operating during the shutdown emergency stop operation. As part of the shutdown process, it is usually necessary to complete any data write operations in progress and flush any cached write-back data from the write cache 110 to the flash memory 103. This may cause difficulties if a large amount of processing is required to complete the data transfer.

[0039] The data storage device 100 has a finite amount of retention energy after a power loss, which depends on the number of retention capacitors. An increase in the number of capacitors allows the data storage device 100 to remain alive longer after a power loss. On the other hand, limiting the amount of data that can be written after a power loss can limit data storage performance because data write requests will need to be rejected until previously opened write requests have completed. Therefore, one object of the present disclosure is to maximize the amount of data that can be safely written given the number of retention capacitors that are still functional after one or more retention capacitors fail.

[0040] In some implementations, firmware running on the data storage device 100 can periodically check the health of the capacitor bank 200. The frequency of the health check can be adjusted. However, if these health checks are performed too frequently, excessive processing bandwidth may be required. This may in turn affect the throughput of the data storage device 100.

[0041] In some implementations, the data storage device 100 may include, for example, Figure 2 B. Figure 2 C and FIG. 3 and the holding capacitor health check and isolation circuit described in the corresponding disclosure in U.S. Patent Application No. 17 / 852,103 filed on June 28, 2022, which is incorporated herein by reference in its entirety. Additionally or alternatively, any other capacitor health check scheme may be implemented to determine the health of the holding capacitors in capacitor bank 200. An example capacitor health check scheme may include a periodic health check, which may include a recharge test (e.g., if a capacitor is discharged and / or recharged too quickly, it may be a failed capacitor).

[0042] Upon detection of a failed retention capacitor, the present disclosure describes various implementations for adapting to the new state of the capacitor bank 200 and maintaining the ability of the data storage device 100 to perform write operations at the best possible performance level without risk of data loss, rather than immediately transitioning the data storage device to a read-only mode. To this end, the data storage device 100 may determine which retention capacitors have failed and isolate them, thereby allowing the data storage device 100 to continue operating using the remaining retention capacitors. Figure 4 Additional details regarding handling of retention capacitor failure are described through FIG. 8 .

[0043] FIG. 3A to FIG. 3C is a state transition diagram of allocation and release operations performed by write buffers of the write cache 110 of the data storage device 100 according to some specific implementations. As part of the write buffer life cycle 300, the controller 101 allocates data write buffers according to the write buffer allocation scheme 310 to store data received from the host 104. Then, depending on the type of write operation performed on the data, the controller 101 releases the write buffers so that they can store new data according to the write buffer release scheme 320 (for cached writes) or the write buffer release scheme 330 (for write-through writes).

[0044] More specifically, according to the write buffer allocation scheme 310 ( Figure 3A ), the controller 101 extracts (312) the write command from the host submission queue and allocates (314) a write buffer of the write cache 110 to store the data corresponding to the write command. The controller 101 then initiates (316) a data transfer of the data from the write cache 110 to the flash memory 103. Once the data transfer is complete, the controller 101 completes (318) the write command (e.g., by notifying the host 104 that the data has been written) and waits (319) for a subsequent write command to arrive, at which point the process repeats with another write command extraction (312).

[0045] If the data is to be written using a cached write process (which may sometimes be referred to as a write-back process or a write-behind process), then the data is written according to the write buffer release scheme 320 ( Figure 3B ) to release the write buffer. The cached write process is a high performance, power failure-susceptible write scheme because the data buffer is released before the data itself has been safely written to the non-volatile NAND array 108 in the corresponding flash memory 103. The early release of the write buffer allows for increased throughput, but at the same time increases the likelihood of data loss if the emergency stop operation cannot be completed (e.g., due to a hold capacitor failure).

[0046] More specifically, the controller 101 waits (322) until there is enough data to be transferred to the flash memory 103 (at Figure 3B Once there is enough data to be written (e.g., a data page, a superblock, etc.), the controller 101 transfers (324) the data to the flash memory 103 and immediately releases (326) the write buffer. At this point in time, the data is in the volatile memory (data register 106) in the corresponding flash memory 103 and has not yet been written to the non-volatile memory (NAND array 108) in the corresponding flash memory 103. At the same time, the non-volatile write buffer that transferred the data to the flash memory 103 has been released to accept new data.

[0047] Thus, when in state 324, the data being transferred is currently in volatile memory and may be lost if the data storage device 100 loses power before the data can be written to the non-volatile NAND array 108. Thus, even though the cached write process benefits from efficiency (due to the write buffer being released earlier), the cached write process also incurs the cost of potential data loss. When the data transfer to the volatile memory of the flash memory 103 (e.g., the latches in the registers 106) is complete, the controller 101 and / or the controller 107 initiates (328) a programming operation (referred to as a write-on-the-fly or a program-on-the-fly) inside the flash memory 103, which causes the data to be written from the volatile registers 106 to the non-volatile NAND array 108.

[0048] The aforementioned cached write operations may sometimes be referred to as write-back operations, post-write operations, or running write operations. A controller performing a write operation according to a write-back scheme first writes the data to the write cache 110, and then once the data has been written to the write cache 110, the data is sent to the flash memory 103. Caching in this manner results in low latency for write operations. However, in the event of a cache failure (e.g., due to a power-off event of the data storage device 100), if the data is not written to the non-volatile memory in the flash memory 103, the cached data may potentially be lost, as discussed above.

[0049] If the data is to be written using a write-through process, then according to the buffer release scheme 330 ( Figure 3C ) to release the write buffer. The write-through write process is a write scheme that is less susceptible to power failures because the data buffer is not released until the data itself has been safely written to the non-volatile NAND array 108 in the corresponding flash memory 103. More specifically, the controller 101 waits (332) until there is enough data to be transferred to the flash memory 103 (in Figure 3C108). Once there is enough data to be written (e.g., data pages, super blocks, etc.), the controller 101 transfers (334) the data to the flash memory 103 and waits (336) for the programming operation to complete (e.g., waiting for the data to be safely written to the non-volatile NAND array 108). At this point in time, the data is still in the non-volatile write buffer of the write cache 110. Therefore, if the data storage device 100 loses power before the data can be written to the non-volatile NAND array 108, the data may not be lost. Although the write-through write scheme does not have the risk of data loss associated with power loss, this scheme is relatively inefficient because the write buffer cannot accept new data while the controller 101 waits (336) for the programming operation to complete. When the data transfer to the volatile memory (e.g., latches in registers 106) of the flash memory 103 is complete, the controller 107 notifies the controller 101, and the controller 101 then releases (338) the write buffer to receive new data.

[0050] A controller that performs write operations according to a write-through scheme writes data to the write cache 110 and the flash memory 103 before releasing the write buffer in the write cache 110 to accept new data. In the event of a cache failure (e.g., due to a power outage event of the data storage device 100), caching in this manner is safer because the data is always present in the non-volatile memory throughout the write operation. However, due to the delay in releasing the write buffer, the write scheme has a higher latency. Nevertheless, compared to a data storage device 100 operating in a read-only mode in which no write operations are allowed to occur, a data storage device 100 that writes data according to a write-through scheme has a higher write performance.

[0051] The retention capacitor failure handling scheme described in the present disclosure uses different combinations of the buffer release schemes 320 and 330 described above, as described below with reference to Figure 4 This is described in more detail in Figure 8.

[0052] Figure 4 4 is a state transition diagram of a retention capacitor failure handling scheme 400 for a data storage device 100 according to some specific implementations. The data storage device 100 employing the scheme 400 begins operating in a normal mode (which may be referred to as a full performance mode) 402. When operating in the normal mode 402, a retention capacitor failure has not been detected, and the write cache 110 operates in a manner optimized to maximize performance. That is, the controller 101 uses all write buffers in the write cache 110 to perform cached writes, and therefore, the controller 101 performs cached writes according to the write buffer release scheme 320 ( Figure 3B) to operate all write buffers. As discussed above, this mode (where all write buffers are released according to scheme 320) is the most efficient, but also the most disadvantageous in the face of power failure events, because all retention capacitors of capacitor bank 200 need to be retained to ensure reliable data transfer to non-volatile memory in the event of power failure.

[0053] When operating in normal mode 402, if the controller 101 detects that a retention capacitor has failed, the data storage device 100 enters state 408, during which the controller 101 detects which retention capacitors have failed and isolates them, as described above. During this state, the controller 101 counts the total number of failed retention capacitors, and if the number is below the first threshold TH1 (or less than or equal to the first threshold TH1) (for example, less than or equal to 2), the data storage device 100 transitions to reduced throughput mode 404. Otherwise, the data storage device 100 remains in normal mode 402. When operating in reduced throughput mode 404, the write cache 110 operates in a manner that allows cached writes to continue so that subsequently received data can be written, but at a reduced rate to account for the reduced scram power capacity (due to the failed retention capacitors). Refer below to Figure 5 and Figure 6 Further details are described regarding various schemes for implementing reduced throughput mode.

[0054] When operating in the normal mode 402 or the reduced throughput mode 404, if the controller 101 detects that another holding capacitor has failed, the data storage device 100 enters the state 408 again, during which the controller 101 detects which holding capacitors have failed and isolates them, as described above. During this state, the controller 101 counts the total number of failed holding capacitors, and if the number is between the first threshold TH1 and the second threshold TH2 (e.g., greater than TH1 and less than or equal to TH2, or greater than or equal to TH1 and less than TH2, or greater than TH1 and less than TH2) (e.g., greater than 2 and less than 6), the data storage device 100 transitions to the read-only mode 406. Otherwise, the data storage device 100 remains in the reduced throughput mode 404. When operating in the read-only mode 406, the data storage device 100 is restricted from writing any new data to the flash memory 103. This is because there is not enough crash energy left to reliably complete all write operations (due to the failed holding capacitors), and the data is most likely to be lost in the event of a power failure.

[0055] Figure 51 is a diagram illustrating a drive operation mode transition scenario 500 that includes write cache reallocation with a reduction in the size of the write cache 110 according to some implementations. In the scenario 500, the reduced throughput mode 404 is implemented by reducing the size of the write cache 110.

[0056] Specifically, when in normal mode 402, all write buffers in write cache 110 operate according to efficient buffer release scheme 320 (corresponding to cached writes). In other words, the entire buffer pool of write cache 110 is configured to operate according to allocation scheme 310 and release scheme 320.

[0057] When operating in normal mode 402, upon a power failure event (labeled as power fail or pfail in the figure), the controller 101 performs an emergency stop operation that begins with the completion of all running programs (all cached write operations currently using the write buffers in the write cache 110). Upon completion of all running programs, the controller 101 flushes the write cache 110, flushes the L2P table, flushes the data structures, and keeps itself powered long enough to perform these and other housekeeping operations (e.g., involving dynamic random access memory (DRAM) and other volatile components of the data storage device 100).

[0058] When operating in the normal mode 402, if less than the first threshold TH1 of failed retention capacitors is detected (e.g., if only 1 or 2 failed retention capacitors are detected), the data storage device 100 transitions to the reduced throughput mode 404, which includes the controller 101 reducing the size of the write cache 110. In other words, the controller 101 reallocates the write cache 110, or reallocates the write buffers in the write cache 110, so that there are fewer write buffers (e.g., write buffers in the portion 510) available to perform cached write operations. The reset of the write buffers (e.g., those in the portion 512) can be reused for other data storage tasks of the data storage device 100. The size of the portion 510 of the write cache 110 can be based on the number of failed retention capacitors detected. For example, if only one failed retention capacitor is detected, the portion 510 in the reduced throughput mode 404 can be half the size of the portion 510 in the normal mode 402, and if two failed retention capacitors are detected, the portion 510 in the reduced throughput mode can be one-quarter the size of the portion 510 in the normal mode 402. The specific relationship between the increase in the failed retention capacitor count and the decrease in the write cache size may depend on the specific design requirements of the data storage device 100 .

[0059] When operating in reduced throughput mode 404, upon a power outage event, controller 101 performs an emergency stop operation as described above, with at least two significant differences. First, because the size of the buffer pool of write cache 110 is reduced, fewer running programs are to be completed, and the amount of write buffers of write cache 110 that need to be flushed is reduced. Therefore, less emergency stop energy is required to complete the emergency stop operation in reduced throughput mode 404, thereby performing in a manner consistent with fewer holding capacitors being available to supply emergency stop energy during the shutdown period.

[0060] When operating in the reduced throughput mode 404, if a number of failed retention capacitors between the first threshold TH1 and the second threshold TH2 is detected (e.g., if only more than 2 and less than 7 failed retention capacitors are detected), the data storage device 100 transitions to a read-only mode 406, which includes the controller 101 reducing the size of the write cache 110 to zero. Therefore, all write buffers in the portion 512 of the buffer pool of the write cache 110 in the reduced throughput mode 404 are unavailable for performing write operations, and the data storage device 100 stops accepting write commands and performing write operations.

[0061] When operating in read-only mode 406, upon a power outage event, controller 101 performs an emergency stop operation as described above, with at least two significant differences. First, since the size of the buffer pool of write cache 110 is now zero, there are no running programs to complete, and no write cache to flush. Thus, completing an emergency stop operation in read-only mode 406 requires even less emergency stop energy, thereby performing in a manner consistent with even less hold-up capacitors being available to supply emergency stop energy during the shutdown period.

[0062] Figure 66 is a drive operating mode transition scheme 600 illustrating write cache reallocation including reallocation of portions of the write cache 110 that perform cached writes and write-through writes according to some specific implementations. In scheme 600, full mode 402 and read-only mode are the same as described above (except for possible differences in threshold TH values), but scheme 600 includes two reduced throughput modes: hybrid mode 602 and write-through mode 604, rather than a single reduced throughput mode 404. In scheme 600, rather than reducing the size of the write cache 110, the size of the write cache 110 remains the same while (i) reducing the portion 610 of the write cache 110 that is used to perform efficient but power-hungry cached writes (e.g., making fewer write buffers available for cached writes), and (ii) increasing the portion 612 of the write cache 110 that is used to perform less efficient but power-hungry write-through writes (e.g., making more write buffers available for write-through writes).

[0063] Specifically, when operating in normal mode 402, the data storage device 100 and the corresponding emergency stop operation are as described above with reference to Figure 5 4. The controller 101 operates as described in the normal mode 402 in FIG. 4. If less than TH1 failed holding capacitors are detected (e.g., 1 or 2), the data storage device 100 transitions to a hybrid mode 602 in which the write cache 110 is reallocated into two portions: a first portion 610 associated with cached writes (operating according to the buffer release scheme 320), and a second portion 620 associated with write-through writes (operating according to the buffer release scheme 330). When operating in the hybrid mode 602, upon a power outage event, the controller 101 performs the emergency stop operations as described above with reference to the normal mode 402, except that the number of running programs that need to be completed is reduced (this is because the portion 610 is smaller in the hybrid mode 602 than it is in the normal mode 402). Therefore, less emergency stop energy is required.

[0064] Importantly, when operating in hybrid mode 602, upon a power outage event, all write-through operations using the write buffers in portion 612 (which may be aborted in the middle of a write) may be stopped immediately to save scram power, since these write buffers have not yet been released. Thus, these write operations may be aborted in the middle of a write and restarted upon power-up (when power is reapplied to the data storage device 100), since the data is still in these write buffers. However, cached write operations using the write buffers in portion 610 cannot be aborted, since the data in these write buffers has been replaced by new data from the host 104. Therefore, the controller 101 must use scram energy to complete cached write operations using the buffers in portion 610 of the write cache 110.

[0065] In other words, at the time of the power-off event, data in portion 610 of write cache 110 has not yet been written to NAND array 108, but will be able to complete the write by using the crash energy, while data in portion 612 of write cache 112 is still safe in the write buffer and those writes can be retried at the next power-on event. Thus, all data written at the time of the power-off event is (or will soon be) safe.

[0066] The size of portion 610 (relative to the total size of write cache 110) and the size of portion 612 (relative to the total size of write cache 110) may be determined based on the count of failed retention capacitors. For example, as the count increases, portion 610 may decrease, which causes portion 612 to increase. As portion 610 continues to decrease in size, portion 610 eventually disappears, leaving the entire write cache 110 represented by portion 612, causing data storage device 100 to operate in write-through mode 604.

[0067] When operating in the normal mode 402 or the hybrid mode 602, if TH1 to TH2 failed holding capacitors (e.g., 3 or 4) are detected, the data storage device 100 transitions to a write-through mode 604, in which the write cache 110 is reallocated into a single portion 612 associated with write-through writes (operating according to the buffer release scheme 330). In other words, the entire write cache 110 (all write buffers in the write cache) is configured to perform only write-through write operations. When operating in the write-through mode 604, upon a power failure event, the controller 101 performs an emergency stop operation as described above with reference to the normal mode 402, except that no running programs need to be completed because the data is safely stored in the non-volatile write cache 110. Therefore, the controller 101 does not require as much power to perform the emergency stop operation.

[0068] When operating in the normal mode 402, the hybrid mode 602, or the write-through mode 604, if TH2 to TH3 failed retention capacitors (e.g., 5 or 6) are detected, the data storage device 100 transitions to the read-only mode 406, which corresponds to the above in Figure 54. When operating in read-only mode 406, the data storage device 100 is restricted from writing any new data to the flash memory 103. This is because there is not enough scram energy left to reliably complete all write operations (due to the failed retention capacitors), and the data is most likely lost upon a power outage event. When operating in read-only mode 406, upon a power outage event, the controller 101 performs the scram operation as described above with reference to normal mode 402, with at least two significant differences. First, since the size of the buffer pool of the write cache 110 (portion 614) is now zero, there are no running programs to complete and no write cache to flush. Therefore, even less scram energy is required to complete the scram operation in read-only mode 406, thereby being performed in a manner consistent with even fewer retention capacitors being available to supply the scram energy during the shutdown period.

[0069] In some implementations, the data storage device 100 can operate in a reduced throughput mode that combines features of modes 404, 602, and 606. For example, when the write cache 110 is divided into two portions 610 and 612 as in mode 602, the size of the write cache 110 can also be reduced as in mode 404. Likewise, when the size of the write cache 110 is reduced as in mode 404, the remaining write buffer of the write cache 110 can be divided into two portions 610 and 612 as in mode 602. Additionally, when in mode 604, the size of the write cache 110 can be reduced. Similarly, when in mode 404, the write buffer can be operated using only write-through operations as in mode 604. In each of the foregoing combinations of features, as the count of failed retention capacitors increases, the size of the write cache 110 may decrease, the proportion of the reduced write cache 110 used for cached writes (as in portion 610) may decrease, and the proportion of the reduced write cache 110 used for write-through writes (as in portion 612) may increase.

[0070] Figure 7 is a flow chart of a retention capacitor failure processing method 700 according to some specific implementations. The method 700 may be managed by instructions stored in a non-transitory computer-readable storage medium (e.g., storage medium 102). The instructions may be included in one or more programs stored in the non-transitory computer-readable storage medium. When executed by one or more processors (e.g., controller 101), the instructions cause the data storage device 100 to perform the method. The instructions may include source code, assembly language code, object code, or any other instruction format that can be interpreted by one or more processors. Some operations in the process may be combined, and the order of some operations may be changed.

[0071] Whenever a retention capacitor failure is detected, the data storage device 100 performs method 700. When performing (702) memory operations at a normal throughput level (normal mode 402), the controller 101 detects (704) a retention capacitor failure. In some specific implementations, this includes receiving a capacitor failure notification from a capacitor health check circuit as described above. In response to the detection, the controller 101 notifies the host 104 of the detected failure and performs (706) one or more quiesce operations (e.g., when in state 408). These quiesce operations include one or more of the following: stop extracting commands from the submission queue, stop extracting new host command processing, end the running host write / read transfer request, flush the write cache 110 (including writing the data in the write cache to the open super block), save FTL metadata (L2P table, etc., similar to an emergency stop operation), optionally abort commands located in the submission queue to avoid command timeouts, and optionally abort commands extracted from the management command queue but not yet started. These quiesce commands may be referred to as housekeeping operations or cleanup operations, and are executed quickly to keep the data intact (minimizing the possibility of losing data) if power loss occurs shortly after a failed retention capacitor is detected.

[0072] Upon completion of the quiescing operation, the controller 101 determines (708) a count of failed retention capacitors. The count includes the retention capacitor failure that caused the notification in the detection operation 704 and all other failed retention capacitors (a total count of failed retention capacitors). In some implementations, this operation includes detecting failed capacitors in the capacitor bank 200 (e.g., by discharging and charging each capacitor to determine if any capacitors are discharging and / or charging too quickly or are not discharging and / or charging at all), and isolating these failed retention capacitors so that the data storage device 100 can continue to operate without these failed retention capacitors reducing the amount of emergency stop energy that can be provided by the remaining functioning retention capacitors.

[0073] In some implementations, after completing the detection and isolation of the failed retention capacitor, the controller 101 may also notify the host 104 that the data storage device 100 has completed the detection and isolation of the failed retention capacitor.

[0074] In some implementations, after completing the detection and isolation of the failed retention capacitors, the controller 101 can update the healthy capacitor bitmap stored in the internal file system in the storage medium 102. This allows the controller 101 to remember which capacitors are faulty so that the controller 101 can continue to shut them down whenever the data storage device 100 is powered on.

[0075] The controller 101 continues to reallocate 710 the write cache 110 based on the count of failed retention capacitors. In some implementations, a static map in firmware (stored in the storage medium 102) provides a reallocation configuration (e.g., the size of the portions 510, 512, 610, and 612) for each possible count of failed retention capacitors, and the controller 101 queries this static map to determine how to reallocate the write cache 110.

[0076] In some implementations, the controller 101 continues to determine (712) whether the size of the write cache is still greater than 0 after the reallocation (in other words, whether the portion 510, 610, or 612 still exists). If so, the controller 101 continues to operate in a reduced throughput mode corresponding to the determined reallocation (e.g., in mode 404, 602, or 604) (714). If not, the controller 101 continues to operate in a read-only mode (e.g., in mode 406) (716).

[0077] FIG. 8A to FIG. 8B is a chart illustrating example benefits of the retention capacitor failure handling scheme described herein according to some specific implementations.

[0078] refer to Fig. 8A In contrast to some conventional storage devices that no longer allow ongoing programming operations after only one failed retention capacitor has been detected, a retention capacitor failure handling scheme as described in the present disclosure may continue to allow ongoing programming operations after one or more (e.g., 1 or 2) failed retention capacitors have been detected (e.g., consistent with any of reduced throughput modes 404, 602, and 604), and then gradually reduce to no longer allowing ongoing programming operations (e.g., consistent with read-only mode 406) after, for example, three failed retention capacitors have been detected.

[0079] refer to Figure 8B, compared to some conventional storage devices that do not limit write performance to 0 MB / s after only one failed retention capacitor has been detected, the retention capacitor failure handling scheme as described in the present disclosure can continue to support write operations up to various threshold counts of failed retention capacitors (but with reduced performance). For example, a data storage device 100 with one or two failed retention capacitors as described in the present disclosure can continue to have a total write performance of 800 MB / s in mode 404 or a total write performance of 1200 MB / s in mode 602, while a data storage device 100 with between three and five retention capacitors as described in the present disclosure can continue to have a total write performance of 300 MB / s in mode 604. While these performance numbers are reduced from a peak performance of 2500 MB / s when all retention capacitors are functioning properly, they are still much higher than the 0 MB / s write performance exhibited by some conventional data storage systems when one or more failed retention capacitors are detected.

[0080] Therefore, the retention capacitor failure handling scheme described in the present application enables the data storage device to be more tolerant to a higher number of failed retention capacitors, reduces the data storage device's reliance on retention capacitor energy in the event of power loss, and thereby improves the performance and overall usable life of the data storage device.

[0081] For convenience, various example embodiments and aspects of the present disclosure are described below. These are provided as examples, without limiting the technology of the present subject. Some of the examples described below are illustrated with respect to the drawings disclosed herein, which are only used for illustrative purposes and do not limit the scope of the present subject technology.

[0082] One or more aspects of the subject technology provide a data storage device 100 comprising: a nonvolatile flash memory (e.g., 103) configured to store data; a controller (e.g., 101) configured to control the nonvolatile memory and communicate with a host (e.g., 104); a write cache (e.g., 110) comprising a write buffer configured to transfer data from the host (e.g., 104) to the nonvolatile flash memory (e.g., 103) during a write operation; and a plurality of retention capacitors (e.g., 200) configured to provide backup power for at least the nonvolatile memory, the controller, and the write cache. A controller (e.g., 101) is configured to: detect (e.g., 704) one or more failed retention capacitors among a plurality of retention capacitors; in response to detecting the one or more failed retention capacitors: perform (e.g., 706) one or more quiescent operations; determine (e.g., 708) a first count of the one or more failed retention capacitors; and based on the first count of the one or more failed retention capacitors, reallocate a write buffer of a write cache for use in one or more subsequent write operations (e.g., transition to mode 404, 406, 602, or 604).

[0083] In some implementations, the controller is configured to reallocate a write buffer of the write cache for use in one or more subsequent write operations by reducing the size of the write cache (e.g., transitioning to mode 404). The controller can be configured to reduce the size of the write cache by an amount based on a first count of the one or more failed retention capacitors (e.g., the higher the count, the greater the reduction in size).

[0084] In some embodiments, the controller is configured to reallocate a write buffer of a write cache by: allocating a first portion (e.g., 510) of the write buffer of the write cache for use in one or more subsequent write operations; and preventing a second portion (e.g., 512) of the write buffer of the write cache from being used in one or more subsequent write operations.

[0085] In some embodiments, the controller is configured to reallocate a write buffer of a write cache based on determining that a first count of one or more failed retention capacitors is below a threshold (e.g., less than TH1); and after performing one or more subsequent write operations, the controller is further configured to: detect (e.g., 704) another one or more failed retention capacitors among the plurality of retention capacitors; and in response to detecting the other one or more failed retention capacitors: perform (e.g., 706) one or more quiesce operations; determine that a second count of the failed retention capacitors satisfies a threshold (e.g., greater than TH1); and based on determining that the second count of the failed retention capacitors satisfies the threshold, transition the non-volatile memory to a read-only mode (e.g., 406).

[0086] In some embodiments, the controller is configured to reallocate write buffers of the write cache based on determining that a first count of one or more failed holding capacitors is below a first threshold (less than TH1); the controller is configured to reallocate write buffers of the write cache by: allocating a first portion (e.g., 610) of the write cache for performing cached write operations; and allocating a second portion (e.g., 612) of the write cache for performing write-through operations; and the controller is further configured to: use one or more buffers in the first portion (e.g., 610) of the write cache to perform a first plurality of cached write operations; and use one or more buffers in the second portion (e.g., 612) of the write cache to perform a first plurality of write-through operations.

[0087] In some implementations, the controller is configured to: allocate the first portion (e.g., 610) of the write cache by setting a size of the first portion (e.g., 610) based on a first count of the one or more failed retention capacitors; and allocate the first portion (e.g., 610) of the write cache by setting a size of the second portion of the write cache equal to the total write cache (e.g., Figure 6 The second portion (e.g., 612) is allocated by subtracting the size of the first portion 610 of the write cache from the size of the write cache 110 in the total write cache. In some implementations, the total write cache can represent the size of all write buffers in the write cache (e.g., 110). The size of the first portion (e.g., 610) of the write cache can represent the size of all write buffers in the first portion (e.g., 610) of the write cache (e.g., 110). The size of the second portion (e.g., 612) of the write cache can represent the size of all write buffers in the second portion (e.g., 612) of the write cache (e.g., 110).

[0088] In some specific implementations, the controller is also configured to: detect a first power-off event of the data storage device when performing a first plurality of cached write operations and a first plurality of direct write operations (for example, in mode 602); and in response to detecting the first power-off event of the data storage device, perform a first plurality of emergency stop operations (for example, in mode 602) while a plurality of retention capacitors provide power to the data storage device, wherein the first plurality of emergency stop operations include: completing the first plurality of cached write operations before powering off the data storage device; and stopping one or more write operations of the first plurality of direct write operations before one or more write operations of the first plurality of direct write operations are completed.

[0089] In some implementations, after performing the first plurality of cached write operations and the first plurality of write-through operations (e.g., in mode 602), the controller is further configured to: detect (e.g., 704) one or more failed retention capacitors from the plurality of retention capacitors; and in response to detecting the one or more failed retention capacitors: perform (e.g., 706) one or more quiesce operations; determine that a second count of failed retention capacitors satisfies a first threshold and is below a second threshold (at Figure 6 1 and 12); based on determining that the second count of failed retention capacitors satisfies the first threshold and is below the second threshold, reallocating all write caches for performing write-through operations (e.g., in portion 612 of mode 604); and after allocating all write caches for performing write-through operations, performing a second plurality of write-through operations using one or more write buffers in the write cache. In some implementations, all write caches can represent all write buffers in a write cache (e.g., 110).

[0090] In some specific implementations, the controller is also configured to: detect a second power-off event of the data storage device when performing a second plurality of direct write operations (e.g., in mode 604); and in response to detecting the second power-off event of the data storage device, perform a second plurality of emergency stop operations (e.g., in mode 604) while a plurality of retention capacitors provide power to the data storage device, wherein the second plurality of emergency stop operations include: stopping one or more write operations of the second plurality of direct write operations before one or more write operations of the second plurality of direct write operations are completed.

[0091] In some embodiments, after performing a second plurality of write-through operations, the controller is further configured to: detect (e.g., 704) a second additional one or more failed retention capacitors among the plurality of retention capacitors; and in response to detecting the second additional one or more failed retention capacitors: perform (e.g., 706) one or more quiet operations; determine that a third count of failed retention capacitors satisfies a second threshold (greater than or equal to TH2); and based on determining that the third count of failed retention capacitors satisfies the second threshold, transition the non-volatile memory to a read-only mode (e.g., mode 406).

[0092] In some embodiments, the controller is configured to reallocate write buffers of the write cache based on determining that a first count of one or more failed retention capacitors satisfies a first threshold (e.g., greater than or equal to TH1); the controller is configured to reallocate write buffers of the write cache by allocating all write caches for performing write-through operations (e.g., mode 604); and after allocating all write caches for performing write-through operations, the controller is configured to perform multiple write-through operations using one or more buffers in the write cache (e.g., in portion 612).

[0093] In some implementations, the one or more quiesce operations include one or more of: completing one or more running programs; flushing a write cache; flushing one or more logical-to-physical tables; and flushing one or more data structures.

[0094] In some implementations, the controller is further configured to cause the one or more failed holding capacitors to be isolated in response to detecting the one or more failed holding capacitors.

[0095] In other aspects, the method is implemented using one or more controllers for one or more storage devices. The method may include the operations described above with reference to the data storage device (e.g., 100), the controller (e.g., 101), the write cache (e.g., 110), the retention capacitor (e.g., 200), and the mode (e.g., 402-408 and 602-604).

[0096] In other aspects, a system may include components for the operations described above with reference to the data storage device (e.g., 100), the controller (e.g., 101), the write cache (e.g., 110), the retention capacitor (e.g., 200), and the modes (e.g., 402-408 and 602-604).

[0097] In one or more aspects, a method includes one or more methods, operations, or parts thereof described herein. In one or more aspects, a device includes one or more memories and one or more processors, the one or more processors being configured to cause the execution of one or more methods, operations, or parts thereof described herein. In one or more aspects, a device includes a component suitable for executing one or more methods, operations, or parts thereof described herein. In one or more aspects, a hardware device includes a circuit configured to execute one or more methods, operations, or parts thereof described herein. In one or more aspects, a device includes a component operable to execute one or more methods, operations, or parts thereof described herein. In one or more aspects, a non-transitory machine-readable storage medium (e.g., one or more memories and / or one or more registers) stores instructions that, when executed by one or more processors, cause one or more processors to execute one or more methods, operations, or parts thereof described herein.

[0098] Other examples of the subject technology include various subsets of the above examples combined in various forms or otherwise rearranged.

[0099] In some examples, items such as various illustrative blocks, modules, components, methods, operations, instructions, and algorithms may have been described generally in terms of their functionality in order to illustrate the interchangeability of hardware and software. In some examples, whether this functionality is implemented as hardware, software, or a combination of hardware and software depends on the specific application and the design constraints imposed on the overall system. A skilled person may implement the described functionality in different ways for each specific application.

[0100] Titles and subtitles, if any, are used for convenience only and do not limit the present invention. The word "exemplary" is used to mean used as an example or illustration. Any specific implementation described herein as an "example" is not necessarily to be construed as being more preferred or advantageous than other specific implementations. Relational terms such as first and second may be used simply to facilitate understanding without necessarily requiring or implying any actual relationship or order between elements or actions, and without necessarily requiring or implying that they have different characteristics unless otherwise stated.

[0101] Phrases such as an aspect, this aspect, another aspect, some aspects, one or more aspects, a specific implementation, this specific implementation, another specific implementation, some specific implementations, one or more specific implementations, an embodiment, this embodiment, another embodiment, some embodiments, one or more embodiments, a configuration, this configuration, another configuration, some configurations, one or more configurations, subject technology, disclosure, the present disclosure, other variations thereof, etc., are for convenience, and do not imply that the disclosure associated with such phrases is necessary for the subject technology, or that such disclosures are applicable to all configurations of the subject technology. The disclosure associated with such phrases may be applicable to all configurations, or one or more configurations. The disclosure associated with such phrases may provide one or more examples. Phrases such as an aspect or some aspects may refer to one or more aspects, and vice versa, and this is similarly applicable to other aforementioned phrases.

[0102] The phrase "at least one" preceding a series of items, where the terms "and" or "or" are used to separate any of the items, modifies the entire list, rather than each member of the list. The phrase "at least one" does not require selection of at least one item; rather, the phrase allows for a meaning that includes at least one of any one item, and / or at least one of any combination of items, and / or at least one of each item. For example, each of the phrases "at least one of A, B, and C" and "at least one of A, B, or C" may refer to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0103] The expression of "first element", "second element" and / or "third element" should be understood as one of the first element, the second element and the third element or any or all combinations of the first element, the second element and the third element. For example, A, B and / or C may refer to only A; only B; only C; any one or some combination of A, B and C; or all of A, B and C. In addition, the expression "element A / element B" may be understood as element A and / or element B.

[0104] In one or more aspects, unless otherwise stated, the terms "between" and "among" may be used interchangeably for convenience only. For example, the expression "between a plurality of elements" may be understood as among a plurality of elements. In another example, the expression "among a plurality of elements" may be understood as between a plurality of elements. In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two.

[0105] In one or more aspects, unless otherwise stated, the terms "each other" and "one another" may be used interchangeably for convenience only. For example, the expression "different from each other" may be understood as different from each other. In another example, the expression "different from each other" may be understood as different from each other. In one or more examples, the number of elements involved in the foregoing statements may be two. In one or more examples, the number of elements involved in the foregoing statements may be more than two.

[0106] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate, link or drive together in different ways. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a common dependency or correlation relationship. In one or more aspects, the components of each device according to the various embodiments of the present disclosure are operatively coupled and configured.

[0107] Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It should also be understood that, unless otherwise explicitly defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, for example, and should not be interpreted in an idealized or overly formal sense.

[0108] It should be understood that the specific order or hierarchy of the disclosed steps, operations or processes is an illustration of an exemplary method. It should be understood that, unless otherwise explicitly stated, the specific order or hierarchy of steps, operations or processes can be performed in different orders, except that steps and / or operations must occur in a specific order. Some of the steps, operations or processes can be performed simultaneously. The attached method claims (if present) present the elements of each step, operation or process in a sample order, and are not intended to be limited to the specific order or hierarchy presented. These can be performed serially, linearly, in parallel or in different orders. It should be understood that the instructions, operations and systems described can usually be integrated together in a single software / hardware product or encapsulated in multiple software / hardware products.

[0109] When describing a temporal relationship, when the temporal order is described as, for example, "after", "subsequently", "next", "before", "in front of", "before...", etc., unless more restrictive terms such as "exactly", "immediately" or "just" are used, discontinuous or non-sequential situations may be included.

[0110] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element may be the second element, and similarly, the second element may be the first element. In addition, without departing from the scope of the present disclosure, the first element, the second element, etc. may be arbitrarily named according to the convenience of those skilled in the art.

[0111] When describing elements of the present disclosure, terms such as "first", "second", "A", "B", "(a)", "(b)", etc. may be used. These terms are intended to distinguish corresponding elements from other elements, and these terms are not used to limit the nature, basis, order or number of the elements.

[0112] In one or more examples, unless otherwise specified, when an element is “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or may be indirectly connected or coupled to the other element with one or more intervening elements disposed or interposed between the two elements.

[0113] The present disclosure is provided to enable those skilled in the art to practice the various aspects described herein. In some instances, when a detailed description of a well-known function or configuration may unnecessarily obscure various aspects of the present disclosure, its detailed description may be omitted. The present disclosure provides various examples of the subject technology, and the subject technology is not limited to these examples. Various modifications of these aspects are apparent to those skilled in the art, and the principles described herein may be applied to other aspects.

[0114] Unless otherwise stated, the same reference numerals may always refer to the same elements even when the same reference numerals are shown in different figures. In one or more aspects, the same elements (or elements with the same names) in different figures may have the same or substantially the same functions and properties unless otherwise stated. In addition, the names of the corresponding elements used in the following description are selected for convenience only and may therefore be different from those used in the actual product.

[0115] The shapes, sizes, areas, ratios, numbers and the like disclosed in the drawings for describing specific implementations of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the illustrated details.

[0116] When the terms "comprise", "have", "include", "contain", "compose", etc. are used, one or more other elements may be added unless terms such as "only" are used. The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the scope of the disclosure. The terms used herein are only used to describe example embodiments and are not intended to limit the scope of the disclosure. Unless the context clearly indicates otherwise, terms in the singular may include plural forms. Without further limitation, an element beginning with "a", "an", "the", or "said" does not exclude the presence of additional elements.

[0117] In one or more aspects, elements, features, or corresponding information (e.g., levels, ranges, dimensions, sizes, etc.) are interpreted as including an error or tolerance range, even if no explicit description of such an error or tolerance range is provided. The error or tolerance range may be caused by various factors (e.g., process factors, internal or external influences, etc.). In addition, although the present disclosure may provide many example ranges and values, these are non-limiting examples, and other ranges and values ​​are within the scope of the subject technology.

[0118] All structural and functional equivalents of the elements throughout the various aspects described in this disclosure that are known or later known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, the content disclosed herein is not intended to be contributed to the general public, regardless of whether this disclosure is explicitly recited in the claims. Pursuant to the sixth paragraph of 35 U.S.C. §112, no claim element will be interpreted unless the phrase "means for..." is used to expressly recite the element, or in the case of a method claim, the phrase "step for..." is used to recite the element.

[0119] The title, background technology, figure description, abstract, and drawings are hereby incorporated into the present disclosure and are provided as illustrative examples of the present disclosure rather than as limiting descriptions. It should be understood that the content submitted is not used to limit the scope or meaning of the claims. In addition, in the specific implementation, it can be seen that the description provides illustrative examples, and various features are grouped together in various specific implementations for the purpose of simplifying the present disclosure. This method of the present disclosure should not be interpreted as reflecting such an intention: the subject matter claimed requires more features than those explicitly stated in each claim. On the contrary, as reflected in the attached claims, the inventive subject matter lies in less than all the features of a single disclosed configuration or operation. The attached claims are hereby incorporated into the specific implementation, wherein each claim is independently a subject matter claimed separately.

[0120] The description provided in the background section should not be considered as prior art merely because it is mentioned in or associated with the background section. The background section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention.

[0121] In addition to the description provided in the Summary of the Invention section, other systems, methods, features, and advantages will be or will become apparent to one skilled in the art upon examination of this disclosure. All such additional systems, methods, features, and advantages are within the scope of this disclosure and are protected by the following claims. Nothing in the Summary of the Invention section should be construed as a limitation on those claims. Other aspects and advantages are also discussed herein.

[0122] The claims are not intended to be limited to the aspects described herein, but are intended to be given the full scope consistent with the language of the claims and to encompass all legal equivalents. Nevertheless, none of the claims is intended to include subject matter that fails to satisfy the requirements of applicable patent law, nor should it be interpreted in such a manner.

Claims

1. A data storage device, comprising: a non-volatile memory configured to store data; a controller configured to control the nonvolatile memory and communicate with a host; a write cache comprising a write buffer configured to transfer data from the host to the non-volatile memory during a write operation; and a plurality of retention capacitors configured to provide backup power for at least the nonvolatile memory, the controller, and the write cache, The controller is configured as follows: detecting one or more failed holding capacitors among the plurality of holding capacitors; as well as In response to detecting the one or more failed holding capacitors: Perform one or more silent operations; determining a first count of the one or more failed holding capacitors; and Based on the first count of the one or more failed retention capacitors, the write buffer of the write cache is reallocated for use in one or more subsequent write operations. 2 . The data storage device of claim 1 , wherein the controller is configured to reallocate the write buffer of the write cache for use in the one or more subsequent write operations by reducing the size of the write cache. 3 . The data storage device of claim 2 , wherein the controller is configured to reduce the size of the write cache by an amount based on the first count of the one or more failed retention capacitors.

4. The data storage device of claim 1 , wherein the controller is configured to reallocate the write buffer of the write cache by: allocating a first portion of the write buffer of the write cache for use in the one or more subsequent write operations; and A second portion of the write buffer of the write cache is prevented from being used in the one or more subsequent write operations.

5. The data storage device according to claim 4, wherein: the controller configured to reallocate the write buffer of the write cache based on determining that the first count of the one or more failed retention capacitors is below a threshold; as well as After performing the one or more subsequent write operations, the controller is further configured to: detecting one or more failed additional holding capacitors of the plurality of holding capacitors; and In response to detecting the one or more failed holding capacitors: Perform one or more silent operations; determining that a second count of failed holding capacitors satisfies the threshold; as well as Based on determining that the second count of failed retention capacitors satisfies the threshold, the nonvolatile memory is transitioned to a read-only mode.

6. The data storage device according to claim 1, wherein: the controller configured to reallocate the write buffer of the write cache based on determining that the first count of the one or more failed retention capacitors is below a first threshold; The controller is configured to reallocate the write buffer of the write cache by: allocating a first portion of the write cache for use in performing cached write operations; and allocating a second portion of the write cache for performing a write-through operation; and The controller is also configured to: performing a first plurality of cached write operations using one or more buffers in the first portion of the write cache; as well as A first plurality of write-through operations are performed using one or more buffers in the second portion of the write cache.

7. The data storage device according to claim 6, wherein the controller is configured to: allocating the first portion by setting a size of the first portion of the write cache based on the first count of the one or more failed retention capacitors; and The second portion of the write cache is allocated by setting the size of the second portion equal to the total size of the write cache minus the size of the first portion of the write cache.

8. The data storage device according to claim 6, wherein the controller is further configured to: detecting a first power failure event of the data storage device while performing the first plurality of cached write operations and the first plurality of write-through operations; as well as In response to detecting the first power-off event of the data storage device, performing a first plurality of emergency stop operations while the plurality of retention capacitors provide power to the data storage device, wherein the first plurality of emergency stop operations include: before powering off the data storage device, completing the first plurality of cached write operations; as well as Before one or more write operations of the first plurality of write-through operations are completed, the one or more write operations of the first plurality of write-through operations are stopped.

9. The data storage device according to claim 6, wherein: After performing the first plurality of cached write operations and the first plurality of write-through operations, the controller is further configured to: detecting one or more failed additional holding capacitors of the plurality of holding capacitors; as well as In response to detecting the one or more failed holding capacitors: Perform one or more silent operations; determining that a second count of failed holding capacitors meets the first threshold and is below a second threshold; reallocating all of the write cache to perform write-through operations based on determining that the second count of failed retention capacitors meets the first threshold and is below the second threshold; and After all of the write cache is allocated for performing write-through operations, a second plurality of write-through operations is performed using one or more write buffers in the write cache.

10. The data storage device of claim 9, wherein the controller is further configured to: While performing the second plurality of write-through operations, detecting a second power-off event of the data storage device; and In response to detecting the second power-off event of the data storage device, performing a second plurality of emergency stop operations while the plurality of retention capacitors provide power to the data storage device, wherein the second plurality of emergency stop operations include: Before one or more write operations of the second plurality of write-through operations are completed, the one or more write operations of the second plurality of write-through operations are stopped.

11. The data storage device according to claim 9, wherein: After performing the second plurality of write-through operations, the controller is further configured to: detecting a second additional one or more failed holding capacitors of the plurality of holding capacitors; as well as In response to detecting the second additional one or more failed holding capacitors: Perform one or more silent operations; determining that a third count of failed holding capacitors satisfies the second threshold; as well as Based on determining that the third count of failed retention capacitors satisfies the second threshold, the nonvolatile memory is transitioned to a read-only mode.

12. The data storage device of claim 1, wherein: the controller configured to reallocate the write buffer of the write cache based on determining that the first count of the one or more failed retention capacitors satisfies a first threshold; The controller is configured to reallocate the write buffer of the write cache by allocating all of the write cache for performing a write-through operation; and After allocating all of the write cache to perform write-through operations, the controller is configured to perform a plurality of write-through operations using one or more buffers in the write cache.

13. The data storage device of claim 1 , wherein the one or more quiesce operations include one or more of the following: Complete one or more running programs; flushing the write cache; Refresh one or more logical-to-physical tables; and Refreshes one or more data structures.

14. The data storage device of claim 1, wherein the controller is further configured to cause the one or more failed retention capacitors to be isolated in response to detecting the one or more failed retention capacitors.

15. A method of operating a data storage device, the method comprising: At a data storage device including a nonvolatile memory configured to store data, a controller configured to control the nonvolatile memory and to communicate with a host, a write cache including a write buffer configured to transfer data from the host to the nonvolatile memory during a write operation, and a plurality of retention capacitors configured to provide backup power for at least the nonvolatile memory, the controller, and the write cache: detecting one or more failed holding capacitors among the plurality of holding capacitors; as well as In response to detecting the one or more failed holding capacitors: Perform one or more silent operations; determining a first count of the one or more failed holding capacitors; and Based on the first count of the one or more failed retention capacitors, the write buffer of the write cache is reallocated for use in one or more subsequent write operations.

16. The method of claim 15, wherein reallocating the write buffer of the write cache comprises: allocating a first portion of the write buffer of the write cache for use in the one or more subsequent write operations; as well as A second portion of the write buffer of the write cache is prevented from being used in the one or more subsequent write operations.

17. The method of claim 15, wherein: Reallocating the write buffer of the write cache comprises: base said reallocation of said write buffers of said write cache on determining that said first count of said one or more failed holding capacitors is below a first threshold; allocating a first portion of the write cache for use in performing cached write operations; and allocating a second portion of the write cache for performing a write-through operation; and The method further comprises: performing a first plurality of cached write operations using one or more buffers in the first portion of the write cache; and A first plurality of write-through operations are performed using one or more buffers in the second portion of the write cache.

18. The method according to claim 17, further comprising: detecting a first power failure event of the data storage device while performing the first plurality of cached write operations and the first plurality of write-through operations; as well as In response to detecting the first power-off event of the data storage device, performing a first plurality of emergency stop operations while the plurality of retention capacitors provide power to the data storage device, wherein the first plurality of emergency stop operations include: before powering off the data storage device, completing the first plurality of cached write operations; as well as Before one or more write operations of the first plurality of write-through operations are completed, the one or more write operations of the first plurality of write-through operations are stopped.

19. The method according to claim 17, further comprising: After performing the first plurality of cached write operations and the first plurality of write-through operations: detecting one or more failed additional holding capacitors of the plurality of holding capacitors; as well as In response to detecting the one or more failed holding capacitors: Perform one or more silent operations; determining that a second count of failed holding capacitors meets the first threshold and is below a second threshold; as well as reallocating all of the write cache to perform write-through operations based on determining that the second count of failed retention capacitors meets the first threshold and is below the second threshold; and After all of the write cache is allocated for performing write-through operations, a second plurality of write-through operations is performed using one or more write buffers in the write cache.

20. A data storage device, the data storage device comprising: a non-volatile memory configured to store data; a controller configured to control the nonvolatile memory and communicate with a host; a write cache comprising a write buffer configured to transfer data from the host to the non-volatile memory during a write operation; and a plurality of retention capacitors configured to provide backup power for at least the nonvolatile memory, the controller, and the write cache, The controller comprises: means for detecting a failed one or more of the plurality of holding capacitors; and means for performing one or more quiescent operations in response to detecting the one or more failed holding capacitors; means for determining a first count of the one or more failed holding capacitors in response to detecting the one or more failed holding capacitors; and Means for reallocating the write buffer of the write cache for use in one or more subsequent write operations based on the first count of the one or more failed retention capacitors.

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