Pulse arrival time measuring system and method

Abstract

The invention relates to the field of pulse arrival time measurement, in particular to a pulse arrival time measurement system and method. Digital signals converted from pulse signals are divided into three paths, CLK time, first pulse time and second pulse time are measured through the CLK unit, the FPGA unit and the TDC unit respectively, accordingly, more accurate pulse arrival time is calculated, the accuracy of the pulse arrival time is within 1 ns, judgment of a rising edge and a falling edge is achieved through the DA unit, and the accuracy of the pulse arrival time is improved. Therefore, the accurate arrival time of each rising edge and each falling edge can be accurately calculated in combination with the calculated pulse arrival time, the high-precision measurement of the pulse arrival time is realized through the TDC unit, and meanwhile, the FPGA unit is matched to perform advantage complementation so as to complete the measurement of the pulse arrival time of various pulse widths; the problem that the precision of measuring the pulse arrival time by the existing middle-end and low-end FPGAs is difficult to reach within 1ns is solved.

Description

Technical Field

[0001] The invention relates to the field of pulse arrival time measurement, and in particular to a pulse arrival time measurement system and method. Background Art

[0002] The main tasks of radar include target detection and target parameter measurement, accurate extraction of radar pulse parameters, target characteristic parameters that can only be obtained in complex electromagnetic environments, improving target classification and recognition capabilities, and improving resolution and observation accuracy in multi-target situations, which are important for determining target attributes and measuring target events.

[0003] In the current common architecture, there are two main ways to measure arrival time (TOA) in FPGA pipeline. The first is the direct counting method, which requires clock multiplication. Although the principle of the direct counting method is relatively simple, it is difficult for low-end and mid-end FPGAs to multiply GHz-level clock signals. Although high-end FPGAs can implement the algorithm, the cost is too high. Secondly, based on the direct counting method, an algorithm based on phase shift measurement is designed. Its advantage is that the phase-locked loop module does not need to be directly multiplied to the GHz level. The equivalent GHz clock signal is achieved by using multiple clock signals with a fixed phase difference in sequence. Although this also makes the phase-locked loop modules of most low-end and mid-end FPGAs available, reducing the cost of the entire measurement system, it is difficult to achieve an accuracy of less than 1ns. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a pulse arrival time measurement system and method, which solves the problem that the accuracy of pulse arrival time measurement by existing mid- and low-end FPGAs is difficult to reach within 1 ns.

[0005] To achieve the above object, the present invention provides the following technical solutions: A pulse arrival time measurement system includes an antenna for receiving a radio frequency signal and converting it into an intermediate frequency signal, and a signal conversion unit for detecting the intermediate frequency signal and converting it into a digital signal, and also includes a clock circuit for providing a clock signal, and also includes: A DA unit for acquiring a digital signal and performing threshold determination on the rising and falling edges of the digital signal; A CLK unit for counting the time corresponding to the rising edge and falling edge of the digital signal in the DA unit, and outputting the CLK time corresponding to the arrival of the rising edge and the falling edge; An FPGA unit for acquiring a digital signal, and sending a STOP signal to the TDC unit upon receiving the digital signal, marking the sending time of the STOP signal as the first pulse arrival time, and calculating the arrival time of each rising edge and falling edge according to the second pulse time and the CLK time; The TDC unit is used to obtain the digital signal, and sends a START signal to the FPGA unit when receiving the digital signal, and calculates the time interval between the START signal and the STOP signal to obtain the second pulse time.

[0006] Preferably, the signal conversion unit includes a detector for detecting the intermediate frequency signal to obtain a demodulated signal, and also includes an A / D circuit for converting the demodulated signal into a digital signal, the A / D circuit includes an encoder U4, the encoder U4 is connected to a comparator U1 for signal input, the 8th and 1st pins of the comparator U1 are provided with a resistor R5, a capacitor C1, a resistor R1, a capacitor C2 and a resistor R6 for forming a loop, the demodulated signal is input from both ends of the resistor R1 respectively, a resistor R7 is connected between the 8th and 5th pins of the comparator U1, a resistor R8 is connected between the 1st and 4th pins of the comparator U1, a resistor R11 is connected between the 5th pin of the comparator U1 and the encoder U4, and a resistor R12 is also connected between the 4th pin of the comparator U1 and the encoder U4.

[0007] Preferably, the DA unit includes a comparator U7, pin 2 of the comparator U7 is connected to a resistor R20 and a capacitor C35 in sequence, pin 3 of the comparator U7 is connected to a resistor R19 and a capacitor C34 in sequence, a resistor R25 is connected between pin 2 and pin 6 of the comparator U7, pin 6 of the comparator U7 is connected to a comparator U10, a Zener diode D5 is connected between pin 6 of the comparator U7 and pin 3 of the comparator U10, pin 5 of the comparator U10 is connected to a chip U9 for outputting rising and falling edges, the chip U9 is connected to the FPGA unit and the encoder U4, and pin 1 of the comparator U10 is connected to a chip U5.

[0008] Preferably, the TDC unit includes a TDC chip U14 connected to the FPGA unit, and resistors R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54 and R55 connected to corresponding ports are arranged between the TDC chip U14 and the FPGA unit. The FPGA unit is also connected to a TDC chip U12, and pins 1 and 2 of the TDC chip U12 are connected to resistor R30, a crystal oscillator Y2, a resistor R29, a capacitor C52, a capacitor C53 and a resistor R131, and pin 1 of the TDC chip U12 is connected to an atomic clock.

[0009] Preferably, the clock circuit includes a clock buffer U15, a resistor R57 is connected between pins 3 and 4 of the clock buffer U15, a capacitor C67, a resistor R56 and a capacitor C68 are connected in sequence between pins 6 and 7 of the clock buffer U15, a resistor R58 and a resistor R60 connected in parallel with capacitor C67, resistor R56 and capacitor C68 are also connected in series between pins 6 and 7 of the clock buffer U15, the resistor R58 and the resistor R60 are connected in series to pin 8 of the clock buffer U15 and capacitor C69, the FPGA unit is also connected to a chip U16, and the chip U16 is connected to a resistor R61, a capacitor C72, a coil L3, a capacitor C78 and a capacitor C80.

[0010] Preferably, it also includes an FMC circuit connected to the FPGA unit, and the FMC circuit includes an interface JIA, an interface JIB and an interface JIC connected to the FPGA unit.

[0011] Preferably, it also includes a storage circuit connected to the FPGA unit, the storage circuit includes a DDR chip U18 connected to the FPGA unit, the B2 pin of the DDR chip is connected with capacitors C90, C92, C94, C96, C97, C98, C99 and C100 in sequence, the DDR chip U18 is connected with a control chip U19, and resistors R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77 are connected between the DDR chip U18 and the control chip U19. 7. R78, R79, R80, R81, R82, R83, R84, R85, R86 and R87, capacitor C107, resistor R92 and resistor R91 are connected to pin 1 of the control chip U19, capacitor C105 and capacitor C108 are connected in parallel between pin 2 and pin 4 of the control chip U19, capacitor C102, capacitor C104, capacitor C106 and capacitor C113 are connected in parallel between pin 3 and pin 6 of the control chip U19, resistor R93 is connected between pin 9 and pin 10 of the control chip U19, and capacitor C115 is connected between pin 8 and pin 10 of the control chip U19.

[0012] Preferably, a power supply circuit for changing the input voltage is further included, and the power supply circuit includes a voltage adjustment chip U26, and the voltage adjustment chip U23 and the voltage adjustment chip U24 are connected to the voltage adjustment chip U26.

[0013] The present invention also provides a method for measuring pulse arrival time, the method comprising the following steps: S1, obtain the pulse signal and convert it into a digital signal, and copy the digital signal into 3 channels; S2, input one of the digital signals into the DA unit, and determine the CLK time corresponding to the rising edge and falling edge of the digital signal according to the rising edge and falling edge determination rules of the FPGA unit; S3, inputting another digital signal into the FPGA unit, the FPGA unit saves the corresponding first pulse arrival time when detecting the digital signal, and outputs a STOP signal of the first pulse time including the difference between the first pulse arrival time and the CLK time; S4, input the last digital signal to the TDC unit, the TDC unit saves the corresponding second pulse arrival time when detecting the digital signal, and outputs a START signal of the second pulse time including the difference between the first pulse arrival time and the second pulse arrival time; S5. Calculate the pulse arrival time corresponding to the rising edge and the falling edge according to the CLK time, the first pulse time and the second pulse time and output them; the calculation formula of the pulse arrival time is: ; In the above formula, Indicates the pulse arrival time corresponding to the rising edge and falling edge, Indicates the CLK time corresponding to the rising edge and falling edge, and Represent the first pulse arrival time and the second pulse time respectively.

[0014] Preferably, the detection of the CLK time is obtained by counting with an atomic clock.

[0015] Compared with the prior art, the present invention provides a pulse arrival time measurement system and method, which has the following beneficial effects: 1. The present invention divides the digital signal converted from the pulse signal into three paths, and respectively measures the CLK time, the first pulse time and the second pulse time through the CLK unit, the FPGA unit and the TDC unit, so as to calculate a more accurate pulse arrival time with an accuracy of less than 1ns, so that the measurement system can achieve the purpose of high-precision measurement of pulse arrival time while meeting the low cost requirement.

[0016] 2. The present invention realizes the judgment of rising edge and falling edge through DA unit, so as to combine the pulse arrival time calculated by CLK unit, FPGA unit and TDC unit to accurately calculate the exact arrival time of each rising edge and falling edge.

[0017] 3. The present invention realizes high-precision measurement of pulse arrival time through the TDC unit, and cooperates with the FPGA unit to realize the measurement of the rising edge and falling edge of wide pulses, thereby complementing each other's advantages to complete the measurement of pulse arrival time of various pulse widths.

[0018] 4. The present invention multiplies the atomic clock into clock signals of different frequencies through a clock circuit, thereby being able to adjust the frequency of the clock signal according to the frequency requirement of the clock signal of the measurement system while ensuring the accuracy of the clock signal.

[0019] 5. The present invention provides a modular I / O interface through the FMC circuit, interface JIA, interface JIB and interface JIC, simplifies the design and improves the reuse rate, supports high-speed signal transmission, can be used to connect various FMC daughter boards, and allows multiple functions to be realized through different daughter boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 It is a structural block diagram of the pulse arrival time measurement system of the present invention; Figure 2 is a circuit diagram of the comparator U1 of the present invention; Figure 3 is a circuit diagram of the encoder U4 of the present invention; Figure 4 is a circuit diagram of the comparator U7 of the present invention; Figure 5 is a circuit diagram of the comparator U10 of the present invention; Figure 6 This is a circuit diagram of the chip U9 of the present invention; Figure 7 is a circuit diagram of the chip U5 of the present invention; Figure 8 is a circuit diagram of the TDC chip U14 of the present invention; Fig. 9 It is a partial circuit diagram of the TDC unit of the present invention; Fig.10 is a circuit diagram of the TDC chip U12 of the present invention; Fig.11 is a circuit diagram of a clock buffer U15 of the present invention; Fig.12 This is a circuit diagram of the chip U16 of the present invention; Fig.13 A circuit diagram of the interface JIA of the present invention; Fig.14 A circuit diagram of the interface JIB of the present invention; Fig.15 It is a circuit diagram of the interface JIC of the present invention; Fig.16 This is a circuit diagram of the DDR chip U18 of the present invention; Fig.17 It is a partial circuit diagram of the FPGA unit of the present invention; Fig.18 This is a circuit diagram of the control chip U19 of the present invention; Fig.19 is a circuit diagram of the voltage regulating chip U23 of the present invention; Fig. 20 is a circuit diagram of the voltage adjustment chip U24 of the present invention; Fig.21 is a flow chart of the pulse arrival time measurement method of the present invention; Fig. 22 This is the working diagram of the TDC unit.

[0021] In the figure: 1. antenna; 2. signal conversion unit; 21. detector; 22. A / D circuit; 3. clock circuit; 4. DA unit; 5. CLK unit; 6. FPGA unit; 7. TDC unit; 8. FMC circuit; 9. storage circuit; 10. power supply circuit. DETAILED DESCRIPTION

[0022] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods, so that the implementation process of how the present application uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0023] Those skilled in the art can understand that all or part of the steps in the following embodiments can be completed by instructing the relevant hardware through a program, so the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0024] In order to solve the problem that the accuracy of pulse arrival time measurement by existing mid- and low-end FPGAs is difficult to reach within 1ns, the present invention provides a pulse arrival time measurement system, which improves the existing FPGA pipeline-type arrival time measurement method, and neither uses a multiplied GHz-level clock signal method nor is it based on a phase shift measurement algorithm. Instead, the digital signal generated by pulse signal conversion is divided into three paths, and the CLK time is obtained through a DA unit 4, the first pulse arrival time and the first pulse time are obtained through an FPGA unit 6, and the second pulse time is obtained through a TDC unit 7. Finally, based on the CLK time, the first pulse time and the second pulse time, the pulse arrival time of each rising edge and falling edge with an accuracy within 1ns is calculated, such as Figure 1As shown, the measurement system includes an antenna 1 for receiving a radio frequency signal and converting it into an intermediate frequency signal, and a signal conversion unit 2 for detecting the intermediate frequency signal and converting it into a digital signal, and also includes a clock circuit 3 for providing a clock signal, and also includes: A DA unit 4 for acquiring a digital signal and performing threshold determination on the rising and falling edges of the digital signal; there are multiple ways to set the threshold value, including a fixed threshold value, a threshold value formed according to the average amplitude of external interference, a threshold value formed on the basis of obtaining some prior information on the statistical distribution of interference, and a threshold value formed for a statistical hypothesis test of distribution freedom when there is no prior information on the statistical distribution of interference, etc., which will not be described in detail here, and the threshold value is often set in conjunction with an FPGA unit 6; a CLK unit 5 for counting the time corresponding to the rising and falling edges of the digital signal in the DA unit 4, and outputting the CLK time corresponding to the arrival of the rising and falling edges; The FPGA unit 6 is used to obtain the digital signal, and sends a STOP signal to the TDC unit 7 when receiving the digital signal, and marks the sending time of the STOP signal as the first pulse arrival time, and calculates the arrival time of each rising edge and falling edge according to the second pulse time and the CLK time. After comparing the measurement accuracy with the high-end FPGA, it is found that after the FPGA unit 6 obtains the CLK time, the first pulse arrival time and the second pulse time, the pulse arrival time with an accuracy within 1ns can be calculated according to the corresponding calculation rules, thereby achieving the purpose of measuring the pulse arrival time with higher accuracy with a lower cost measurement system; the TDC unit 7 is used to obtain the digital signal, and sends a START signal to the FPGA unit 6 when receiving the digital signal, and calculates the time interval between the START signal and the STOP signal to obtain the second pulse time. Fig. 22 This is the working diagram of the TDC unit. The TDC unit 7 measures the pulse time with high accuracy. However, when measuring the pulse time, it is only applicable to the case where the pulse width is small. Therefore, it cooperates with the FPGA unit 6 and CLK unit 5 with poor accuracy to finally achieve the accurate prediction of the pulse arrival time within 1ns. According to the detection comparison of higher-precision pulse measurement equipment, the measurement accuracy of this measurement system reaches 25 picoseconds.

[0025] The signal conversion unit 2 needs to detect the intermediate frequency signal to obtain a demodulated signal, and convert the demodulated signal into a digital signal. The following provides a specific circuit structure of the signal conversion unit 2 to achieve this function. Figure 2 and Figure 3As shown, the signal conversion unit 2 includes a detector 21 for detecting the intermediate frequency signal to obtain a demodulated signal, and also includes an A / D circuit 22 for converting the demodulated signal into a digital signal. The A / D circuit 22 includes an encoder U4, and the encoder U4 is connected to a comparator U1 for signal input. Pins 8 and 1 of the comparator U1 are provided with a resistor R5, a capacitor C1, a resistor R1, a capacitor C2 and a resistor R6 for forming a loop. The demodulated signal is input from both ends of the resistor R1 respectively, and a resistor R7 is connected between pins 8 and 5 of the comparator U1, a resistor R8 is connected between pins 1 and 4 of the comparator U1, a resistor R11 is connected between pin 5 of the comparator U1 and the encoder U4, and a resistor R12 is further connected between pin 4 of the comparator U1 and the encoder U4.

[0026] The DA unit 4 realizes the judgment of the rising edge and the falling edge in the digital signal, so that the CLK unit 5, the FPGA unit 6 and the TDC unit 7 cooperate with each other to judge the arrival time of the corresponding rising edge and the falling edge. The circuit structure of the DA unit 4 is provided below. Figure 4-Figure 7 As shown, the DA unit 4 includes a comparator U7, and the pin 2 of the comparator U7 is connected to a resistor R20 and a capacitor C35 in sequence, the pin 3 of the comparator U7 is connected to a resistor R19 and a capacitor C34 in sequence, a resistor R25 is connected between the pin 2 and the pin 6 of the comparator U7, the pin 6 of the comparator U7 is connected to a comparator U10, a Zener diode D5 is connected between the pin 6 of the comparator U7 and the pin 3 of the comparator U10, the pin 5 of the comparator U10 is connected to a chip U9 for outputting rising and falling edges, the chip U9 is connected to the FPGA unit 6 and the encoder U4, and the pin 1 of the comparator U10 is connected to a chip U5.

[0027] The TDC unit 7 cooperates with the CLK unit 5 and the FPGA unit 6 to realize the accurate calculation of the pulse arrival time. The circuit structure of the TDC unit 7 is provided below, so as to realize the data interaction among the three and the measurement of the pulse arrival time. Figure 8-Figure 10 As shown, the TDC unit 7 includes a TDC chip U14 connected to the FPGA unit 6, and resistors R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54 and R55 connected to corresponding ports are arranged between the TDC chip U14 and the FPGA unit 6. The FPGA unit 6 is also connected to the TDC chip U12, and pins 1 and 2 of the TDC chip U12 are connected to resistor R30, crystal oscillator Y2, resistor R29, capacitor C52, capacitor C53 and resistor R131, and pin 1 of the TDC chip U12 is connected to an atomic clock.

[0028] The clock circuit 3 needs to multiply the CLK signal of the atomic clock to make it suitable for this measurement system. The circuit structure of the clock circuit 3 is provided below. Fig.11 and Fig.12 As shown, the clock circuit 3 includes a clock buffer U15, a resistor R57 is connected between pins 3 and 4 of the clock buffer U15, a capacitor C67, a resistor R56 and a capacitor C68 are connected between pins 6 and 7 of the clock buffer U15 in sequence, a resistor R58 and a resistor R60 connected in parallel with the capacitor C67, the resistor R56 and the capacitor C68 are also connected in series between pins 6 and 7 of the clock buffer U15, the resistor R58 and the resistor R60 are connected in series to pin 8 of the clock buffer U15 and the capacitor C69, the FPGA unit 6 is also connected to a chip U16, and the chip U16 is connected to a resistor R61, a capacitor C72, a coil L3, a capacitor C78 and a capacitor C80.

[0029] In order to provide a modular I / O interface for the FPGA unit 6, simplify the design and improve the reuse rate, a circuit structure of an interface is also provided, such as Figure 13-Figure 15 As shown, the measurement system also includes an FMC circuit 8 connected to the FPGA unit 6. The FMC circuit 8 includes an interface JIA, an interface JIB and an interface JIC connected to the FPGA unit 6. The interface JIA, the interface JIB and the interface JIC are standardized interfaces. The FMC standard defines two connectors, LPC and HPC, supports high-speed signal transmission, and allows multiple functions to be implemented through different daughter boards. The Xilinx VC707 development board is an example of an FMC interface, which has two FMC interfaces and can be used to connect various FMC daughter boards.

[0030] In order to store the data obtained during the measurement process, a circuit structure for storing process data is also provided, such as Figure 16-18As shown, the measurement system also includes a storage circuit 9 connected to the FPGA unit 6, the storage circuit 9 includes a DDR chip U18 connected to the FPGA unit 6, the B2 pin of the DDR chip is sequentially connected with capacitors C90, C92, C94, C96, C97, C98, C99 and C100, the DDR chip U18 is connected with a control chip U19, and resistors R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86 and R87, capacitor C107, resistor R92 and resistor R91 are connected to pin 1 of the control chip U19, capacitor C105 and capacitor C108 are connected in parallel between pin 2 and pin 4 of the control chip U19, capacitor C102, capacitor C104, capacitor C106 and capacitor C113 are connected in parallel between pin 3 and pin 6 of the control chip U19, resistor R93 is connected between pin 9 and pin 10 of the control chip U19, and capacitor C115 is connected between pin 8 and pin 10 of the control chip U19.

[0031] In order to ensure that the voltage output by the power supply can be used by various chips, the output voltage of the power supply needs to be changed. The following is a structure of a voltage adjustment circuit. Figure 19-20 As shown, the measurement system also includes a power supply circuit 10 for changing the input voltage. The power supply circuit 10 includes a voltage adjustment chip U26. The model of the voltage adjustment chip U26 is YYT628IBV. The voltage adjustment chip U26 is connected to a voltage adjustment chip U23 and a voltage adjustment chip U24.

[0032] The present invention also provides a method for measuring pulse arrival time, such as Fig.21 As shown, the measurement method includes the following steps: S1, obtain the pulse signal and convert it into a digital signal, and copy the digital signal into 3 channels; S2. Input one of the digital signals into the DA unit, and determine the CLK time corresponding to the rising edge and falling edge of the digital signal according to the rising edge and falling edge determination rules of the FPGA unit 6; in order to improve the measurement accuracy, the detection of the CLK time is obtained by counting the atomic clock. The atomic clock is a kind of clock that uses the energy level difference of atoms as a reference signal. The core application of the atomic clock lies in its excellent time stability and high precision. When the orbit of the electron flying outside the nucleus changes, it will absorb or release electromagnetic waves of constant frequency, that is, the oscillation frequency. The focus of the atomic clock is to extract this oscillation frequency as a measure of time and convert it into a second signal. Therefore, the atomic clock is connected as the counting standard CLK at the same time to obtain the CLK time, that is, the CLK signal identifier in each circuit diagram; S3, inputting another digital signal into the FPGA unit 6, the FPGA unit 6 saves the corresponding first pulse arrival time when detecting the digital signal, and outputs a STOP signal of the first pulse time including the difference between the first pulse arrival time and the CLK time; S4, input the last digital signal to the TDC unit 7, the TDC unit 7 saves the corresponding second pulse arrival time when detecting the digital signal, and outputs a START signal of the second pulse time including the difference between the first pulse arrival time and the second pulse arrival time; S5. Calculate the pulse arrival time corresponding to the rising edge and the falling edge according to the CLK time, the first pulse time and the second pulse time and output them; the calculation formula of the pulse arrival time is: ; In the above formula, Indicates the pulse arrival time corresponding to the rising edge and falling edge, Indicates the CLK time corresponding to the rising edge and falling edge, and Represent the first pulse arrival time and the second pulse time respectively.

[0033] The above implementation methods have been described in detail. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A pulse arrival time measurement system, comprising an antenna (1) for receiving a radio frequency signal and converting it into an intermediate frequency signal, and a signal conversion unit (2) for detecting the intermediate frequency signal and converting it into a digital signal, and also comprising a clock circuit (3) for providing a clock signal, characterized in that: Also includes: A DA unit (4) for acquiring a digital signal and performing threshold determination on a rising edge and a falling edge of the digital signal; A CLK unit (5) for counting the time corresponding to the rising edge and the falling edge of the digital signal in the DA unit (4), and outputting the CLK time corresponding to the arrival of the rising edge and the falling edge; An FPGA unit (6) for acquiring a digital signal, and sending a STOP signal to a TDC unit (7) when receiving the digital signal, marking the sending time of the STOP signal as the first pulse arrival time, and calculating the arrival time of each rising edge and falling edge according to the second pulse time and the CLK time; A TDC unit (7) is used to acquire a digital signal, and when receiving the digital signal, sends a START signal to the FPGA unit (6), and calculates the time interval between the START signal and the STOP signal to obtain a second pulse time.

2. A pulse arrival time measurement system according to claim 1, characterized in that: The signal conversion unit (2) comprises a detector (21) for detecting an intermediate frequency signal to obtain a demodulated signal, and also comprises an A / D circuit (22) for converting the demodulated signal into a digital signal, wherein the A / D circuit (22) comprises an encoder U4, the encoder U4 is connected to a comparator U1 for signal input, the 8th and 1st pins of the comparator U1 are provided with a resistor R5, a capacitor C1, a resistor R1, a capacitor C2 and a resistor R6 for forming a loop, the demodulated signal is input from both ends of the resistor R1, a resistor R7 is connected between the 8th and 5th pins of the comparator U1, a resistor R8 is connected between the 1st and 4th pins of the comparator U1, a resistor R11 is connected between the 5th pin of the comparator U1 and the encoder U4, and a resistor R12 is further connected between the 4th pin of the comparator U1 and the encoder U4.

3. A pulse arrival time measurement system according to claim 2, characterized in that: The DA unit (4) includes a comparator U7, wherein the 2nd pin of the comparator U7 is connected to a resistor R20 and a capacitor C35 in sequence, the 3rd pin of the comparator U7 is connected to a resistor R19 and a capacitor C34 in sequence, the 2nd pin and the 6th pin of the comparator U7 are connected to a resistor R25, the 6th pin of the comparator U7 is connected to a comparator U10, a voltage-stabilizing diode D5 is connected between the 6th pin of the comparator U7 and the 3rd pin of the comparator U10, the 5th pin of the comparator U10 is connected to a chip U9 for outputting rising edges and falling edges, the chip U9 is connected to the FPGA unit (6) and the encoder U4, and the 1st pin of the comparator U10 is connected to a chip U5.

4. A pulse arrival time measurement system according to claim 1, characterized in that: The TDC unit (7) comprises a TDC chip U14 connected to the FPGA unit (6); resistors R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54 and R55 are arranged between the TDC chip U14 and the FPGA unit (6) and connected to corresponding ports; a TDC chip U12 is also connected to the FPGA unit (6); a resistor R30, a crystal oscillator Y2, a resistor R29, a capacitor C52, a capacitor C53 and a resistor R131 are connected to pins 1 and 2 of the TDC chip U12; and an atomic clock is connected to pin 1 of the TDC chip U12.

5. A pulse arrival time measurement system according to claim 1, characterized in that: The clock circuit (3) comprises a clock buffer U15, wherein a resistor R57 is connected between pins 3 and 4 of the clock buffer U15, and a capacitor C67, a resistor R56 and a capacitor C68 are connected in sequence between pins 6 and 7 of the clock buffer U15. A resistor R58 and a resistor R60 connected in parallel with the capacitor C67, the resistor R56 and the capacitor C68 are also connected in series between pins 6 and 7 of the clock buffer U15. The resistor R58 and the resistor R60 are connected in series to pin 8 of the clock buffer U15 and the capacitor C69. The FPGA unit (6) is also connected to a chip U16, and the chip U16 is connected to a resistor R61, a capacitor C72, a coil L3, a capacitor C78 and a capacitor C80.

6. A pulse arrival time measurement system according to claim 1, characterized in that: It also includes an FMC circuit (8) connected to the FPGA unit (6), and the FMC circuit (8) includes an interface JIA, an interface JIB and an interface JIC connected to the FPGA unit (6).

7. A pulse arrival time measurement system according to claim 1, characterized in that: The device also includes a storage circuit (9) connected to the FPGA unit (6), wherein the storage circuit (9) includes a DDR chip U18 connected to the FPGA unit (6), a capacitor C90, a capacitor C92, a capacitor C94, a capacitor C96, a capacitor C97, a capacitor C98, a capacitor C99 and a capacitor C100 are sequentially connected to the B2 pin of the DDR chip, a control chip U19 is connected to the DDR chip U18, and resistors R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75 and R76 are connected between the DDR chip U18 and the control chip U19. , R77, R78, R79, R80, R81, R82, R83, R84, R85, R86 and R87, capacitor C107, resistor R92 and resistor R91 are connected to pin 1 of the control chip U19, capacitor C105 and capacitor C108 are connected in parallel between pin 2 and pin 4 of the control chip U19, capacitor C102, capacitor C104, capacitor C106 and capacitor C113 are connected in parallel between pin 3 and pin 6 of the control chip U19, resistor R93 is connected between pin 9 and pin 10 of the control chip U19, and capacitor C115 is connected between pin 8 and pin 10 of the control chip U19.

8. A pulse arrival time measurement system according to claim 1, characterized in that: It also includes a power supply circuit (10) for changing the input voltage, wherein the power supply circuit (10) includes a voltage adjustment chip U26, and the voltage adjustment chip U23 and the voltage adjustment chip U24 are connected to the voltage adjustment chip U26.

9. A method for measuring pulse arrival time, based on the measurement system according to any one of claims 1 to 8, characterized in that: The measurement method comprises the following steps: S1, obtain the pulse signal and convert it into a digital signal, and copy the digital signal into 3 channels; S2, input one of the digital signals into the DA unit, and determine the CLK time corresponding to the rising edge and falling edge of the digital signal according to the rising edge and falling edge determination rules of the FPGA unit; S3, inputting another digital signal into the FPGA unit, the FPGA unit saves the corresponding first pulse arrival time when detecting the digital signal, and outputs a STOP signal of the first pulse time including the difference between the first pulse arrival time and the CLK time; S4, input the last digital signal to the TDC unit, the TDC unit saves the corresponding second pulse arrival time when detecting the digital signal, and outputs a START signal of the second pulse time including the difference between the first pulse arrival time and the second pulse arrival time; S5. Calculate the pulse arrival time corresponding to the rising edge and the falling edge according to the CLK time, the first pulse time and the second pulse time and output them; the calculation formula of the pulse arrival time is: ； In the above formula, Indicates the pulse arrival time corresponding to the rising edge and falling edge, Indicates the CLK time corresponding to the rising edge and falling edge, and Represent the first pulse arrival time and the second pulse time respectively.

10. The measuring method according to claim 9, characterized in that: The CLK time is detected by counting an atomic clock.

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