Memory access system, method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a memory access system, method and device, electronic equipment and a readable storage medium, and relates to the technical field of computers. When the memory is accessed, each row of data in the buffer memory can be quickly transferred to each row of the register (conversely in the same way), element data does not need to be transferred one by one, so that the register can quickly receive and release the data, the occupied time of the register is effectively shortened, and the memory access efficiency is improved. And the utilization efficiency of storage resources in the register is improved. Furthermore, when the control unit needs to process a plurality of instructions, the register can quickly receive and release the data, so that the subsequent instructions can be executed in time, and the data processing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory access system, method, device, electronic device and readable storage medium. Background Art

[0002] When the electronic device processes data, the processor may read the data in the internal memory into the register through an access instruction, or the processor may write the data in the register into the internal memory through a storage instruction.

[0003] In this process, due to the limited storage resources in the register, if the processing time of a single instruction is too long, the register will be occupied for a long time and the subsequent instructions cannot be executed in time, which will lead to low data processing efficiency. Therefore, how to efficiently use the storage resources in the register is an urgent problem to be solved. Summary of the invention

[0004] In view of this, embodiments of the present application provide a memory access system, method, device, electronic device, and readable storage medium to improve the utilization efficiency of storage resources in registers.

[0005] In a first aspect, a memory access system is provided, the system comprising at least a control unit, an internal memory, a buffer memory and a register.

[0006] The buffer memory and the register have the same length, the control unit is configured to control the internal memory, the buffer memory and the register, the register is configured to be controlled to access the internal memory through the buffer memory, the buffer memory and the register read and write data in a row-by-row manner, and the buffer memory and the internal memory read and write data in an addressing manner.

[0007] In some embodiments, the control unit is configured to perform the following steps:

[0008] In response to a memory read access instruction, first target data stored in the internal memory is buffered in the buffer memory according to an addressing mode corresponding to the memory read access instruction.

[0009] The first target data in the buffer memory is written into the register in a row-by-row reading and writing manner.

[0010] The first target data in the register is read to perform data processing.

[0011] In some embodiments, the control unit is further configured to perform:

[0012] In response to a memory storage access instruction, the second target data in the register is buffered into the buffer memory in a row-by-row reading and writing manner.

[0013] The second target data in the buffer memory is written into the internal memory according to the addressing mode corresponding to the memory storage access instruction.

[0014] In some embodiments, the register is a vector register, the memory read access instruction and the memory storage access instruction are vector extension instructions in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: a fixed interval memory access mode and an indexed memory access mode.

[0015] In a second aspect, a memory access method is provided, the method comprising:

[0016] In response to the memory read access instruction, first target data stored in the internal memory is buffered in the buffer memory according to an addressing mode corresponding to the memory read access instruction.

[0017] The first target data in the buffer memory is written into the register in a row-by-row reading and writing manner.

[0018] The first target data in the register is read to perform data processing.

[0019] In some embodiments, the register is a vector register, the memory read access instruction is a vector extension instruction in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: a fixed interval memory access mode and an indexed memory access mode.

[0020] In a third aspect, a memory access method is provided, the method comprising:

[0021] In response to the memory storage access instruction, the second target data in the register is buffered into the buffer memory in a row-by-row reading and writing manner.

[0022] The second target data in the buffer memory is written into the internal memory according to the addressing mode corresponding to the memory storage access instruction.

[0023] In some embodiments, the register is a vector register, the memory storage access instruction is a vector extension instruction in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: a fixed interval memory access mode and an indexed memory access mode.

[0024] In a fourth aspect, a memory access device is provided, the device comprising:

[0025] The first buffer module is configured to execute in response to a memory read access instruction and buffer the first target data stored in the internal memory into the buffer memory according to an addressing mode corresponding to the memory read access instruction.

[0026] The first storage module is configured to write the first target data in the buffer memory into the register in a row-by-row reading and writing manner.

[0027] The data processing module is configured to read the first target data in the register to perform data processing.

[0028] In some embodiments, the register is a vector register, the memory read access instruction is a vector extension instruction in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: a fixed interval memory access mode and an indexed memory access mode.

[0029] In a fifth aspect, a memory access device is provided, the device comprising:

[0030] The second buffer module is configured to execute in response to the memory storage access instruction and buffer the second target data in the register into the buffer memory in a row-by-row reading and writing manner.

[0031] The second storage module is configured to execute an addressing mode corresponding to the memory storage access instruction to write the second target data in the buffer memory into the internal memory.

[0032] In some embodiments, the register is a vector register, the memory storage access instruction is a vector extension instruction in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: a fixed interval memory access mode and an indexed memory access mode.

[0033] In the sixth aspect, an embodiment of the present application provides an electronic device, comprising an instruction memory and a memory access system as described in the first aspect, wherein the instruction memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by a control unit in the memory access system to implement the memory access method as described in the second aspect or the third aspect.

[0034] In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the memory access method as described in the second aspect or the third aspect is implemented.

[0035] In the embodiment of the present application, since the buffer memory and the internal memory do not require the participation of registers during data exchange, the length of the buffer memory and the register are the same, and the data is read and written between the buffer memory and the register in a row-by-row manner, therefore, when accessing the internal memory, the embodiment of the present application can quickly transfer each row of data in the buffer memory to each row in the register (and vice versa), without the need to transfer element data one by one, so that the register can quickly receive and release data, effectively reducing the length of time the register is occupied and improving the utilization efficiency of the storage resources in the register. Furthermore, when the control unit needs to process multiple instructions, since the register can quickly receive and release data, subsequent instructions can be executed in a timely manner, improving the efficiency of data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other purposes, features and advantages of the embodiments of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0037] Figure 1 A schematic diagram of the addressing process in the continuous memory access mode of the related technology;

[0038] Figure 2 A schematic diagram of the addressing process in a fixed interval memory access mode of the related technology;

[0039] Figure 3 A schematic diagram of the addressing process in the index memory access mode of the related technology;

[0040] Figure 4 A schematic diagram of a memory access system according to an embodiment of the present application;

[0041] Figure 5 A flowchart of a memory access method according to an embodiment of the present application;

[0042] Figure 6 A schematic diagram of a flow chart of performing read access in a fixed interval memory access mode according to an embodiment of the present application;

[0043] Figure 7 A schematic diagram of a flow chart of performing read access in an index memory access mode according to an embodiment of the present application;

[0044] Figure 8 A flowchart of another memory access method according to an embodiment of the present application;

[0045] Fig. 9 A schematic diagram of a flow chart of performing storage access in a fixed interval memory access mode according to an embodiment of the present application;

[0046] Fig.10 A schematic diagram of a process of performing storage access in an index memory access mode according to an embodiment of the present application;

[0047] Fig.11 A schematic diagram of the structure of a memory access device according to an embodiment of the present application;

[0048] Fig.12 A schematic diagram of the structure of another memory access device according to an embodiment of the present application;

[0049] Fig.13 A schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0050] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0051] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0052] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0053] Unless the context clearly requires otherwise, the words "include", "comprising" and the like throughout this application should be interpreted as including rather than exclusive or exhaustive; that is, as meaning "including but not limited to".

[0054] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0055] When an electronic device processes data, a processor may read data in a memory (ie, an internal memory) into a register through an access instruction, or the processor may write data in a register into the memory through a storage instruction.

[0056] The addressing modes of the above memory access instructions (i.e., access instructions and storage instructions) may include a continuous memory access mode (unit-stride), a fixed interval memory access mode (strided), and an indexed memory access mode (indexed). The continuous memory access mode can continuously access multiple element data in the memory without occupying the register for a long time.

[0057] However, for the fixed-interval memory access mode and the index memory access mode, since the fixed-interval memory access mode is a mode of accessing each element data from the memory at a fixed interval, and the index memory access mode is a mode of accessing each element data from the memory according to the data index, therefore, in the fixed-interval memory access mode and the index memory access mode, the register can only access one element data in the memory at a time, which causes the register to be occupied for a long time.

[0058] Taking the data processing of vector data by related technology as an example, if the length of the vector register in the electronic device is VLEN bit, the number of register groups allowed to operate simultaneously is LMUL, and the bit width of an element data is sew bit, then the maximum number of element data that can be processed by a vector instruction is LMUL_MAX*(VLEN / SEW), and the number of element data included in a vector register is N=VLEN / SEW, where LMUL_MAX is used to represent the maximum value of LMUL.

[0059] like Figure 1 , Figure 2 and Figure 3 As shown, the memory includes 6 element data 11 to be accessed, among which, Figure 1 Each square in the represents an element data, and the element data 11 filled in the memory is used to represent the element data to be accessed this time. Figure 1 , Figure 2 and Figure 3 The padding in is only used to identify the element data 11 to be accessed, and does not limit the specific content of the element data. That is, the element data 11 with the same padding can be data with the same content or data with different contents.

[0060] Figure 1 This is a schematic diagram of the addressing process of the related technology in the continuous memory access mode, such as Figure 1 As shown, the continuous memory access mode can continuously access each element data 11 in the memory, and store the element data 11 in the register at one time to access the data in the memory. In this process, since the continuous memory access mode can continuously access multiple element data 11 in the memory, the continuous memory access mode does not occupy the register for a long time.

[0061] Figure 2It is a schematic diagram of the addressing process of the related technology in the fixed interval memory access mode, such as Figure 2 As shown, the fixed interval memory access mode can be performed at a fixed interval ( Figure 2 Taking the interval of 1 element data as an example, each element data 11 is accessed from the memory, and each element data 11 is stored in the register one by one to access the data in the memory. In this process, since the fixed interval memory access mode is a mode of accessing each element data from the memory at a fixed interval, the fixed interval memory access mode can only access and obtain one element data 11 at a time, that is, it takes 6 accesses to obtain Figure 2 All element data 11 in the memory, which makes the related technology take a long time to execute fixed interval memory access mode instructions, resulting in problems such as registers being occupied for a long time and subsequent instructions cannot be executed in time.

[0062] Figure 3 This is a schematic diagram of the addressing process of the related technology in the index memory access mode, such as Figure 3 As shown, the index memory access mode can access each element data 11 from the memory according to the data index. That is, the order of accessing the memory in the index memory access mode is not fixed. Therefore, the index memory access mode can only access to obtain one element data 11 at a time, that is, it takes 6 accesses to obtain Figure 3 All element data 11 in the index memory access mode, which makes the related technology take a long time to execute the index memory access mode instruction, which in turn causes problems such as registers being occupied for a long time and subsequent instructions cannot be executed in time.

[0063] Combination Figure 2 and Figure 3 From the perspective of the related art, since the storage resources in the registers are limited, if the processing time of a single instruction is too long, the registers will be occupied for a long time and the subsequent instructions cannot be executed in time, which will lead to low data processing efficiency. For example, in an out-of-order multi-issue central processing unit (CPU), since the execution of instructions is out of order, it is often necessary to rename the architecture registers during the execution of instructions. Correspondingly, in the physical registers corresponding to the architecture registers, if the processing time of a single instruction is too long, the corresponding physical registers will not be released for a long time, which will cause the subsequent renaming operations of the same type of instructions, resulting in the CPU processing instruction pipeline being blocked, and the CPU processing instruction efficiency is low. Therefore, how to efficiently utilize the storage resources in the registers is a problem that needs to be solved urgently.

[0064] In order to solve the above problems, the embodiments of the present application provide a memory access system and a memory access method that can be applied to the memory access system. The memory access system of the embodiments of the present application can be applied to an electronic device, the electronic device can be a terminal or a server, the terminal can be a smart phone, a tablet computer, a vehicle control terminal or a personal computer (PC), etc., the server can be a single server, a server cluster configured in a distributed manner, or a cloud server.

[0065] Specifically, the memory access system of the embodiment of the present application includes at least a control unit, an internal memory, a buffer memory and a register. The register and the control unit may be components integrated in the processor of the electronic device, and the buffer memory may be a component integrated in the processor or a component separately provided in the electronic device.

[0066] In an embodiment of the present application, the length of the buffer memory and the register is the same, the control unit is configured to control the internal memory, the buffer memory and the register, the register is configured to be controlled to access the internal memory through the buffer memory, the buffer memory and the register read and write data in a row-by-row manner, and the buffer memory and the internal memory read and write data in an addressing manner. In other words, the buffer memory can be configured to be controlled to receive and buffer the data stored in the register or the internal memory, and the internal memory and the register can be configured to be controlled to receive and store the buffered data in the buffer memory. In addition, the length of the buffer memory and the register is the same, which allows the data of one register to be transmitted at a time, that is, the data in the register is read into the corresponding buffer memory at a time, thereby improving the data transmission efficiency.

[0067] The buffer memory of the embodiment of the present application can be used as an intermediate component between the register and the internal memory. On the one hand, it can interact with the internal memory in an addressing manner, and this process does not require the participation of the register. On the other hand, the buffer memory of the embodiment of the present application can interact with the register in a line-by-line reading and writing manner to quickly avoid the register being occupied for a long time and improve the utilization efficiency of the storage resources in the register.

[0068] For example, Figure 4As shown, the control unit 44 can be connected to the internal memory 41, the buffer memory 42 and the register 43 respectively to control each memory. Among them, the register 43 is a high-speed storage component with limited storage capacity, which can quickly provide data to the control unit 44. However, due to the small capacity of the register 43, a large amount of data cannot be stored in the register 43. That is to say, when the control unit 44 needs to process data, on the one hand, the control unit 44 can first transfer the data to be processed from the internal memory 41 to the register 43, and then obtain the data through data interaction with the register 43 to read the data in the internal memory 41 (i.e., the memory load process). On the other hand, the control unit 44 can also first store the processed data in the register 43 through data interaction with the register 43, and then transfer the data to the internal memory 41 (i.e., the memory store process).

[0069] Specifically, in the process of the control unit 44 reading and accessing (loading) the internal memory 41, the control unit 44 can first write the data stored in the internal memory 41 into the buffer memory 42 in an addressing manner, and this process does not require the participation of the register 43, that is, at this time, there is no need to occupy the storage resources of the register 43. Further, the control unit 44 can quickly write the data in the buffer memory 42 into the register 43 in a row-by-row reading and writing manner, so that the control unit 44 can read the data.

[0070] Accordingly, in the process of the control unit 44 accessing (storing) the internal memory 41, the control unit 44 may first write the processed data stored in the register 43 into the buffer memory 42 in a row-by-row read and write manner. Furthermore, the control unit 44 may write the data stored in the buffer memory 42 into the internal memory 41 in an addressing manner, so that the internal memory 41 stores the data. This process does not require the participation of the register 43, that is, the storage resources of the register 43 do not need to be occupied at this time.

[0071] In the above process, since the buffer memory 42 and the internal memory 41 do not need the participation of the register 43 during data exchange, the lengths of the buffer memory 42 and the register 43 are the same, and the data is read and written between the buffer memory 42 and the register 43 in a row-by-row manner, therefore, when accessing the memory, the embodiment of the present application can quickly transfer each row of data in the buffer memory 42 to each row in the register 43 (and vice versa), without the need to transfer element data one by one, so that the register 43 can quickly receive and release data, effectively reducing the length of time the register 43 is occupied and improving the utilization efficiency of the storage resources in the register 43. Furthermore, when the control unit 44 needs to process multiple instructions, since the register 43 can quickly receive and release data, subsequent instructions can be executed in a timely manner, improving the efficiency of data processing.

[0072] In an optional embodiment, the register of the embodiment of the present application is a vector register, the memory read access instruction and the memory storage access instruction are vector extension instructions in the RISC-V instruction set (i.e., RISC V-V memory access instructions), and the addressing mode includes at least one or more of the following modes: fixed interval memory access mode and index memory access mode.

[0073] Among them, RISC-V is an open source instruction set architecture based on the principle of reduced instruction set computing (RISC), which is small, fast and low power. The fixed interval memory access mode is a mode of accessing each element data from the memory at a fixed interval, and the index memory access mode is a mode of accessing each element data from the memory according to the data index.

[0074] That is to say, the memory access system and memory access method of the embodiments of the present application can be applied to vector data reading and storage in a fixed interval memory access mode or an indexed memory access mode. In this process, since data is read and written line by line between the buffer memory and the register, the register can quickly receive and release data, effectively reducing the length of time the register is occupied and improving the utilization efficiency of the storage resources in the register.

[0075] For the above read access process, such as Figure 5 As shown, the control unit of the embodiment of the present application can be configured to perform the following steps:

[0076] In step S110 , in response to the memory read access instruction, the first target data stored in the internal memory is buffered into the buffer memory according to the addressing mode corresponding to the memory read access instruction.

[0077] Among them, the memory read access instruction is used to access the memory and read the data therein. After receiving and parsing the memory read access instruction, the control unit can determine the addressing mode corresponding to the memory read access instruction. In addition, the first target data is used to characterize the data accessed and read in the internal memory. In an optional embodiment, the memory read access instruction of the embodiment of the present application can be a vector extension instruction in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: fixed interval memory access mode and index memory access mode.

[0078] In step S120, the first target data in the buffer memory is written into the register in a row-by-row reading and writing manner.

[0079] In step S130 , the first target data in the register is read for data processing.

[0080] Take the read access of fixed interval memory access mode as an example, Figure 6As shown, when the control unit reads and accesses each first target data 61 in the internal memory (i.e., the memory), the control unit can first write the first target data 61 stored in the internal memory into the buffer memory one by one in a fixed interval memory access mode. This process does not require the participation of the register, that is, the storage resources of the register do not need to be occupied at this time. Further, the control unit can quickly write the first target data 61 in the buffer memory into the register in a row-by-row read and write manner, so that the control unit reads the first target data 61 in the register for data processing.

[0081] Take the read access of index access mode as an example, Figure 7 As shown, when the control unit reads and accesses each first target data 71 in the internal memory (i.e., the memory), the control unit can first write the first target data 71 stored in the internal memory into the buffer memory one by one in the index access mode. This process does not require the participation of the register, that is, the storage resources of the register do not need to be occupied at this time. Further, the control unit can quickly write the first target data 71 in the buffer memory into the register in a row-by-row read and write manner, so that the control unit reads the first target data 71 in the register for data processing.

[0082] exist Figure 6 and Figure 7 In the process shown, since the buffer memory and the internal memory do not require the participation of registers when data is exchanged, the lengths of the buffer memory and the register are the same, and the first target data is transferred between the buffer memory and the register in a row-by-row reading and writing manner. Therefore, when reading and accessing the memory, the embodiment of the present application can quickly transfer each row of data in the buffer memory to each row in the register without transferring the first target data one by one, so that the register can quickly receive and release data, effectively reducing the length of time the register is occupied and improving the utilization efficiency of the storage resources in the register.

[0083] For the above storage access process, such as Figure 8 As shown, the control unit of the embodiment of the present application can be configured to perform the following steps:

[0084] In step S210 , in response to the memory storage access instruction, the second target data in the register is buffered into the buffer memory in a row-by-row reading and writing manner.

[0085] Among them, the memory storage access instruction is used to access the memory and store data in the memory. After receiving and parsing the memory storage access instruction, the control unit can determine the addressing mode corresponding to the memory storage access instruction. In addition, the second target data is used to characterize the data that needs to be stored in the internal memory. In an optional embodiment, the memory storage access instruction of the embodiment of the present application can be a vector extension instruction in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: fixed interval memory access mode and index memory access mode.

[0086] In step S220, the second target data in the buffer memory is written into the internal memory according to the addressing mode corresponding to the memory storage access instruction.

[0087] Take the storage access of fixed interval memory access mode as an example, Fig. 9 As shown, when the control unit accesses the internal memory (i.e., the memory) and stores each second target data 91, the control unit can first quickly write the second target data 91 stored in the register into the buffer memory in a row-by-row reading and writing manner. Further, the control unit can write each second target data 91 stored in the buffer memory into the internal memory in a fixed interval memory access mode, so that the internal memory stores each second target data 91. This process does not require the participation of the register, that is, at this time, the storage resources of the register do not need to be occupied.

[0088] Take the storage access of index access mode as an example, Fig.10 As shown, when the control unit accesses the internal memory (i.e., the memory) and stores each second target data 1001, the control unit can first quickly write the second target data 1001 stored in the register into the buffer memory in a row-by-row reading and writing manner. Further, the control unit can write each second target data 1001 stored in the buffer memory into the internal memory in an index access mode, so that the internal memory stores each second target data 1001. This process does not require the participation of registers, that is, at this time, the storage resources of the registers do not need to be occupied.

[0089] exist Fig. 9 and Fig.10 In the process shown, since the buffer memory and the internal memory do not require the participation of registers when data is exchanged, the lengths of the buffer memory and the register are the same, and the second target data is transferred between the buffer memory and the register in a row-by-row read and write manner. Therefore, when storing and accessing the memory, the embodiment of the present application can quickly transfer each row of data in the register to each row in the buffer memory without transferring the second target data one by one, so that the register can quickly receive and release data, effectively reducing the length of time the register is occupied and improving the utilization efficiency of the storage resources in the register.

[0090] Based on the same technical concept, the embodiment of the present application also provides a memory access device, such as Fig.11 As shown, the device includes: a first buffer module 1101 , a first storage module 1102 and a data processing module 1103 .

[0091] The first buffer module 1101 is configured to execute, in response to a memory read access instruction, buffer the first target data stored in the internal memory into the buffer memory according to an addressing mode corresponding to the memory read access instruction.

[0092] The first storage module 1102 is configured to write the first target data in the buffer memory into the register in a row-by-row reading and writing manner.

[0093] The data processing module 1103 is configured to read the first target data in the register to perform data processing.

[0094] In some embodiments, the register is a vector register, the memory read access instruction is a vector extension instruction in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: a fixed interval memory access mode and an indexed memory access mode.

[0095] In the embodiment of the present application, since the buffer memory and the internal memory do not require the participation of registers during data exchange, the length of the buffer memory and the register are the same, and the data is read and written between the buffer memory and the register in a row-by-row manner, therefore, when accessing the internal memory, the embodiment of the present application can quickly transfer each row of data in the buffer memory to each row in the register (and vice versa), without the need to transfer element data one by one, so that the register can quickly receive and release data, effectively reducing the length of time the register is occupied and improving the utilization efficiency of the storage resources in the register. Furthermore, when the control unit needs to process multiple instructions, since the register can quickly receive and release data, subsequent instructions can be executed in a timely manner, improving the efficiency of data processing.

[0096] The present application also provides a memory access device, such as Fig.12 As shown, the device includes: a second buffer module 1201 and a second storage module 1202 .

[0097] The second buffer module 1201 is configured to execute in response to the memory storage access instruction and buffer the second target data in the register into the buffer memory in a row-by-row reading and writing manner.

[0098] The second storage module 1202 is configured to execute an addressing mode corresponding to the memory storage access instruction to write the second target data in the buffer memory into the internal memory.

[0099] In some embodiments, the register is a vector register, the memory storage access instruction is a vector extension instruction in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: a fixed interval memory access mode and an indexed memory access mode.

[0100] In the embodiment of the present application, since the buffer memory and the internal memory do not require the participation of registers during data exchange, the length of the buffer memory and the register are the same, and the data is read and written between the buffer memory and the register in a row-by-row manner, therefore, when accessing the internal memory, the embodiment of the present application can quickly transfer each row of data in the buffer memory to each row in the register (and vice versa), without the need to transfer element data one by one, so that the register can quickly receive and release data, effectively reducing the length of time the register is occupied and improving the utilization efficiency of the storage resources in the register. Furthermore, when the control unit needs to process multiple instructions, since the register can quickly receive and release data, subsequent instructions can be executed in a timely manner, improving the efficiency of data processing.

[0101] Fig.13 Schematic diagram of an electronic device according to an embodiment of the present application. Fig.13 As shown, Fig.13 The electronic device shown is a general address query device, which includes a general computer hardware structure, which at least includes a processor 1301, an instruction memory 1302 and an internal memory 1307. The processor 1301 includes a buffer memory, a register and a control unit (the buffer memory, the register and the control unit are not shown in the figure), and the processor 1301, the instruction memory 1302 and the internal memory 1307 are connected via a bus 1303. The instruction memory 1302 is suitable for storing instructions or programs executable by the processor 1301. The processor 1301 can be an independent microprocessor or a collection of one or more microprocessors. Thus, the processor 1301 executes the instructions stored in the instruction memory 1302, thereby executing the method flow of the embodiment of the present application as described above to realize the processing of data and the control of other devices. The bus 1303 connects the above-mentioned multiple components together, and at the same time connects the above-mentioned components to the display controller 1304 and the display device and the input / output (I / O) device 1305. The input / output (I / O) device 1305 may be a mouse, keyboard, modem, network interface, touch input device, somatosensory input device, printer, and other devices known in the art. Typically, the input / output device 1305 is connected to the system via an input / output (I / O) controller 1306.

[0102] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices (equipment) or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present application may adopt a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0103] The present application is described with reference to flowcharts of methods, apparatuses (devices) and computer program products according to embodiments of the present application. It should be understood that each process in the flowchart can be implemented by computer program instructions.

[0104] These computer program instructions may be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device that implements the process Figure 1 A function specified in a process or multiple processes.

[0105] These computer program instructions may also be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce the instructions for implementing the process Figure 1 A device that specifies functions in a process or multiple processes.

[0106] Another embodiment of the present application relates to a non-volatile storage medium for storing a computer-readable program, wherein the computer-readable program is used for a computer to execute part or all of the above method embodiments.

[0107] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by specifying relevant hardware through a program, and the program is stored in a storage medium, including several instructions for a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0108] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory access system, characterized in that: The system at least comprises a control unit, an internal memory, a buffer memory and a register; The buffer memory and the register have the same length, the control unit is configured to control the internal memory, the buffer memory and the register, the register is configured to be controlled to access the internal memory through the buffer memory, the buffer memory and the register read and write data in a row-by-row manner, and the buffer memory and the internal memory read and write data in an addressing manner.

2. The system according to claim 1, characterized in that The control unit is configured to perform the following steps: In response to a memory read access instruction, buffering first target data stored in the internal memory into the buffer memory according to an addressing mode corresponding to the memory read access instruction; Writing the first target data in the buffer memory into the register in a row-by-row reading and writing manner; as well as The first target data in the register is read to perform data processing.

3. The system according to claim 1 or 2, characterized in that: The control unit is further configured to perform: In response to a memory storage access instruction, buffering the second target data in the register into the buffer memory in a row-by-row reading and writing manner; as well as The second target data in the buffer memory is written into the internal memory according to the addressing mode corresponding to the memory storage access instruction.

4. The system according to claim 3, characterized in that The register is a vector register, the memory read access instruction and the memory storage access instruction are vector extension instructions in the RISC-V instruction set, and the addressing mode includes at least one or more of the following modes: a fixed interval memory access mode and an index memory access mode.

5. A memory access method, characterized in that: The method comprises: In response to a memory read access instruction, buffering first target data stored in the internal memory into a buffer memory according to an addressing mode corresponding to the memory read access instruction; Writing the first target data in the buffer memory into the register in a row-by-row reading and writing manner; and The first target data in the register is read to perform data processing.

6. A memory access method, characterized in that: The method comprises: In response to the memory storage access instruction, buffering the second target data in the register into the buffer memory in a row-by-row reading and writing manner; and The second target data in the buffer memory is written into the internal memory according to the addressing mode corresponding to the memory storage access instruction.

7. A memory access device, characterized in that: The device comprises: A first buffer module is configured to execute, in response to a memory read access instruction, buffering first target data stored in the internal memory into a buffer memory according to an addressing mode corresponding to the memory read access instruction; A first storage module is configured to write the first target data in the buffer memory into the register in a row-by-row reading and writing manner; and The data processing module is configured to read the first target data in the register to perform data processing.

8. A memory access device, characterized in that: The device comprises: A second buffer module is configured to execute in response to the memory storage access instruction, buffering the second target data in the register into the buffer memory in a row-by-row reading and writing manner; and The second storage module is configured to execute an addressing mode corresponding to the memory storage access instruction to write the second target data in the buffer memory into the internal memory.

9. An electronic device, characterized in that: It comprises an instruction memory and a memory access system as described in any one of claims 1-4, wherein the instruction memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by a control unit in the memory access system to implement the memory access method as described in claim 5 or 6.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the memory access method according to claim 5 or 6 is implemented.

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