Fault information storage method, power management integrated circuit and basic input and output system

Abstract

The embodiment of the invention provides a fault information storage method, a power management integrated circuit and a basic input / output system, and relates to the technical field of computers, the method comprises the following steps: receiving first fault information sent by the basic input / output system; wherein the first fault information is generated when the basic input and output system detects a memory fault, and is used for describing the detected memory fault; and storing the first fault information under the condition that the quantity of the fault information stored in the power management integrated circuit does not exceed a preset quantity. By applying the scheme provided by the embodiment of the invention, the memory fault positioning efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a fault information storage method, a power management integrated circuit, and a basic input and output system. Background Art

[0002] SEL (System Event Log) is a log file used to store various errors, warnings, and important events that occur during the operation of a computer system. When a memory failure occurs, the BIOS (Basic InputOutput System) packages the relevant information, such as the fault address and error type, into an event entry and writes it to the SEL log.

[0003] However, a memory failure may report multiple errors, and the SEL log will record a large amount of fault information. When locating a memory failure, the staff needs to manually retrieve the core fault information that causes the memory operation error from the large amount of fault information in the SEL log, which takes a long time and results in low efficiency in locating the memory failure. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a fault information storage method, a power management integrated circuit, and a basic input and output system to improve the efficiency of memory fault location. The specific technical solution is as follows:

[0005] In a first aspect of an embodiment of the present application, a fault information storage method is first provided, which is applied to a power management integrated circuit. The method includes:

[0006] receiving first fault information sent by a basic input / output system; wherein the first fault information is generated by the basic input / output system when a memory fault is detected, and is used to describe the detected memory fault;

[0007] When the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the first fault information is stored.

[0008] In a possible embodiment, the method further includes:

[0009] If the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, the fault count of the second fault information is increased by one; wherein the first target identifier and the second target identifier are identifiers of the same type.

[0010] In a possible embodiment, the fault information generated by the basic input and output system includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier; wherein the first identifier indicates the fault type, the second identifier indicates the fault number, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error;

[0011] and / or

[0012] The fault type includes at least one of the following types: unknown memory error, no memory error, single-bit parity error, multi-bit parity error, single chip failure, multiple chip failures, hardware failure, and forced access interruption;

[0013] and / or

[0014] The fault location indicates a memory bar where a memory fault occurs, or a memory unit where a memory fault occurs, or a row address where a memory fault occurs, or a column address where a memory fault occurs.

[0015] In a second aspect of an embodiment of the present application, a fault information storage method is provided, which is applied to a basic input and output system, and the method includes:

[0016] Detect whether a memory failure occurs;

[0017] In the event of a memory failure, fault information describing the memory failure is generated and sent to a power management integrated circuit, so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

[0018] In a possible embodiment, when a memory failure occurs, generating fault information describing the memory failure, and sending the fault information to a power management integrated circuit, includes:

[0019] When a memory fault occurs and the memory fault is an uncorrectable error, generating third fault information describing the memory fault, and sending the third fault information to the power management integrated circuit;

[0020] or,

[0021] When a memory fault occurs, and the memory fault is a correctable error, and the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated and sent to the power management integrated circuit.

[0022] In a third aspect of an embodiment of the present application, a power management integrated circuit is provided, wherein the power management integrated circuit is configured to perform the following operations:

[0023] receiving first fault information sent by a basic input / output system; wherein the first fault information is generated by the basic input / output system when a memory fault is detected, and is used to describe the detected memory fault;

[0024] When the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the first fault information is stored.

[0025] In a possible embodiment, the power management integrated circuit is further configured to perform the following operations:

[0026] If the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, the fault count of the second fault information is increased by one; wherein the first target identifier and the second target identifier are identifiers of the same type.

[0027] In a possible embodiment, the fault information generated by the basic input and output system includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier; wherein the first identifier indicates the fault type, the second identifier indicates the fault number, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error;

[0028] and / or

[0029] The fault type includes at least one of the following types: unknown memory error, no memory error, single-bit parity error, multi-bit parity error, single chip failure, multiple chip failures, hardware failure, and forced access interruption;

[0030] and / or

[0031] The fault location indicates a memory bar where a memory fault occurs, or a memory unit where a memory fault occurs, or a row address where a memory fault occurs, or a column address where a memory fault occurs.

[0032] In a fourth aspect of the embodiments of the present application, a basic input / output system is provided, wherein the basic input / output system is configured to perform the following operations:

[0033] Detect whether a memory failure occurs;

[0034] In the event of a memory failure, fault information describing the memory failure is generated and sent to a power management integrated circuit, so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

[0035] In a possible embodiment, the basic input and output system is used to perform the following operations:

[0036] When a memory fault occurs and the memory fault is an uncorrectable error, generating third fault information describing the memory fault, and sending the third fault information to the power management integrated circuit;

[0037] or,

[0038] When a memory fault occurs, and the memory fault is a correctable error, and the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated and sent to the power management integrated circuit.

[0039] In a fifth aspect of an embodiment of the present application, an electronic device is provided, comprising a power management integrated circuit and a basic input-output system, wherein the power management integrated circuit is the power management integrated circuit described in any one of the third aspects above, and the basic input-output system is the basic input-output system described in any one of the fourth aspects above.

[0040] In a sixth aspect of an embodiment of the present application, a fault information storage device is provided, which is applied to a power management integrated circuit, and the device includes:

[0041] An information receiving module, used for receiving first fault information sent by a basic input and output system; wherein the first fault information is generated by the basic input and output system when a memory fault is detected, and is used for describing the detected memory fault;

[0042] The information storage module is used to store the first fault information when the amount of fault information stored in the power management integrated circuit does not exceed a preset amount.

[0043] In a possible embodiment, the device further includes:

[0044] An information updating module is used to increase the number of faults of the second fault information by one if the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information; wherein the first target identifier and the second target identifier are identifiers of the same type.

[0045] In a possible embodiment, the fault information generated by the basic input and output system includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier; wherein the first identifier indicates the fault type, the second identifier indicates the fault number, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error;

[0046] and / or

[0047] The fault type includes at least one of the following types: unknown memory error, no memory error, single-bit parity error, multi-bit parity error, single chip failure, multiple chip failures, hardware failure, and forced access interruption;

[0048] and / or

[0049] The fault location indicates a memory bar where a memory fault occurs, or a memory unit where a memory fault occurs, or a row address where a memory fault occurs, or a column address where a memory fault occurs.

[0050] In a seventh aspect of an embodiment of the present application, a fault information storage device is provided, which is applied to a basic input and output system, and the device includes:

[0051] A fault detection module, used to detect whether a memory fault occurs;

[0052] An information generation module is used to generate fault information describing the memory fault when a memory fault occurs, and send the fault information to a power management integrated circuit so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

[0053] In a possible embodiment, the information generating module is specifically used to:

[0054] When a memory fault occurs and the memory fault is an uncorrectable error, generating third fault information describing the memory fault, and sending the third fault information to the power management integrated circuit;

[0055] or,

[0056] When a memory fault occurs, and the memory fault is a correctable error, and the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated and sent to the power management integrated circuit.

[0057] In another aspect of the implementation of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the method steps described in any one of the first aspect or the second aspect are implemented.

[0058] Beneficial effects of the embodiments of the present application:

[0059] The fault information storage method provided in the embodiment of the present application is that the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0060] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0061] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0063] Figure 1 A schematic diagram of a flow chart of a first fault information storage method provided in an embodiment of the present application;

[0064] Figure 2 A schematic diagram of a flow chart of a second fault information storage method provided in an embodiment of the present application;

[0065] Figure 3 A schematic diagram of a memory stick provided in an embodiment of the present application;

[0066] Figure 4 A schematic diagram of a flow chart of a third fault information storage method provided in an embodiment of the present application;

[0067] Figure 5 A flowchart of a fourth fault information storage method provided in an embodiment of the present application;

[0068] Figure 6 A flowchart of a fifth fault information storage method provided in an embodiment of the present application;

[0069] Figure 7 A schematic diagram of the structure of a first fault information storage device provided in an embodiment of the present application;

[0070] Figure 8A schematic diagram of the structure of a second fault information storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0072] The present application embodiment provides a method for storing fault information, which is applied to a power management integrated circuit. Figure 1 , is a flow chart of the first fault information storage method provided in an embodiment of the present application, the method includes S101-S102.

[0073] S101, receiving first fault information sent by a basic input and output system.

[0074] The first fault information is generated by the basic input / output system when a memory fault is detected, and is used to describe the detected memory fault.

[0075] In S101, the basic input and output system (BIOS) is a collection of microprograms installed on the computer motherboard, which is responsible for hardware initialization, system self-checking and providing the most basic hardware operation functions during the startup process. When the BIOS detects a memory fault, it generates first fault information describing the detected memory fault and sends the first fault information to the power management integrated circuit.

[0076] A power management integrated circuit (PMIC) is a chip that integrates functions such as power conversion, voltage regulation, battery charge management, and system power control. PMIC encapsulates multiple output power supplies in one chip, can handle the timing of the power system, power a variety of loads, and provide protection functions in the event of overvoltage, undervoltage, overcurrent, overheating, etc., and provide power support for memory modules.

[0077] In addition, the PMIC has the property of not losing the fault information when the power is off. Storing the fault information in the PMIC can prevent the fault information stored in the PMIC from being lost when the power is off.

[0078] S102: When the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, store first fault information.

[0079] Specifically, when the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the first fault information is stored in a register Vendor Specific Region (vendor specific region) of the PMIC.

[0080] The preset number is preset by a technician with professional knowledge based on actual needs and / or experience.

[0081] Exemplarily, assuming that the preset number is M, it means that the maximum number of fault information stored in the PMIC is M. When the number of fault information stored in the PMIC does not exceed M, the first fault information is stored.

[0082] If M=3, it means that the maximum number of fault information stored in the PMIC is 3. When the number of fault information stored in the PMIC does not exceed 3, the first fault information is stored.

[0083] In addition, since some faults are caused by root problems, for example, the power supply is not powered on, resulting in the inability to load the operating system and the inability to store data in the memory stick, the root problem is that the power supply is not powered on, the operating system cannot be loaded, and the memory stick cannot store data, which is a series of problems caused by the power supply not being powered on, and the fault information of the root problem is often generated first, therefore, when storing fault information, if the number of fault information stored in the power management integrated circuit exceeds the preset number, the first fault information is not stored. That is, the fault information stored in this application is the fault information generated first, so that the stored fault information is likely to be the fault information of the root problem.

[0084] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0085] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0086] In one possible embodiment, see Figure 2 , is a flow chart of a second method for storing fault information provided in an embodiment of the present application, which is similar to the above Figure 1 Compared with the illustrated embodiment, the above method further includes S201.

[0087] S201: If the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, the fault count of the second fault information is increased by one.

[0088] The first target identifier and the second target identifier are identifiers of the same type.

[0089] In S201, the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, which refers to whether the first fault information is consistent with the second fault information in terms of fault type and fault location.

[0090] Exemplarily, assuming that the fault type of the first fault information is type 1 and the fault location is location 1, and the fault type of the second fault information is type 1 and the fault location is location 1, it means that the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information.

[0091] Assuming that the number of faults in the second fault information stored by the PMIC is N, and the fault type and fault location in the first fault information are consistent with the fault type and fault location in the second fault information stored by the PMIC, the number of faults in the second fault information is increased by one, that is, the number of faults in the second fault information is N+1.

[0092] In a possible embodiment, the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, which means whether the first fault information is consistent with the second fault information in terms of fault type, fault location, and whether the memory fault is a correctable error or an uncorrectable error.

[0093] For example, assuming that the fault type of the first fault information is type 1, the fault location is location 1, and the memory fault described in the first fault information is a correctable error, the fault type of the second fault information is type 1, the fault location is location 1, and the memory fault described in the second fault information is a correctable error, it means that the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information.

[0094] Assuming that the number of faults in the second fault information stored by the PMIC is N, the fault type and fault location in the first fault information are consistent with the fault type and fault location in the second fault information stored by the PMIC, and the memory fault described in the first fault information and the memory fault described in the second fault information are both correctable errors, then the number of faults in the second fault information is increased by one, that is, the number of faults in the second fault information is N+1.

[0095] By selecting the above embodiment, if the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, it means that the same memory fault has occurred before. Therefore, directly increasing the fault count of the second fault information by one can reduce the amount of fault information stored in the power management integrated circuit.

[0096] Specifically, after receiving the first fault information, the PMIC has the following processing methods:

[0097] Method 1: if the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, and the number of fault information stored in the PMIC does not exceed a preset number, the number of faults in the second fault information is increased by one.

[0098] Method 2: if the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, and the number of fault information stored in the PMIC exceeds a preset number, the number of faults in the second fault information is increased by one.

[0099] Method three: if the first target identifier in the first fault information is inconsistent with the second target identifier in the stored second fault information, and the amount of fault information stored in the PMIC does not exceed a preset amount, the first fault information is stored.

[0100] Mode 4: If the first target identifier in the first fault information is inconsistent with the second target identifier in the stored second fault information, and the amount of fault information stored in the PMIC exceeds a preset amount, the first fault information is not stored.

[0101] In a possible embodiment, the fault information generated by the basic input and output system includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier; wherein the first identifier indicates the fault type, the second identifier indicates the fault number, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error;

[0102] and / or

[0103] The fault type includes at least one of the following types: unknown memory error, no memory error occurs, single-bit parity error, multi-bit parity error, single chip failure, multiple chip failures, hardware failure, and access is forced to be interrupted;

[0104] and / or

[0105] The fault location indicates a memory bar where a memory fault occurs, or a memory unit where a memory fault occurs, or a row address where a memory fault occurs, or a column address where a memory fault occurs.

[0106] Exemplarily, when describing the fault type, PLATFORM MEM ERROR UNKNOWN indicates that the memory error is unknown, PLATFORM MEM ERROR NONE indicates that no memory error occurs, PLATFORM MEM ERROR SINGLEBIT ECC indicates a single-bit parity error, PLATFORM MEM ERROR MLTIBIT ECC indicates a multi-bit parity error, PLATFORM MEM ERROR SINGLESYMBOLS CHIPKILL indicates a single chip failure, PLATFORM MEM ERRORMULTISYMBOL CHIPKILL indicates multiple chip failures, PLATFORM MEM ERROR MATER ABORT indicates a hardware failure, and PLATFORM MEM ERROR TARGET ABORT indicates that access is forced to be interrupted.

[0107] The number of faults can be represented by Error Count. If the value of Error Count in a certain memory fault information is N, it means that the memory fault described in the memory fault information has occurred N times.

[0108] The fault location can be represented by Rank (memory bar), Bank (memory unit), Row (row), and Column. Rank indicates the memory bar where the memory fault occurs, Bank indicates the memory unit where the memory fault occurs, Row indicates the row address where the memory fault occurs, and Column indicates the column address where the memory fault occurs.

[0109] Faults can be divided into CE (Corrected Error) and UE (Uncorrected Error).

[0110] Among them, CE is a data error that can be corrected within the fault tolerance range of the hardware platform, and the system or application will not stop running due to this type of error, such as a single-bit data error. However, UE has exceeded the fault tolerance range of the hardware platform, which will cause the system to crash or the application to stop running, such as a multi-bit data error.

[0111] In a possible embodiment, the fault information generated by the basic input and output system also includes a checksum field and a reserved field. The checksum field can be represented by Checksum, which is used to detect errors in the data transmission process. The reserved field can be represented by Reserve, which is used to expand and record other information in the future.

[0112] See also Figure 3, is a schematic diagram of a memory stick provided in an embodiment of the present application.

[0113] from Figure 3 It can be seen that the memory module includes PMIC, SPD Hub (Serial Presence Detect Hub), DDR5 (Double Data Rate 5 Synchronous Dynamic Random-Access Memory) and gold fingers. Among them, the gold fingers are the light gray and black alternating parts, which are used to physically connect the memory module and the motherboard's memory slot.

[0114] If the maximum number of fault information stored in the PMIC is 3, in the embodiment of the present application, the storage space indicated by the register address offset 0x70-0x9F of the PMIC can be used to store 3 pieces of fault information. The format of the fault information is specifically described below using fault information 1 as an example.

[0115] See Table 1, which is a fault information table provided in an embodiment of the present application.

[0116] Table 1

[0117] The above embodiment is selected, because the fault information includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier, the first identifier indicates the fault type, the second identifier indicates the number of faults, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error, the staff can quickly locate the memory fault based on the fault information stored in the power management integrated circuit.

[0118] The present application embodiment provides a method for storing fault information, which is applied to a basic input and output system. Figure 4 , is a flow chart of a third fault information storage method provided in an embodiment of the present application, the method comprising S401-S402.

[0119] S401, detecting whether a memory failure occurs.

[0120] S402, when a memory fault occurs, generating fault information describing the memory fault, and sending the fault information to a power management integrated circuit, so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

[0121] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0122] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0123] In one possible embodiment, see Figure 5 , is a flow chart of a fourth method for storing fault information provided in an embodiment of the present application, which is similar to the above Figure 4 Compared with the embodiment shown, the above S402 can be implemented by S402A or S402B.

[0124] S402A, when a memory fault occurs and the memory fault is an uncorrectable error, generate third fault information describing the memory fault, and send the third fault information to the power management integrated circuit.

[0125] In S402A, if the memory fault is an uncorrectable error, it means that the memory fault will not be automatically repaired by the system and the severity of the memory fault is high. Therefore, the BIOS will immediately generate third fault information describing the memory fault and send the third fault information to the power management integrated circuit.

[0126] S402B, when a memory fault occurs, and the memory fault is a correctable error, and the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated, and the fourth fault information is sent to the power management integrated circuit.

[0127] In S402B, if the memory fault is a correctable error, it means that the memory fault may be automatically repaired by the system and the severity of the fault is low. Therefore, the BIOS does not immediately generate fault information describing the memory fault, but generates fourth fault information describing the memory fault of this type when the number of occurrences of the memory fault of this type has reached a preset number, and sends the fourth fault information to the power management integrated circuit.

[0128] Exemplarily, assuming that the fault type of the memory fault is a single-bit parity error, since the single-bit parity error can be automatically repaired by the system, the BIOS will not immediately generate fault information describing the memory fault when the single-bit parity error is detected for the first time. If the preset number of times is Y times, when the BIOS detects that the number of occurrences of the single-bit parity error has reached Y, it generates fourth fault information describing the single-bit parity error and sends the fourth fault information to the power management integrated circuit.

[0129] In the above embodiment, if the memory fault is an uncorrectable error, it means that the memory fault will not be automatically repaired by the system, so the basic input and output system generates third fault information describing the memory fault and sends the third fault information to the power management integrated circuit. If the memory fault is a correctable error, it means that the memory fault can be automatically repaired by the system, so when the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated and sent to the power management integrated circuit, which can not only reduce the number of fault information generated by the basic input and output system and the number of interactions between the basic input and output system and the power management integrated circuit, but also save the storage space of the power management integrated circuit.

[0130] In one possible embodiment, see Figure 6 , is a flow chart of the fifth fault information storage method provided in an embodiment of the present application, and the above method includes S601-S605.

[0131] S601, the basic input and output system performs memory training.

[0132] S602: The basic input and output system detects whether a memory failure occurs.

[0133] If so, it means that the memory fails, and S603 is executed; if not, it means that the memory does not fail, but other components of the electronic device may still fail, so S604 is continued.

[0134] S603, the basic input and output system generates fault information describing the memory fault, and sends the fault information to the power management integrated circuit, so that the power management integrated circuit stores the fault information when the amount of the stored fault information does not exceed a preset amount.

[0135] S604, the basic input and output system performs a power-on self-test.

[0136] Among them, the power-on self-test includes cache test, I / O (Input / Output) device test, graphics card test, processor test, power management test, motherboard self-test, etc.

[0137] S605: When the hardware device works normally, the basic input and output system loads the operating system.

[0138] Corresponding to the above-mentioned fault information storage method, the embodiment of the present application further provides a power management integrated circuit, which is used to perform the following operations:

[0139] Receiving first fault information sent by a basic input / output system; wherein the first fault information is generated by the basic input / output system when a memory fault is detected, and is used to describe the detected memory fault;

[0140] When the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the first fault information is stored.

[0141] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0142] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0143] In a possible embodiment, the power management integrated circuit is further configured to perform the following operations:

[0144] If the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, the fault count of the second fault information is increased by one; wherein the first target identifier and the second target identifier are identifiers of the same type.

[0145] By selecting the above embodiment, if the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, it means that the same memory fault has occurred before. Therefore, directly increasing the fault count of the second fault information by one can reduce the amount of fault information stored in the power management integrated circuit.

[0146] In a possible embodiment, the fault information generated by the basic input and output system includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier; wherein the first identifier indicates the fault type, the second identifier indicates the fault number, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error;

[0147] and / or

[0148] The fault type includes at least one of the following types: unknown memory error, no memory error occurs, single-bit parity error, multi-bit parity error, single chip failure, multiple chip failures, hardware failure, and access is forced to be interrupted;

[0149] and / or

[0150] The fault location indicates a memory bar where a memory fault occurs, or a memory unit where a memory fault occurs, or a row address where a memory fault occurs, or a column address where a memory fault occurs.

[0151] The above embodiment is selected, because the fault information includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier, the first identifier indicates the fault type, the second identifier indicates the number of faults, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error, the staff can quickly locate the memory fault based on the fault information stored in the power management integrated circuit.

[0152] Corresponding to the aforementioned fault information storage method, the embodiment of the present application further provides a basic input and output system, which is used to perform the following operations:

[0153] Detect whether a memory failure occurs;

[0154] In the event of a memory failure, fault information describing the memory failure is generated and sent to the power management integrated circuit, so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

[0155] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0156] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0157] In a possible embodiment, the basic input and output system is used to perform the following operations:

[0158] When a memory fault occurs and the memory fault is an uncorrectable error, third fault information describing the memory fault is generated and the third fault information is sent to the power management integrated circuit;

[0159] or,

[0160] When a memory fault occurs, and the memory fault is a correctable error, and the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated, and the fourth fault information is sent to the power management integrated circuit.

[0161] In the above embodiment, if the memory fault is an uncorrectable error, it means that the memory fault will not be automatically repaired by the system, so the basic input and output system generates third fault information describing the memory fault and sends the third fault information to the power management integrated circuit. If the memory fault is a correctable error, it means that the memory fault can be automatically repaired by the system, so when the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated and sent to the power management integrated circuit, which can not only reduce the number of fault information generated by the basic input and output system and the number of interactions between the basic input and output system and the power management integrated circuit, but also save the storage space of the power management integrated circuit.

[0162] Corresponding to the aforementioned fault information storage method, an embodiment of the present application also provides an electronic device, the electronic device comprising a power management integrated circuit and a basic input-output system, the power management integrated circuit being any power management integrated circuit in the aforementioned fault information storage method, and the basic input-output system being any basic input-output system in the aforementioned fault information storage method.

[0163] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0164] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0165] Corresponding to the above-mentioned fault information storage method, the embodiment of the present application also provides a fault information storage device, which is applied to a power management integrated circuit, see Figure 7 , is a first fault information storage device provided in an embodiment of the present application, the device comprising:

[0166] The information receiving module 701 is used to receive first fault information sent by the basic input and output system; wherein the first fault information is generated by the basic input and output system when a memory fault is detected, and is used to describe the detected memory fault;

[0167] The information storage module 702 is used to store the first fault information when the amount of fault information stored in the power management integrated circuit does not exceed a preset amount.

[0168] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0169] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0170] In a possible embodiment, the above device further includes:

[0171] The information updating module is used to increase the fault count of the second fault information by one if the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information; wherein the first target identifier and the second target identifier are identifiers of the same type.

[0172] By selecting the above embodiment, if the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, it means that the same memory fault has occurred before. Therefore, directly increasing the fault count of the second fault information by one can reduce the amount of fault information stored in the power management integrated circuit.

[0173] In a possible embodiment, the fault information generated by the basic input and output system includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier; wherein the first identifier indicates the fault type, the second identifier indicates the fault number, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error;

[0174] and / or

[0175] The fault type includes at least one of the following types: unknown memory error, no memory error occurs, single-bit parity error, multi-bit parity error, single chip failure, multiple chip failures, hardware failure, and access is forced to be interrupted;

[0176] and / or

[0177] The fault location indicates a memory bar where a memory fault occurs, or a memory unit where a memory fault occurs, or a row address where a memory fault occurs, or a column address where a memory fault occurs.

[0178] The above embodiment is selected, because the fault information includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier, the first identifier indicates the fault type, the second identifier indicates the number of faults, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error, the staff can quickly locate the memory fault based on the fault information stored in the power management integrated circuit.

[0179] Corresponding to the above-mentioned fault information storage method, the embodiment of the present application also provides a fault information storage device, which is applied to the basic input and output system, see Figure 8 , is a second fault information storage device provided in an embodiment of the present application, the device comprising:

[0180] A fault detection module 801 is used to detect whether a memory fault occurs;

[0181] The information generation module 802 is used to generate fault information describing the memory fault when a memory fault occurs, and send the fault information to the power management integrated circuit so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

[0182] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0183] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0184] In a possible embodiment, the information generating module 802 is specifically configured to:

[0185] When a memory fault occurs and the memory fault is an uncorrectable error, third fault information describing the memory fault is generated and the third fault information is sent to the power management integrated circuit;

[0186] or,

[0187] When a memory fault occurs, and the memory fault is a correctable error, and the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated, and the fourth fault information is sent to the power management integrated circuit.

[0188] In the above embodiment, if the memory fault is an uncorrectable error, it means that the memory fault will not be automatically repaired by the system, so the basic input and output system generates third fault information describing the memory fault and sends the third fault information to the power management integrated circuit. If the memory fault is a correctable error, it means that the memory fault can be automatically repaired by the system, so when the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated and sent to the power management integrated circuit, which can not only reduce the number of fault information generated by the basic input and output system and the number of interactions between the basic input and output system and the power management integrated circuit, but also save the storage space of the power management integrated circuit.

[0189] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned fault information storage methods are implemented.

[0190] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0191] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0192] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any fault information storage method in the above embodiments.

[0193] By selecting the above embodiment, the basic input / output system generates first fault information when a memory fault is detected. After the power management integrated circuit receives the first fault information sent by the basic input / output system, the first fault information is stored in the power management integrated circuit if the number of fault information stored in the power management integrated circuit does not exceed a preset number. Since the first fault information is used to describe the memory fault detected by the basic input / output system, the staff can locate the memory fault based on the first fault information stored in the power management integrated circuit.

[0194] Furthermore, since the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the staff can quickly locate the memory fault from a small amount of fault information, thereby improving the efficiency of memory fault location.

[0195] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0196] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0197] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the power management integrated circuit, basic input and output system, electronic device, device, and storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0198] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A method for storing fault information, characterized in that: Applied to a power management integrated circuit, the method comprises: receiving first fault information sent by a basic input / output system; wherein the first fault information is generated by the basic input / output system when a memory fault is detected, and is used to describe the detected memory fault; When the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the first fault information is stored.

2. The method according to claim 1, characterized in that The method further comprises: If the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, the fault count of the second fault information is increased by one; wherein the first target identifier and the second target identifier are identifiers of the same type.

3. The method according to claim 1 or 2, characterized in that: The fault information generated by the basic input and output system includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier; wherein the first identifier indicates the fault type, the second identifier indicates the fault number, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error; and / or The fault type includes at least one of the following types: unknown memory error, no memory error, single-bit parity error, multi-bit parity error, single chip failure, multiple chip failures, hardware failure, and forced access interruption; and / or The fault location indicates a memory bar where a memory fault occurs, or a memory unit where a memory fault occurs, or a row address where a memory fault occurs, or a column address where a memory fault occurs.

4. A method for storing fault information, characterized in that: Applied to a basic input and output system, the method comprises: Detect whether a memory failure occurs; In the event of a memory failure, fault information describing the memory failure is generated and sent to a power management integrated circuit, so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

5. The method according to claim 4, characterized in that In the event of a memory failure, generating failure information describing the memory failure and sending the failure information to a power management integrated circuit comprises: When a memory fault occurs and the memory fault is an uncorrectable error, generating third fault information describing the memory fault, and sending the third fault information to the power management integrated circuit; or, When a memory fault occurs, and the memory fault is a correctable error, and the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated and sent to the power management integrated circuit.

6. A power management integrated circuit, characterized in that: The power management integrated circuit is used to perform the following operations: receiving first fault information sent by a basic input / output system; wherein the first fault information is generated by the basic input / output system when a memory fault is detected, and is used to describe the detected memory fault; When the amount of fault information stored in the power management integrated circuit does not exceed a preset amount, the first fault information is stored.

7. The power management integrated circuit according to claim 6, characterized in that: The power management integrated circuit is also used to perform the following operations: If the first target identifier in the first fault information is consistent with the second target identifier in the stored second fault information, the fault count of the second fault information is increased by one; wherein the first target identifier and the second target identifier are identifiers of the same type.

8. The power management integrated circuit according to claim 6 or 7, characterized in that: The fault information generated by the basic input and output system includes at least one of the following information: a first identifier, a second identifier, a third identifier, and a fourth identifier; wherein the first identifier indicates the fault type, the second identifier indicates the fault number, the third identifier indicates the fault location, and the fourth identifier indicates whether the fault is a correctable error or an uncorrectable error; and / or The fault type includes at least one of the following types: unknown memory error, no memory error, single-bit parity error, multi-bit parity error, single chip failure, multiple chip failures, hardware failure, and forced access interruption; and / or The fault location indicates a memory bar where a memory fault occurs, or a memory unit where a memory fault occurs, or a row address where a memory fault occurs, or a column address where a memory fault occurs.

9. A basic input and output system, characterized in that: The basic input and output system is used to perform the following operations: Detect whether a memory failure occurs; In the event of a memory failure, fault information describing the memory failure is generated and sent to a power management integrated circuit, so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

10. The basic input-output system according to claim 9, characterized in that: The basic input and output system is used to perform the following operations: When a memory fault occurs and the memory fault is an uncorrectable error, generating third fault information describing the memory fault, and sending the third fault information to the power management integrated circuit; or, When a memory fault occurs, and the memory fault is a correctable error, and the number of occurrences of this type of memory fault has reached a preset number, fourth fault information describing this type of memory fault is generated and sent to the power management integrated circuit.

11. An electronic device, characterized in that: The electronic device comprises a power management integrated circuit and a basic input-output system, wherein the power management integrated circuit is the power management integrated circuit described in any one of claims 6 to 8, and the basic input-output system is the basic input-output system described in claim 9 or 10.

12. A fault information storage device, characterized in that: Applied to a power management integrated circuit, the device comprises: An information receiving module, used for receiving first fault information sent by a basic input and output system; wherein the first fault information is generated by the basic input and output system when a memory fault is detected, and is used for describing the detected memory fault; The information storage module is used to store the first fault information when the amount of fault information stored in the power management integrated circuit does not exceed a preset amount.

13. A fault information storage device, characterized in that: Applied to a basic input and output system, the device comprises: A fault detection module, used to detect whether a memory fault occurs; An information generation module is used to generate fault information describing the memory fault when a memory fault occurs, and send the fault information to a power management integrated circuit so that the power management integrated circuit stores the fault information when the amount of stored fault information does not exceed a preset amount.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of claims 1-3 or 4-5 are implemented.

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