Data storage method and device, data reading method and device and readable medium

Abstract

The invention provides a data storage method which is applied to a data processing device, a first linked list used for managing on-chip storage and a second linked list used for managing off-chip storage are configured in the data processing device, the first linked list and the second linked list comprise queue information and node switching information, the queue information of the first linked list comprises a storage mark, and the node switching information comprises node switching information. The storage mark is used for representing that the data storage mode is on-chip storage or off-chip storage; the method comprises the following steps: determining a first storage mode of to-be-stored data, and determining a second storage mode of previous data storage according to a storage mark; under the condition that the first storage mode is different from the second storage mode, determining a target node of previous data storage, updating node switching information of the target node in a linked list corresponding to the target node, and updating a storage mark; on-chip and off-chip storage resources can be flexibly used, and unbalanced use of cache addresses is avoided. The invention further provides a data reading method, a data processing device and a readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data storage method and device, a data reading method and device, and a readable medium. Background Art

[0002] The linked list storage management realizes the concatenation of data stored in the RAM (Random Access Memory) through the queue linked list and the free linked list.

[0003] Currently, linked list storage management technologies include: multi-queue linked lists, on-chip and off-chip shared linked lists, on-chip and off-chip node division, etc.

[0004] At present, most of the on-chip and off-chip linked list concatenation schemes include: (1) After the on-chip cache is occupied, the off-chip cache resources are occupied. At this time, a set of linked lists can be used to concatenate the on-chip and off-chip linked list nodes, or two sets of linked list nodes but the addresses are related to each other. However, this scheme has a fixed way of utilizing on-chip and off-chip resources and is not flexible enough. (2) The on-chip and off-chip caches jointly maintain a set of linked list nodes, and choose to store data on or off the chip based on the on-chip and off-chip tags. The on-chip and off-chip nodes are connected in series. However, this scheme has the problem of uneven RAM access due to the high address jumps of the on-chip and off-chip caches. Summary of the invention

[0005] The present invention provides a data storage method and device, a data reading method and device, and a readable medium.

[0006] In a first aspect, an embodiment of the present disclosure provides a data storage method, which is applied to a data processing device, wherein a first linked list for managing on-chip storage and a second linked list for managing off-chip storage are configured in the data processing device, wherein the first linked list and the second linked list include queue information and node switching information, wherein the queue information of the first linked list includes a storage tag, wherein the storage tag is used to indicate a storage mode of data, wherein the storage mode includes on-chip storage and off-chip storage; the method includes:

[0007] Determining a first storage method for data to be stored, and storing the data to be stored according to the first storage method;

[0008] Determine a second storage mode of the previous data storage according to the storage mark;

[0009] When the first storage method is different from the second storage method, determine the target node of the previous data storage, update the node switching information of the target node in the linked list corresponding to the target node, and update the storage mark; the linked list corresponding to the target node is one of the first linked list and the second linked list.

[0010] In another aspect, an embodiment of the present disclosure further provides a data reading method, which is applied to a data processing device, wherein a first linked list for managing on-chip storage and a second linked list for managing off-chip storage are configured in the data processing device, wherein the first linked list and the second linked list include queue information and node switching information, and the queue information of the first linked list includes a read tag, and the read tag is used to indicate a data reading method, and the reading method includes on-chip reading and off-chip reading; the method includes:

[0011] Determining a reading method of the data to be read according to the reading mark;

[0012] In the case where the reading mode is off-chip reading, determining a target node according to the queue information of the second linked list;

[0013] Obtain node switching information of the target node in the second linked list;

[0014] The to-be-read data is read in the target node, wherein after it is determined according to the node switching information that all data stored in the off-chip cache has been read, the read mark is updated to a value indicating on-chip reading.

[0015] On the other hand, an embodiment of the present disclosure also provides a data processing device, comprising: one or more processors; a memory on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the data storage method as described above; one or more I / O interfaces, connected between the processor and the memory, configured to implement information interaction between the processor and the memory.

[0016] On the other hand, an embodiment of the present disclosure also provides a data processing device, comprising: one or more processors; a memory on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the data reading method as described above, and / or the data reading method as described above; one or more I / O interfaces, connected between the processor and the memory, configured to implement information interaction between the processor and the memory.

[0017] On the other hand, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein when the program is executed, the data storage method or the data reading method as described above is implemented.

[0018] The data processing method provided by the embodiment of the present disclosure is applied to a data processing device, wherein a first linked list for managing on-chip storage and a second linked list for managing off-chip storage are configured in the data processing device, the first linked list and the second linked list include queue information and node switching information, the queue information of the first linked list includes a storage tag, and the storage tag is used to indicate that the storage mode of the data is on-chip storage or off-chip storage; the method comprises: determining a first storage mode of the data to be stored, and determining a second storage mode of the previous data storage according to the storage tag; when the first storage mode is different from the second storage mode, determining a target node of the previous data storage, updating the node switching information of the target node in the linked list corresponding to the target node, and updating the storage tag; in the embodiment of the present disclosure, the on-chip cache and the off-chip cache respectively maintain a linked list, record the node switching information in the two linked lists, and maintain the storage tag in the linked list of the on-chip cache, in the data storage process, the storage tag and the node switching information can be used to realize the switching between on-chip storage and off-chip storage, the on-chip and off-chip storage resources can be used flexibly, and the problem of uneven use of cache addresses can be effectively solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the principle of data storage and reading provided in an embodiment of the present disclosure;

[0020] Figure 2 Schematic diagram of the data storage method provided in the embodiment of the present disclosure Figure 1 ;

[0021] Figure 3 Schematic diagram of the data storage method provided in the embodiment of the present disclosure Figure 2 ;

[0022] Figure 4 Schematic diagram of the data reading method provided in the embodiment of the present disclosure Figure 1 ;

[0023] Figure 5 Schematic diagram of the data reading method provided in the embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0024] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0025] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0027] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of idealized schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0029] The on-chip cache can be a single linked list structure or a multi-linked list structure to meet the line speed requirements of the system design. The multi-linked list structure consists of multiple sub-linked lists, which are connected in series to form a queue linked list. The off-chip node implements queue linked list management through the "node aggregation" method. Through the "node aggregation" method, blocks (data blocks) with consecutive addresses can be combined into a chunk (group block), collectively referred to as a chunk_block structure. When the on-chip and off-chip linked lists share the chunk_block structure, if the on-chip and off-chip data are mixed, some linked list nodes are used on the chip and some nodes are used off-chip, which will cause the read and write side access balance of the off-chip cache to be very poor. In other words, when the on-chip cache and the off-chip cache share a set of linked lists, the linked list nodes are randomly allocated, and the address usage process of the on-chip cache and the off-chip cache is random, which may cause some addresses to be occupied by the on-chip cache, the channel addresses of the off-chip cache are unevenly used, and the performance of the off-chip cache is reduced.

[0030] To solve the above problems, an embodiment of the present disclosure provides a data storage method, which is applied to a data processing device, wherein a first linked table for managing on-chip storage and a second linked table for managing off-chip storage are configured in the data processing device, such as Figure 1As shown, the arrows connecting the on-chip address 1, on-chip address 2, on-chip address 3 and on-chip address 4 represent the first linked list, the arrows connecting the off-chip chunk address 1, off-chip chunk address 2 and off-chip chunk address 3 represent the second linked list, and the remaining arrows represent the actual linked lists formed during the data access process, starting from Figure 1 It can be seen that on-chip and off-chip data access can be achieved.

[0031] The first linked list and the second linked list may include queue information and node switching information. The queue information of the first linked list may include a storage flag (tp_flag) and a read flag (hp_flag). The storage flag (tp_flag) is used to indicate the storage method of the data, and the storage methods include on-chip storage and off-chip storage; the read flag (hp_flag) is used to indicate the reading method of the data, and the reading methods include on-chip reading and off-chip reading.

[0032] The queue information definition of the first linked list is shown in Table 1:

[0033] Table 1

[0034]

[0035] The node switching information of each node in the first linked list is defined as shown in Table 2:

[0036] Table 2

[0037]

[0038] The queue information definition of the second linked list is shown in Table 3:

[0039] Table 3

[0040] chunk_hp Off-chip node head pointer chunk_tp Off-chip node tail pointer chunk_cti Block queue count, block storage offset chunk_cto Block dequeue count, block read offset

[0041] The node switching information of each node in the second linked list is defined as shown in Table 4:

[0042] Table 4

[0043]

[0044] It should be noted that Table 1 and Table 3 are for data storage queues. An on-chip storage queue corresponds to Table 1, and an off-chip storage queue corresponds to Table 3. Table 2 and Table 4 are for data storage nodes. An on-chip storage node corresponds to Table 2, and an off-chip data storage node (i.e., chunk node) corresponds to Table 4.

[0045] Based on the above definitions of the first linked list and the second linked list, the present disclosure provides a data storage method, such as Figure 2 As shown, the method comprises the following steps:

[0046] Step S11, determining a first storage method for data to be stored, and storing the data to be stored according to the first storage method.

[0047] In this step, it is determined whether the data to be stored needs to be stored in an on-chip cache or an off-chip cache. The embodiment of the present disclosure does not limit the specific implementation method of determining the first storage method of the data to be stored. Exemplarily, the storage method can be determined based on a policy set by the user, or a specified storage method can be used.

[0048] Step S12, determining the second storage mode of the previous data storage according to the storage mark.

[0049] Read tp_flag in the queue information of the first linked list, and determine the second storage mode of the previous data storage according to the value of tp_flag. Exemplarily, if tp_flag=0, it means that the previous data storage is on-chip storage, that is, the second storage mode is on-chip storage; if tp_flag=1, it means that the previous data storage is off-chip storage, that is, the second storage mode is off-chip storage.

[0050] Step S13, when the first storage mode is different from the second storage mode, determining the target node of the previous data storage, updating the node switching information of the target node in the linked list corresponding to the target node, and updating the storage mark.

[0051] If the first storage mode is different from the second storage mode, it means that the on-chip storage and off-chip storage need to be switched. In this case, the target node is determined and the node switching information of the target node is updated. The node switching information is used to indicate whether the node has switched the storage mode and the switching position. The target node is the node used to store the previous data when the data was last stored. If the previous data was stored as on-chip storage, the target node is an on-chip cache node, and the linked list corresponding to the target node is the first linked list; if the previous data was stored as off-chip storage, the target node is an off-chip cache node, that is, a chunk node, and the linked list corresponding to the target node is the second linked list.

[0052] It should be noted that when the first storage method is different from the second storage method, tp_flag must also be updated. For example, if the first storage method is on-chip storage and the second storage method is off-chip storage, the value of tp_flag is updated from 0 to 1; if the first storage method is off-chip storage and the second storage method is on-chip storage, the value of tp_flag is updated from 1 to 0.

[0053] The data processing method provided by the embodiment of the present disclosure is applied to a data processing device, wherein a first linked list for managing on-chip storage and a second linked list for managing off-chip storage are configured in the data processing device, the first linked list and the second linked list include queue information and node switching information, the queue information of the first linked list includes a storage tag, and the storage tag is used to indicate that the storage mode of the data is on-chip storage or off-chip storage; the method comprises: determining a first storage mode of the data to be stored, and determining a second storage mode of the previous data storage according to the storage tag; when the first storage mode is different from the second storage mode, determining a target node of the previous data storage, updating the node switching information of the target node in the linked list corresponding to the target node, and updating the storage tag; in the embodiment of the present disclosure, the on-chip cache and the off-chip cache respectively maintain a linked list, record the node switching information in the two linked lists, and maintain the storage tag in the linked list of the on-chip cache, in the data storage process, the storage tag and the node switching information can be used to realize the switching between on-chip storage and off-chip storage, the on-chip and off-chip storage resources can be used flexibly, and the problem of uneven use of cache addresses can be effectively solved.

[0054] Figure 3 Schematic diagram of the data storage method provided in the embodiment of the present disclosure Figure 2 In some embodiments, as Figure 3 As shown, after determining the second storage mode of the previous data storage according to the storage mark (i.e., step S12), the data storage method may further include the following steps:

[0055] Step S13': when the first storage mode is the same as the second storage mode, the storage mark is kept unchanged.

[0056] If the first storage mode is the same as the second storage mode, it means that the storage mode is not switched, and there is no need to update the value of tp_flag, that is, the value of tp_flag remains unchanged.

[0057] It should be noted that step S11 and step S12 in this embodiment are the same as Figure 2 Step S11 and step S12 in the illustrated embodiment are the same and will not be described in detail herein.

[0058] The first storage mode is different from the second storage mode, indicating that the storage mode is switched. The storage mode switching is divided into the following two situations: one is switching from off-chip storage to on-chip storage, and the other is switching from on-chip storage to off-chip storage. The following describes these two situations respectively.

[0059] In some embodiments, the second storage mode is off-chip storage, and the linked list corresponding to the target node is the second linked list, that is, switching from off-chip storage to on-chip storage. As shown in Table 4, the node switching information in the second linked list includes chunk_change_vld and chunk_change_cti. Accordingly, the node switching information of the target node is updated in the linked list corresponding to the target node (i.e., step S13), including the following steps: updating the first switching identifier (chunk_change_vld) and the switching position offset (chunk_change_cti) of the target node in the second linked list, the first switching identifier is used to indicate whether to switch to on-chip storage, and the switching position offset is used to indicate the address of the data block for switching the storage mode.

[0060] In some embodiments, the updating of the first switching flag (chunk_change_vld) and the switching position offset (chunk_change_cti) of the target node in the second linked list includes the following steps: updating the first switching flag (chunk_change_vld) to a value indicating that the storage mode is switched to the on-chip storage, and updating the switching position offset to the offset address of the data block switched to the on-chip storage. Exemplarily, chunk_change_vld=1, and updating chunk_change_cti to the address of the data block of the chunk node for switching to the on-chip storage. Figure 1 Taking the second linked list shown as an example, if the target node is off-chip chunk address 2, that is, the storage mode is switched at the last block of the chunk node at off-chip chunk address 2, then chunk_change_cti=block address n of chunk address 2.

[0061] In some embodiments, as shown in Table 1, the queue information of the first linked list may further include a head node switching mark (hp_change_vld), where the head node switching mark indicates whether the head node is to switch the storage mode. For example, if hp_change_vld=0, it indicates that the head node does not switch the storage mode; if hp_change_vld=1, it indicates that the head node switches the storage mode.

[0062] In the case where the first storage mode is the same as the second storage mode, the storage mode is not switched when storing the data to be stored, and the data storage method may further include the following steps: if the data to be stored is the first data stored in the on-chip storage queue, then the first node switching mark (hp_change_vld) is updated, that is, if only the data to be stored is stored in the on-chip cache, that is, the data to be stored is the first on-chip storage data, then the first node of the on-chip linked list queue is not switched. In some embodiments, the first node switching mark (hp_change_vld) may be updated to a value indicating that the first node of the queue of the first linked list is not switched to off-chip storage, exemplarily, hp_change_vld=0.

[0063] In some embodiments, the second storage mode is on-chip storage, and the linked list corresponding to the target node is the first linked list, that is, switching from on-chip storage to off-chip storage. Correspondingly, the updating of the node switching information of the target node in the linked list corresponding to the target node (i.e., step S13) includes the following steps: updating the second switching flag (imen_next_change_flag) of the target node in the first linked list or updating the third switching flag (hp_change_vld) in the queue information in the first linked list; wherein the second switching flag is used to indicate that the next hop is switched to off-chip storage, and the third switching flag is used to indicate whether the first node of the first linked list is switched to off-chip storage. The second switching flag (imen_next_change_flag) is stored in Table 2 of the first linked list, and the third switching flag (hp_change_vld) is stored in Table 1 of the first linked list.

[0064] In some embodiments, the updating of the second switching flag (imen_next_change_flag) of the target node in the first linked list or the updating of the third switching flag (hp_change_vld) in the queue information in the first linked list includes the following steps: when there is one data stored in the on-chip storage queue, the third switching flag (hp_change_vld) in the queue information is updated in the first linked list, that is, the third switching flag is updated to a value indicating that the storage mode is switched to off-chip storage, exemplarily, hp_change_vld=1; when there are multiple data stored in the on-chip storage queue, the second switching flag (imen_next_change_flag) of the target node is updated in the first linked list, that is, the second switching flag is updated to a value indicating that the next hop will switch the storage mode to off-chip storage, exemplarily, imen_next_change_flag=1.

[0065] In some embodiments, as shown in Table 3, the queue information of the second linked list includes a data block storage offset (chunk_cti). When the first storage method is off-chip storage and the first storage method is the same as the second storage method, the data storage method may further include: updating the data block storage offset.

[0066] As shown in Table 3, the queue information of the second linked list may also include an off-chip node head pointer (chunk_hp) and an off-chip node tail pointer (chunk_tp). When the first storage mode is off-chip storage, and the first storage mode is the same as the second storage mode, the pointer information of the off-chip node needs to be updated. Specifically, if the data to be stored is the first data stored in the off-chip storage queue, the off-chip node head pointer (chunk_hp) and the off-chip node tail pointer (chunk_tp) are updated; if the stored data is not the first data stored in the off-chip storage queue, that is, data has been stored in the off-chip storage queue, the off-chip node tail pointer (chunk_tp) is updated.

[0067] The disclosed embodiment also provides a data reading method, which is applied to a data processing device. The data processing device is configured with a first linked list for managing on-chip storage and a second linked list for managing off-chip storage. The first linked list and the second linked list include queue information and node switching information. The queue information of the first linked list includes a read tag, which is used to indicate a data reading method, including on-chip reading and off-chip reading. It should be noted that the data processing device and the aforementioned data processing device can be the same data processing device, that is, the data processing device can have both data storage and data reading functions. Figure 4 As shown, the data reading method comprises the following steps:

[0068] Step S21, determining a reading method for the data to be read according to the reading mark.

[0069] Read the hp_flag in the queue information of the first linked list, and determine the reading mode of the data to be read according to the value of hp_flag. The reading mode of the data to be read depends on the storage mode of the data. If the storage mode of the data is on-chip storage, the reading mode is on-chip reading; if the storage mode of the data is off-chip storage, the reading mode is off-chip reading. Exemplarily, hp_flag=0, the reading mode of the data to be read is on-chip reading; hp_flag=1, the reading mode of the data to be read is off-chip reading.

[0070] Step S22, when the reading mode is off-chip reading, determine the target node according to the queue information of the second linked list.

[0071] The target node refers to the node used to store the data to be read.

[0072] Step S23, obtaining the node switching information of the target node in the second linked list.

[0073] After the target node is determined, the corresponding node switching information can be obtained through Table 4 corresponding to the target node.

[0074] Step S24, reading the to-be-read data in the target node, wherein after it is determined according to the node switching information that all the data stored in the off-chip cache has been read, the read mark is updated to a value indicating on-chip reading.

[0075] The data reading method of the disclosed embodiment is applied to a data processing device, wherein the data processing device is configured with a first linked list for managing on-chip storage and a second linked list for managing off-chip storage, wherein the first linked list and the second linked list include queue information and node switching information, wherein the queue information of the first linked list includes a read tag, wherein the read tag is used to indicate a data reading mode, wherein the reading mode includes on-chip reading and off-chip reading; wherein the method includes: determining a reading mode of the data to be read according to the read tag; in the case where the reading mode is off-chip reading, determining a target node according to the queue information of the second linked list; obtaining node switching information of the target node in the second linked list; reading the data to be read in the target node, wherein after determining that all data stored in the off-chip cache have been read according to the node switching information, the read tag is updated to a value indicating on-chip reading. In the disclosed embodiment, the on-chip cache and the off-chip cache respectively maintain a linked list, the node switching information is recorded in the two linked lists, and the read tag is maintained in the linked list of the on-chip cache, wherein in the data reading process, the read tag and the node switching information can be used to realize the switching between on-chip reading and off-chip reading, the on-chip and off-chip storage resources can be used flexibly, and the problem of uneven use of cache addresses can be effectively solved.

[0076] In some embodiments, as shown in Table 3, the queue information of the second linked list includes an off-chip node head pointer (chunk_hp) and a data block read offset (chunk_cto), and the step of determining the target node according to the queue information of the second linked list (i.e., step S22) includes the following steps: determining the target node according to the sum of the off-chip node head pointer and the data block read offset. In other words, the off-chip node head pointer (chunk_hp) is moved backward to a position after the data block read offset (chunk_cto), which is the position of the target node.

[0077] In some embodiments, as shown in Table 3, the queue information of the second linked list includes a data block read offset (chunk_cto), and as shown in Table 4, the node switching information includes a first switching identifier (chunk_change_vld) and a switching position offset (chunk_change_cti), and the first switching identifier is used to indicate whether to switch to on-chip storage.

[0078] The step of determining that all data stored in the off-chip cache have been read out based on the node switching information (i.e., step S24) includes the following steps: when the first switching flag (chunk_change_vld) indicates switching to on-chip storage, and the data block read offset (chunk_cto) is equal to the switching position offset (chunk_change_cti), determining that all data stored in the off-chip cache have been read out. Exemplarily, when chunk_change_vld=1 and chunk_cto=chunk_change_cti, it is considered that all data stored in the off-chip cache have been read out, and at this time, hp flag=0.

[0079] In some embodiments, as shown in Table 1, the update queue information of the first linked list includes a third switching flag (hp_change_vld), and the third switching flag (hp_change_vld) is used to indicate whether the first node of the first linked list is switched to the off-chip storage. For example, if hp_change_vld=0, it means that the first node of the first linked list is not switched to the off-chip storage; if hp_change_vld=1, it means that the first node of the first linked list is switched to the off-chip storage.

[0080] like Figure 5 As shown, after determining the reading mode of the data to be read according to the reading mark (i.e., step S21), the data reading method further includes the following steps:

[0081] Step S31, when the reading mode is on-chip reading, determining the target node according to the queue information of the first linked list.

[0082] In this step, the target node may be determined according to information such as the first linked list head pointer (imem_hp) and the first linked list tail pointer (imem_tp) in the queue information of the first linked list.

[0083] Step S32: Obtain a second switching identifier of the target node from the first linked list, where the second switching identifier is used to indicate that the next hop is switched to an off-chip storage.

[0084] Step S33, reading the to-be-read data from the target node, and updating the third switching identifier and the reading mark according to the second switching identifier of the target node.

[0085] When the second switch flag (imen_next_change_flag) of the target node indicates that the next hop is switched to off-chip storage, the third switch flag (hp_change_vld) is updated to a value indicating that the first node of the first linked list is switched to off-chip storage, and the read flag (hp_flag) is updated to a value indicating on-chip reading. Exemplarily, if imen_next_change_flag=1, hp_change_vld=1, and hp_flag=0. It should be noted that, when the second switch flag (imen_next_change_flag) of the target node indicates that the next hop is not switched to off-chip storage, the third switch flag (hp_change_vld) and the read flag (hp_flag) are not updated.

[0086] Since the on-chip cache resources are limited, the off-chip cache needs to be used according to the usage requirements. When the on-chip cache and the off-chip cache are used at the same time, the off-chip cache can be divided into multiple nodes (chunk nodes), each node contains multiple cache units, and the chunk_block structure can effectively save RAM resources and off-chip RAM access delay compared to the traditional single linked list structure. Therefore, the embodiment of the present disclosure adopts the form of separate management of on-chip cache nodes and off-chip cache nodes, taking the on-chip single linked list and off-chip node aggregation as an example (the on-chip and off-chip linked lists can use single linked lists, multi-linked lists, and chunk_block linked list combinations, respectively).

[0087] The off-chip linked list uses a chunk_block structure. A chunk node contains n blocks. For the same queue, a new chunk address can only be applied for after all the blocks in each chunk node are used up.

[0088] Each chunk node uses the chunk_change_vld tag to indicate whether to switch to on-chip storage, and records the switch position offset chunk_change_cti, indicating which block to switch to. When the off-chip block dequeue count chunk_cto is equal to chunk_change_cti, the off-chip data reading ends and switches to on-chip data reading. For the off-chip linked list, in order to save resources, a chunk node includes at least 16 data blocks (blocks). In this way, after switching from off-chip to on-chip and from on-chip to off-chip, at least 16 blocks cannot be switched. Each chunk node only needs to record a chunk_change_vld tag and chunk_change_cti.

[0089] The queue of the on-chip linked list needs to maintain the head pointer switching mark hp_change_vld, and each node of the on-chip linked list needs to maintain the next hop switching mark imem_next_change_flag. The update of these two pieces of information needs to be known after the arrival of the next data packet to know whether to switch. Therefore, when storing data, the corresponding mark can be written as 0. If switching is required when the next data packet arrives, it is set to 1. This can avoid maintaining the information of the previous linked list when the on-chip linked list is continuously queued.

[0090] An embodiment of the present disclosure also provides a data processing device, including: one or more processors; a memory on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the data storage method as described above, and / or the data reading method as described above; one or more I / O interfaces, connected between the processor and the memory, configured to implement information interaction between the processor and the memory.

[0091] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU) and the like; the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, and can realize information exchange between the processor and the memory, including but not limited to the data bus (Bus) and the like.

[0092] The embodiments of the present disclosure further provide a computer-readable medium on which a computer program is stored, wherein when the computer program is executed, the data storage method or the data reading method provided in the aforementioned embodiments is implemented.

[0093] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, the functional modules / units in the device may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0094] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A data storage method, characterized in that: The method is applied to a data processing device, wherein a first linked list for managing on-chip storage and a second linked list for managing off-chip storage are configured in the data processing device, wherein the first linked list and the second linked list include queue information and node switching information, wherein the queue information of the first linked list includes a storage tag, wherein the storage tag is used to indicate a storage mode of data, wherein the storage mode includes on-chip storage and off-chip storage; and wherein the method includes: Determining a first storage method for data to be stored, and storing the data to be stored according to the first storage method; Determine a second storage mode of the previous data storage according to the storage mark; When the first storage method is different from the second storage method, determine the target node of the previous data storage, update the node switching information of the target node in the linked list corresponding to the target node, and update the storage mark; the linked list corresponding to the target node is one of the first linked list and the second linked list.

2. The method according to claim 1, characterized in that After determining the second storage mode of the previous data storage according to the storage mark, the method further includes: When the first storage mode is the same as the second storage mode, the storage mark is kept unchanged.

3. The method according to claim 2, characterized in that The second storage method is off-chip storage, and the linked list corresponding to the target node is the second linked list; the node switching information of the second linked list includes a first switching identifier and a switching position offset, the first switching identifier is used to indicate whether to switch to on-chip storage, and the switching position offset is used to indicate the offset address of the data block for switching the storage method.

4. The method according to claim 3, characterized in that The queue information of the first linked list also includes a first node switching mark. When the first storage method is the same as the second storage method, the method also includes: if the data to be stored is the first data stored in the on-chip storage queue, updating the first node switching mark.

5. The method according to claim 2, characterized in that The second storage mode is on-chip storage, and the linked list corresponding to the target node is the first linked list; The updating of the node switching information of the target node in the linked list corresponding to the target node includes: updating the second switching identifier of the target node in the first linked list, or updating the third switching identifier in the queue information of the first linked list; wherein the second switching identifier is used to indicate that the next hop switches to the off-chip storage, and the third switching identifier is used to indicate whether the first node of the first linked list switches to the off-chip storage.

6. The method according to claim 2, characterized in that The queue information of the second linked list includes a data block storage offset. When the first storage mode is off-chip storage and the first storage mode is the same as the second storage mode, the method further includes: updating the data block storage offset.

7. A data reading method, characterized in that: The method is applied to a data processing device, wherein a first linked list for managing on-chip storage and a second linked list for managing off-chip storage are configured in the data processing device, wherein the first linked list and the second linked list include queue information and node switching information, wherein the queue information of the first linked list includes a read tag, wherein the read tag is used to indicate a data reading mode, wherein the reading mode includes on-chip reading and off-chip reading; and wherein the method includes: Determining a reading method of the data to be read according to the reading mark; In the case where the reading mode is off-chip reading, determining a target node according to the queue information of the second linked list; Obtain node switching information of the target node in the second linked list; The to-be-read data is read in the target node, wherein after it is determined according to the node switching information that all data stored in the off-chip cache has been read, the read mark is updated to a value indicating on-chip reading.

8. The method according to claim 7, characterized in that The queue information of the second linked list includes an off-chip node head pointer and a data block read offset, and determining the target node according to the queue information of the second linked list includes: The target node is determined according to the sum of the off-chip node head pointer and the data block read offset.

9. The method according to claim 7, characterized in that The queue information of the second linked list includes a data block read offset, and the node switching information includes a first switching identifier and a switching position offset, wherein the first switching identifier is used to indicate whether to switch to on-chip storage; The step of determining, according to the node switching information, that all data stored in the off-chip cache has been read, includes: When the first switching flag indicates switching to the on-chip storage and the data block read offset is equal to the switching position offset, it is determined that all data stored in the off-chip cache are read.

10. The method according to claim 7, characterized in that The update queue information of the first linked list includes a third switching flag, and the third switching flag is used to indicate whether the first node of the first linked list is switched to off-chip storage; After determining a reading method of the to-be-read data according to the reading mark, the method further includes: When the reading mode is on-chip reading, determining a target node according to the queue information of the first linked list; Acquire a second switching identifier of the target node from the first linked list, where the second switching identifier is used to indicate that the next hop is switched to an off-chip storage; The to-be-read data is read from the target node, and the third switching identifier and the reading mark are updated according to the second switching identifier of the target node.

11. A data processing device, comprising: one or more processors; a memory having one or more programs stored therein; When the one or more programs are executed by the one or more processors, the one or more processors implement the data processing method according to any one of claims 1 to 6, and / or the data reading method according to any one of claims 7 to 10; One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

12. A computer readable medium having a computer program stored thereon, wherein: When the program is executed, the data storage method according to any one of claims 1 to 6 is implemented, or the data reading method according to any one of claims 7 to 10 is implemented.

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