Method for verifying correctness of design rule check file
By verifying the method of checking files for design rules and using the program language for DRC verification, the problem of inaccurate definition of connectivity rules in manual creation of DRC files is solved, the accuracy and reliability of design rule checking is achieved, and the design risk is reduced.
Patent Information
- Application Number
- CN202411588857.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2025-02-18
AI Technical Summary
The DRC files manually created in the prior art cannot accurately define the connectivity rules of the device terminals, resulting in the layout design not meeting the manufacturing process requirements, increasing design problems and circuit performance risks.
Provides a method to verify the correctness of design rules, and uses a programming language to perform DRC verification, including short-circuit checks and circuit breakers, identify and output the electrical network identifier of each terminal, To determine the correctness of the connection relationship.
This method systematically verifies the correctness of the connectivity rules in the DRC file, significantly reduces design problems caused by connection relationship errors, improves the accuracy and reliability of the design, and reduces the resulting manual inspection and human operations risk.
Smart Images
Figure CN119476149A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of integrated circuit design and relates to a method for verifying the correctness of a design rule checking file. Background Art
[0002] In the field of integrated circuit design, Design Rule Check (DRC) is a key tool used to verify whether the integrated circuit layout complies with the manufacturing process rules. DRC identifies problems that may affect the manufacturing process or circuit performance by checking the design rules such as the geometry, interlayer distance, and device spacing in the layout, thereby ensuring the manufacturability and electrical performance of the integrated circuit. However, with the rapid increase in the complexity of integrated circuit design, the types and complexity of design rules have also increased. In addition, different process platforms have their own specific design rules, which requires designers to accurately and comprehensively define these rules when establishing DRC files to avoid layout design defects caused by incomplete or incorrect rule definitions.
[0003] At present, the establishment of DRC files mostly relies on manual operations, and designers need to manually define various design rules according to specific process platforms. This manual process of creating DRC files is not only labor-intensive and time-consuming, but also prone to errors, including incomplete or incorrect rule definitions. In particular, for the rules that define the connectivity of device terminals, due to their complexity, it is easier to increase the possibility and difficulty of human errors. In complex circuit design, it is very challenging to ensure that the connection rules for each terminal in the DRC file are accurate. If the terminal connectivity rules or device-to-device connectivity rules in the DRC file are not accurately defined, it may cause serious circuit performance problems and even cause some unforeseen problems, such as chip function failure or reduced reliability. In addition, with the continuous updating of process rules, DRC files also need to be frequently modified and maintained, which further increases the risk of errors. Moreover, for some complex electrical phenomena, such as latch-up, if the DRC file fails to correctly define the connection relationship between the internal terminals of the device, the relevant hidden dangers may not be discovered in time, thereby bringing manufacturing and performance risks.
[0004] Therefore, how to provide a method for verifying the correctness of the design rule check file, ensure the accurate definition of the connectivity relationship of the device terminals, and reduce the errors caused by human operation has become an important technical problem that needs to be solved urgently by technical personnel in this field.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0006] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a method for verifying the correctness of a design rule check file, so as to solve the problem that the manually created DRC file in the prior art cannot accurately define the connectivity rules of the device terminals, resulting in the layout design not meeting the manufacturing process requirements.
[0007] To achieve the above object and other related objects, the present invention provides a method for verifying the correctness of a design rule check file, comprising the following steps:
[0008] Providing a test layout, the test layout comprising a plurality of layers, the plurality of layers being arranged according to a preset design rule and leading out a plurality of terminals;
[0009] Providing a preset DRC file, wherein the preset DRC file includes a definition of electrical connectivity relationships between different terminals in the test layout;
[0010] A program language is provided, the program language is applied to the preset DRC file, and DRC verification is performed on the test layout, the DRC verification includes short circuit check and open circuit check on the test layout, wherein the program language identifies and outputs an electrical network identifier corresponding to each of the terminals in the test layout by parsing the connectivity rules in the preset DRC file;
[0011] Whether the connectivity relationship established in the preset DRC file is correct is determined according to the electrical network identifier.
[0012] Optionally, during the short circuit check process, each of the terminals in the test layout is set to a suspended state, and the electrical network identifier corresponding to each of the terminals is compared to verify whether the connectivity relationship established in the preset DRC file is correct.
[0013] Optionally, after the test layout is verified by DRC, if any two or more of the terminals have the same electrical network identifier and there is no actual electrical connection in the test layout, it is determined that the connectivity relationship established in the preset DRC file is wrong.
[0014] Optionally, after the test layout is verified by DRC, if any two or more of the terminals have the same electrical network identifier and there is actually an electrical connection in the test layout, it is determined that there is a short circuit in the test layout.
[0015] Optionally, the test layout is further provided with a top conductive layer for performing circuit breaking inspection, and each of the terminals is connected to the top conductive layer so that all the terminals are in the same electrical network.
[0016] Optionally, after the test layout is verified by DRC, if different electrical network identifiers exist in the terminals and there is actually an electrical connection in the test layout, it is determined that the connectivity relationship established in the preset DRC file is wrong.
[0017] Optionally, after the test layout is verified by DRC, if different electrical network identifiers exist in the terminals and there is no actual electrical connection in the test layout, it is determined that there is a break in the test layout.
[0018] Optionally, the plurality of layers are arranged into a plurality of semiconductor devices according to a preset design rule, and each of the semiconductor devices includes at least one terminal.
[0019] Optionally, the semiconductor device includes at least one of a transistor, a capacitor and a resistor.
[0020] Optionally, the programming language includes a scripting language or a hardware description language.
[0021] As described above, the method for verifying the correctness of the design rule check file provided by the present invention is simple and efficient. The method systematically verifies the correctness of the connectivity rules in the preset DRC file, significantly reduces the design problems caused by connectivity relationship errors in the DRC file, improves the accuracy of the design from the source, avoids layout design deviations caused by DRC file connectivity errors, and ensures the correctness and reliability of the DRC file itself. At the same time, the present invention adopts a multi-level, automated verification process, which greatly reduces the risks brought by manual inspection and human operation, significantly improves the verification efficiency and accuracy, enhances the application value of the DRC file in actual design, and ensures the high reliability and correctness of the final design. In addition, the present invention specifically verifies the terminal connectivity in the DRC file, greatly improving the accuracy of the terminal connection defined in the DRC file, especially in the layout design that needs to avoid triggering latch-up or the layout design of some complex circuit structures, reducing possible connectivity errors. At the same time, the verification of the design rule check file by the present invention can also effectively promote the collaboration and consistency check between different technology development departments, for example, ensuring the consistency of the device layout connectivity provided by the TD (Technology Development) department and the device layout connectivity completed by the Pcell (Parameterized Cell) department, ensuring that the DRC rules used by the designer are fully matched with the actual device layout, thereby improving the accuracy and reliability of the entire design process. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Shown is a flow chart of a method for verifying correctness of a design rule check file according to the present invention.
[0023] Figure 2 In a specific example of the method for verifying the correctness of a design rule check file of the present invention, a NetID result table is obtained after the test layout is subjected to DRC verification.
[0024] Figure 3 In a specific example of the method for verifying the correctness of a design rule check file of the present invention, a NetID result table is obtained after the test layout with the top conductive layer is verified by DRC.
[0025] Figure 4 In another specific example of the method for verifying the correctness of a design rule check file of the present invention, a NetID result table is obtained after DRC verification of the test layout having the top conductive layer. DETAILED DESCRIPTION
[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0027] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0028] This embodiment provides a method for verifying the correctness of a design rule check file. Figure 1 , shown as a flow chart of the method, comprising the following steps:
[0029] S1: providing a test layout, wherein the test layout includes a plurality of layers, wherein the plurality of layers are arranged according to a preset design rule and lead out a plurality of terminals;
[0030] S2: providing a preset DRC file, wherein the preset DRC file includes a definition of electrical connectivity relationships between different terminals in the test layout;
[0031] S3: providing a programming language, applying the programming language to the preset DRC file, and performing DRC verification on the test layout, wherein the DRC verification includes performing short circuit check and open circuit check on the test layout, wherein the programming language identifies and outputs an electrical network identifier corresponding to each of the terminals in the test layout by parsing the connectivity rules in the preset DRC file;
[0032] S4: Determine whether the connectivity relationship established in the preset DRC file is correct according to the electrical network identifier.
[0033] Combine the following Figures 1 to 4 The specific technical solution of the present invention for verifying the correctness of the design rule check file is described in detail.
[0034] First, step S1 is performed: providing a test layout, wherein the test layout includes a plurality of layers, and the plurality of layers are arranged according to a preset design rule and lead out a plurality of terminals.
[0035] As an example, a plurality of the layers are arranged into a plurality of semiconductor devices according to a preset design rule, and each of the semiconductor devices includes at least one terminal.
[0036] Specifically, the multiple layers in the test layout are arranged according to preset design rules, and each layer corresponds to a different process layer, such as a polysilicon layer, a metal layer, a contact hole layer, and a passivation layer. Each process layer provides specific functions according to a specific structural design to support the realization of different electrical characteristics and semiconductor device structures.
[0037] Specifically, the terminals of the semiconductor devices may be independent of each other or electrically connected in the same electrical network. For example, some terminals are isolated from each other and connected to different electrical nodes, corresponding to different electrical networks, while other terminals are connected to each other through interlayer conductive lines to form a common electrical network.
[0038] As an example, the semiconductor device includes at least one of a transistor, a capacitor, and a resistor.
[0039] As an example, the transistor includes at least one of a bipolar transistor and a field effect transistor.
[0040] Specifically, the terminals of the field effect transistor include a source, a drain and a gate, the terminals of the bipolar transistor include a base, a collector and an emitter, the terminals of the capacitor include two electrodes (a positive electrode and a negative electrode), and the resistor includes two connection terminals.
[0041] Specifically, the specific design of the test layout can be selected according to actual application requirements to simulate different layout designs, and is not limited to a single layout. For example, the test layout can be a BCD structure (i.e., bipolar transistor-complementary metal oxide semiconductor transistor-double diffused metal oxide semiconductor transistor) including multiple transistors or other structures that meet design requirements.
[0042] It should be noted that the test layout in this embodiment is created based on the actual semiconductor process flow and device connection requirements, and can simulate the complex electrical connections and physical layouts in the real layout, covering most connection situations and design scenarios. Importantly, the process flow and design rules of the test layout are consistent with those of the real layout, and the design rule check file of the test layout is also applicable to the real layout design.
[0043] Execute step S2: provide a preset DRC file, wherein the preset DRC file includes a definition of the electrical connectivity relationship between different terminals in the test layout.
[0044] As an example, the preset DRC file includes a definition of an electrical connectivity relationship between a plurality of the terminals of different semiconductor devices and / or a definition of an electrical connectivity relationship between a plurality of the terminals in a same semiconductor device.
[0045] Specifically, the preset DRC file checks whether the connection of the multiple terminals in the test layout complies with the design rules by defining the electrical connectivity relationship between the multiple terminals of different semiconductor devices and the electrical connectivity relationship between different terminals of the same semiconductor device. For example, the preset DRC file may stipulate that a certain terminal A must be connected to a certain terminal B through a specific metal layer, and cannot be electrically connected across other layers; or stipulate that a certain terminal needs to be electrically connected to other terminals through a contact hole or a specific multi-layer structure layer. In addition, the preset DRC file may also include a limit on the spacing between the multiple terminals to avoid the problem of increased wiring complexity and decreased electrical characteristics (such as signal transmission delay, increased parasitic capacitance, etc.) due to the large spacing between the multiple terminals, and the problem of electrical interference or short circuit due to the small spacing between the multiple terminals.
[0046] Execute step S3: provide a programming language, apply the programming language to the preset DRC file, and perform DRC verification on the test layout, wherein the DRC verification includes performing short circuit check and open circuit check on the test layout, wherein the programming language identifies and outputs an electrical network identifier (Network Identifier, NetID) corresponding to each terminal in the test layout by parsing the connectivity rules in the preset DRC file.
[0047] Specifically, in this embodiment, the program language can parse the connectivity rule information between each terminal and other terminals defined in the preset DRC file, or the rule information of electrical connection with other electrical networks. In the process of DRC verification of the test layout, the set program language is added to the preset DRC file to output the NetID corresponding to each terminal, so as to obtain the electrical network to which each terminal belongs. In addition, by analyzing these NetIDs, the electrical connection relationship between multiple terminals in the test layout can be determined.
[0048] It should be noted that, in this embodiment, the DRC verification includes a scheme of performing short circuit and open circuit checks on the test layout, which does not simply refer to performing short circuit and open circuit checks on the test layout, but refers to evaluating the correctness of the connectivity relationship defined in the preset DRC file by a specific method. The purpose of this method is to verify the connectivity rules specified in the preset DRC file, not just to check whether there are short circuits and open circuits in the test layout.
[0049] As an example, the program language includes a scripting language (such as Python, TCL, etc.), a hardware description language (such as Verilog, VHDL) or other suitable program languages. In this embodiment, the program language is preferably a scripting language.
[0050] Execute step S4: determine whether the connectivity relationship established in the preset DRC file is correct according to the electrical network identifier.
[0051] As an example, during the short circuit check process, each of the terminals in the test layout is set to a suspended state, and the electrical network identifier corresponding to each of the terminals is compared to verify whether the connectivity relationship established in the preset DRC file is correct.
[0052] As an example, after the test layout is verified by DRC, if any two or more of the terminals have the same electrical network identifier and there is no actual electrical connection in the test layout, it is determined that the connectivity relationship established in the preset DRC file is wrong.
[0053] As an example, after the test layout is verified by DRC, if any two or more of the terminals have the same electrical network identifier and there is actually an electrical connection in the test layout, it is determined that there is a short circuit in the test layout.
[0054] Specifically, in this embodiment, setting each of the terminals to a suspended state means setting each of the terminals to an electrically isolated state without forming an electrical connection with other terminals or electrical components. In this case, each of the terminals has an independent NetID. By comparing the NetID of each of the terminals, it can be verified whether the connectivity relationship established in the preset DRC file is correct.
[0055] Specifically, if the test layout is verified by DRC and any two or more of the terminals have the same NetID, it indicates that one of the following two situations may exist:
[0056] (1) The test layout is constructed incorrectly, resulting in any two or more terminals that should be electrically isolated being incorrectly connected together.
[0057] (2) The connectivity relationship established in the preset DRC file is incorrect, resulting in the DRC check failing to correctly identify the electrical isolation status between the terminals.
[0058] Specifically, in the present embodiment, whether the terminals with the same NetID are actually electrically connected can be determined by manual inspection. If the above two or more terminals with the same NetID are actually not electrically connected in the test layout, it indicates that the connectivity relationship of the terminals established in the preset DRC file is wrong, resulting in the DRC check being unable to correctly identify. For example, the preset DRC file mistakenly defines the mutually independent terminals as being in a connected state, causing any two or more terminals that should be electrically isolated to be identified as being in the same electrical network. If any two or more of the terminals with the same NetID are actually electrically connected in the test layout, it indicates that the constructed test layout is wrong and there is a risk of short circuit. For example, due to errors in the design of the conductive path and other reasons, any two or more terminals are incorrectly connected, resulting in the risk of short circuit.
[0059] Furthermore, for the test layout with short circuit risk, it is also possible to confirm whether the actual electrical connection mode in the test layout meets the requirements of the real layout. If such connection is acceptable, the setting of the connectivity relationship of the terminals in the preset DRC file can be adjusted according to the actual situation. If such connection is unacceptable, the test layout needs to be modified to ensure that it meets the design requirements.
[0060] like Figure 2 As shown in FIG. 1 , a result table of NetID obtained after DRC verification of the test layout is shown in a specific example. Figure 2 As shown, the multiple terminals are divided by ID, for example, the ID of terminal T1 is 1, the ID of terminal T2 is 2, and so on. In addition, each terminal has a corresponding NetID, represented by the numbers "1, 2, 3...". Figure 2 There are four types of NetIDs corresponding to the plurality of terminals, wherein the terminals T2, T3 and T5 share the same NetID, and the terminals T6 and T7 also share another same NetID.
[0061] In this embodiment, by manually checking the test layout, it can be determined whether there is actually an electrical connection between the terminals with the same NetID (such as the group of T2, T3 and T5 or the group of T6 and T7). If the inspection finds that the terminals with the same NetID are not actually electrically connected in the test layout, it means that the setting of the terminal connectivity relationship in the preset DRC file is incorrect and needs to be corrected. On the contrary, if these terminals with the same NetID are indeed electrically connected in the test layout, it means that there is a problem in the construction of the test layout and there is a risk of short circuit.
[0062] As an example, the test layout is further provided with a top conductive layer for performing a circuit breakage check, and each of the terminals is connected to the top conductive layer so that all the terminals are in the same electrical network.
[0063] As an example, the terminal is connected to the top conductive layer in a manner including a direct connection or an indirect connection.
[0064] Specifically, in this embodiment, the method in which the terminal is directly connected to the top-layer conductive layer means that the layer where the terminal is located is in direct physical contact with the layer where the top-layer conductive layer is located to achieve electrical connection; and the method in which the terminal is indirectly connected to the top-layer conductive layer means that the terminal is electrically connected to the top-layer conductive layer through an interlayer connection method (such as an interlayer conductive line or a conductive through-hole, etc.).
[0065] Specifically, in this embodiment, each of the terminals is connected to the top conductive layer, that is, each of the terminals in the test layout should have the same NetID after DRC verification. If there are different NetIDs, it means that the connectivity relationship between the multiple terminals established in the preset DRC file is wrong or the constructed test layout is wrong.
[0066] As an example, after the test layout is verified by DRC, if different electrical network identifiers exist in the terminals and there is no actual electrical connection in the test layout, it is determined that there is a break in the test layout.
[0067] Specifically, when the terminals with different NetIDs have no actual electrical connection in the test layout, that is, when the terminals with different NetIDs are independent of each other in the test layout, it indicates that the constructed test layout has a risk of open circuit. For example, in the test layout, although two terminals (such as terminal A and terminal B) are connected to the top conductive layer, if some conductive paths (such as conductive through holes, conductive lines, etc.) are missing, no effective electrical connection is formed between the two. That is, electrically, terminal A and terminal B are still independent of each other. Then, the DRC verification result will determine that terminal A and terminal B do not belong to the same electrical network. The existence of these conductive paths further indicates that there is a risk of open circuit in the test layout.
[0068] As an example, after the test layout is verified by DRC, if different electrical network identifiers exist in the terminals and there is actually an electrical connection in the test layout, it is determined that the connectivity relationship established in the preset DRC file is wrong.
[0069] Specifically, when the terminals with different NetIDs are actually electrically connected on the test layout, that is, when the terminals with different NetIDs are connected through valid conductive paths in the test layout, it indicates that the connectivity relationship between the terminals defined in the preset DRC file is wrong and needs to be further corrected. For example, in the test layout, two terminals (such as terminal A and terminal B) are connected to the top conductive layer, wherein terminal A is directly connected to the top conductive layer, and terminal B is indirectly connected to the top conductive layer through a conductive via, so that the terminal A and the terminal B are in the same electrical network. However, if the definition of the terminal B and the conductive via in the preset DRC file is incomplete or inaccurate, the actually connected terminal A and the terminal B will be regarded as different electrical networks during DRC verification, so that the terminal A and the terminal B correspond to different NetIDs respectively.
[0070] In addition, in this embodiment, a manual determination method may be used to determine whether the terminals with different NetIDs are actually in an electrical connection relationship in the test layout.
[0071] like Figure 3 As shown in FIG. 1 , a result table of NetID obtained after DRC verification of the test layout with the top conductive layer is shown in a specific example. Figure 3 In the embodiment, the plurality of terminals correspond to the same NetID, that is, each of the terminals is connected to the same electrical network.
[0072] like Figure 4 As shown, in another specific example, a NetID result table of the test layout with the top conductive layer is obtained after DRC verification. Figure 4 In the test layout, there are two kinds of NetIDs corresponding to the multiple terminals, wherein the multiple terminals T1, T2, T3, T4, T5, T6, T7, T8 and T9 share the same NetID, while the terminal T10 has another NetID. By further checking the test layout, the actual electrical connection relationship of the terminal (T10) with different NetIDs in the test layout can be determined. If it is found that in the test layout, the terminal T10 is actually electrically connected to any one of the other terminals T1, T2, T3, T4, T5, T6, T7, T8 and T9, it indicates that the connectivity relationship of the terminals established in the preset DRC file is wrong and needs to be further corrected. On the contrary, if it is found that in the test layout, the terminal T10 is actually not electrically connected to any one of the other terminals T1, T2, T3, T4, T5, T6, T7, T8 and T9, it indicates that the constructed test layout has a risk of short circuit.
[0073] As an example, the programming language can automatically update the electrical network identifier to reflect design changes.
[0074] In summary, the present invention provides a method for verifying the correctness of a design rule check file, comprising the following steps: providing a test layout, the test layout comprising a plurality of layers, the plurality of layers being arranged according to preset design rules and leading out a plurality of terminals; providing a preset DRC file, the preset DRC file comprising a definition of the electrical connectivity relationship of different terminals in the test layout; providing a program language, applying the program language to the preset DRC file, and performing DRC verification on the test layout, the DRC verification comprising performing a short circuit check and an open circuit check on the test layout, wherein the program language identifies and outputs an electrical network identifier corresponding to each terminal in the test layout by parsing the connectivity rules in the preset DRC file; and determining whether the connectivity relationship established in the preset DRC file is correct based on the electrical network identifier. The method for verifying the correctness of a design rule check file provided by the present invention is simple and efficient. This method systematically verifies the correctness of the connectivity rules in the preset DRC file, significantly reduces the design problems caused by connectivity relationship errors in the DRC file, improves the accuracy of the design from the source, avoids layout design deviations caused by connectivity errors in the DRC file, and ensures the correctness and reliability of the DRC file itself. At the same time, the present invention adopts a multi-level, automated verification process, which greatly reduces the risks brought by manual inspection and human operation, significantly improves the verification efficiency and accuracy, enhances the application value of the DRC file in actual design, and ensures the high reliability and correctness of the final design. In addition, the present invention specifically verifies the terminal connectivity in the DRC file, greatly improving the accuracy of the terminal connection defined in the DRC file, especially in the layout design that needs to avoid triggering latch-up or the layout design of some complex circuit structures, reducing possible connectivity errors. At the same time, the verification of the design rule check file by the present invention can also effectively promote the collaboration and consistency check between different technology development departments, for example, ensuring that the device layout provided by the TD (Technology Development) department is consistent with the device layout connectivity completed by the Pcell (Parameterized Cell) department, ensuring that the DRC rules used by the designer are fully matched with the actual device layout, thereby improving the accuracy and reliability of the entire design process. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0075] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for verifying the correctness of a design rule check file, characterized in that: The following steps are involved: Providing a test layout, the test layout comprising a plurality of layers, the plurality of layers being arranged according to a preset design rule and leading out a plurality of terminals; Providing a preset DRC file, wherein the preset DRC file includes a definition of electrical connectivity relationships between different terminals in the test layout; A program language is provided, the program language is applied to the preset DRC file, and DRC verification is performed on the test layout, the DRC verification includes short circuit check and open circuit check on the test layout, wherein the program language identifies and outputs an electrical network identifier corresponding to each of the terminals in the test layout by parsing the connectivity rules in the preset DRC file; Whether the connectivity relationship established in the preset DRC file is correct is determined according to the electrical network identifier.
2. The method for verifying the correctness of a design rule check file according to claim 1, characterized in that: During the short circuit check, each of the terminals in the test layout is set to a suspended state, and the electrical network identifier corresponding to each of the terminals is compared to verify whether the connectivity relationship established in the preset DRC file is correct.
3. The method for verifying the correctness of a design rule check file according to claim 2, characterized in that: After the test layout is verified by DRC, if any two or more of the terminals have the same electrical network identifier and there is no actual electrical connection in the test layout, it is determined that the connectivity relationship established in the preset DRC file is wrong.
4. The method for verifying the correctness of a design rule check file according to claim 2, characterized in that: After the test layout is verified by DRC, if any two or more of the terminals have the same electrical network identifier and there is actually an electrical connection in the test layout, it is determined that a short circuit exists in the test layout.
5. The method for verifying the correctness of a design rule check file according to claim 1, characterized in that: The test layout is also provided with a top conductive layer for performing circuit breakage inspection, and each of the terminals is connected to the top conductive layer so that all the terminals are in the same electrical network.
6. The method for verifying the correctness of a design rule check file according to claim 5, characterized in that: After the test layout is verified by DRC, if different electrical network identifiers exist in the terminals and electrical connections actually exist in the test layout, it is determined that the connectivity relationship established in the preset DRC file is wrong.
7. The method for verifying the correctness of a design rule check file according to claim 5, characterized in that: After the test layout is verified by DRC, if different electrical network identifiers exist in the terminals and there is no actual electrical connection in the test layout, it is determined that there is a break in the test layout.
8. The method for verifying the correctness of a design rule check file according to claim 1, characterized in that: The plurality of layers are arranged into a plurality of semiconductor devices according to a preset design rule, and each of the semiconductor devices includes at least one terminal.
9. The method for verifying the correctness of a design rule check file according to claim 8, characterized in that: The semiconductor device includes at least one of a transistor, a capacitor and a resistor.
10. The method for verifying the correctness of a design rule check file according to claim 1, characterized in that: The program language includes a scripting language or a hardware description language.