Configuration method and providing method of electrostatic discharge protection grade adjustable IO IP core, device and chip

Abstract

The invention relates to the technical field of chip IP (Internet Protocol) cores and EDA (Electronic Design Automation), in particular to a configuration method and a providing method of an IOIP (Input / Output Intellectual Property) core with an adjustable electrostatic discharge protection grade, a device and a chip. An IO IP core provided by an existing process factory or an IP manufacturer is generally an integral module, only can provide electrostatic discharge protection capability of limited gears, and cannot be conveniently changed according to chip requirements. A special EDA tool is researched and developed, meanwhile, the circuit module and the layout of the IO IP core are subjected to customized design, and the configurable IO IP core comprising the IO core circuit module and the electrostatic discharge protection level adjustable module is reconstructed, so that user requirements are obtained through the customized EDA tool, and the modules in the configurable IO IP core are configured; and the flexible configuration according to the actual chip complex application is realized.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip IP core and EDA (Electronic Design Automation), and in particular to a configuration method and providing method, device and chip of an IO IP core with adjustable electrostatic discharge protection level. Background Art

[0002] The annual market demand for chips in my country's key industrial fields such as electricity, rail transit, and automobiles is as high as 100 billion yuan. Unlike general-purpose consumer chips, industrial chips are mostly mounted outdoors with terminals and are easily subject to strong transient electromagnetic interference generated by the operation of surrounding power devices such as IGBTs (Insulated Gate Bipolar Transistors), and may also be affected by environmental factors such as high temperature and high humidity.

[0003] Therefore, industrial chips need to achieve 7*24 hours of stable operation in high / low temperature, high humidity, strong electromagnetic and other environments, and their lifespan needs to reach more than 15 years. This poses a huge challenge to the reliability of chip pins that are susceptible to environmental interference. The ESD (Electro-Static discharge) protection capability of the input / output (I / O) pins of industrial chips is an important indicator for their resistance to external environmental interference.

[0004] As the division of labor in chips becomes more and more detailed, the IO IP core has become one of the standard IPs provided by chip process manufacturers. The IO IP core design is a very important part of chip design, directly connecting the chip's internal core circuit, external packaging, and printed circuit board (PCB) and other external environments.

[0005] Most of the IO IP cores currently provided by mainstream process factories can only resist 2kV electrostatic discharge. However, in industrial chips, many chips such as power drivers need to resist 4kV and 5kV electrostatic discharge, and some interface chips even need to resist electrostatic discharge above 10kV. Therefore, the electrostatic discharge protection capabilities provided by the current process factory-specific IO IP cores cannot meet the chip design requirements for complex industrial application scenarios such as electromagnetic heat and electricity. Summary of the invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide a configuration method of an IOIP core with an adjustable electrostatic discharge protection level and a providing method, device and chip.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for configuring an IO IP core with an adjustable electrostatic discharge protection level, the method being implemented based on a customized EDA tool, and the method comprising:

[0008] Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module and an electrostatic release protection level adjustable module, wherein the electrostatic release protection level adjustable module includes a plurality of unit electrostatic release protection modules, and wherein the unit electrostatic release protection module includes a plurality of MOS modules;

[0009] Get the electrostatic discharge protection level entered by the user for the specified pin module of the custom IO IP core;

[0010] According to the electrostatic discharge protection level, configuring the electrostatic discharge protection level adjustable module includes: according to the electrostatic discharge protection level, selecting one or more unit electrostatic discharge protection modules from the multiple unit electrostatic discharge protection modules and connecting the selected one or more unit electrostatic discharge protection modules to generate a configured electrostatic discharge protection level adjustable module, wherein the configured electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level;

[0011] Connecting the IO core circuit module and the configured electrostatic discharge protection module to generate a designated pin module of the customized IOIP core, wherein the IO core circuit module includes a power supply voltage port, a ground port, an IO input signal port, and a control signal output port; the selected unit electrostatic discharge protection module includes a power supply voltage port, a ground port, and a control signal input port;

[0012] The power supply voltage ports of the IO core circuit module and the selected unit electrostatic discharge protection module are both connected to the power supply voltage, and the grounding ports are both grounded;

[0013] The control signal output port of the IO core circuit module is connected to the control signal input port of the selected unit electrostatic discharge protection module, and is used to output a control signal to the selected unit electrostatic discharge protection module based on the IO input signal;

[0014] In the selected unit electrostatic release protection module, the MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute a unit electrostatic release protection capability.

[0015] According to an embodiment of the present disclosure, it also includes:

[0016] Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

[0017] According to an embodiment of the present disclosure, the MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and provides an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute a unit electrostatic release protection capability, including:

[0018] All MOS modules in the selected unit electrostatic discharge protection module are connected to the control signal input port of the selected unit electrostatic discharge protection module, and all connected MOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time;

[0019] Alternatively, some MOS modules in the selected unit electrostatic release protection module are connected to the control signal input port of the selected unit electrostatic release protection module, and the connected part of the MOS modules simultaneously provide part of the unit electrostatic release protection capability and the corresponding output current capability, and the remaining MOS modules provide the remaining unit electrostatic release protection capability;

[0020] Alternatively, all MOS modules in the selected unit electrostatic release protection module are disconnected from the control signal input port of the selected unit electrostatic release protection module, and all disconnected MOS modules provide unit electrostatic release protection capability.

[0021] According to an embodiment of the present disclosure, when some MOS modules in the selected unit electrostatic release protection module are connected to the control signal input port of the selected unit electrostatic release protection module, among the remaining MOS modules in the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port;

[0022] When all MOS modules in the selected unit electrostatic release protection module are disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0023] According to an embodiment of the present disclosure, the gates of a part of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the MOS modules are grounded through the ground port, including:

[0024] The gate and source of a part of MOS modules are short-circuited and then connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of MOS modules are short-circuited and then grounded through the ground port.

[0025] According to an embodiment of the present disclosure, when some MOS modules in the selected unit electrostatic release protection module are connected to the control signal input port of the selected unit electrostatic release protection module, in the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistor module and the grounding port;

[0026] When all MOS modules in the selected unit electrostatic release protection module are disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistance module and the grounding port.

[0027] According to an embodiment of the present disclosure, the gates of a part of the MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of another part of the MOS modules are grounded through the resistor module and the ground port, including:

[0028] The gate and source of a part of MOS modules are short-circuited and then connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of MOS modules are short-circuited and then grounded through the resistor module and the grounding port.

[0029] According to an embodiment of the present disclosure, the method further includes: acquiring a bottom module, and using the bottom module to seal the bottom of the designated pin module of the customized IO IP core to generate a designated pin module with a sealed bottom.

[0030] According to an embodiment of the present disclosure, the method further includes:

[0031] Based on the bottom-enclosed designated pin module, a second designated pin circuit layout of the customized IO IP core is generated.

[0032] According to an embodiment of the present disclosure, the method further includes:

[0033] Acquire at least one filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module being connected to a power supply voltage, and the ground port of the filling module being grounded;

[0034] Generate multiple pin modules of the customized IO IP core;

[0035] Splicing the plurality of pin modules to obtain a spliced ​​pin module;

[0036] The at least one filling module is used to fill the empty space in the splicing tube foot module to obtain a filled splicing tube foot module.

[0037] According to an embodiment of the present disclosure, the method further includes:

[0038] Based on the filled spliced ​​pin module, a multi-pin circuit layout of the customized IO IP core is generated.

[0039] According to an embodiment of the present disclosure, the customized EDA tool is used to provide an expected electrostatic discharge protection level input box to obtain the electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core.

[0040] According to an embodiment of the present disclosure, when a corresponding plurality of module layouts are generated based on the IO core circuit module and the configured electrostatic discharge protection module, the widths of the plurality of module layouts are consistent.

[0041] In a second aspect, the present disclosure provides a method for providing a configurable IO IP core, comprising:

[0042] Providing an IO core circuit module, the IO core circuit module includes an IO input signal port, a control signal output port, a power supply voltage port and a ground port, and is used to process the received IO input signal and output a control signal;

[0043] An electrostatic release protection level adjustable module is provided, wherein the electrostatic release protection level adjustable module includes multiple unit electrostatic release protection modules, each unit electrostatic release protection module includes: multiple MOS modules, a control signal input port, a power supply voltage port and a ground port, and a customized EDA tool selects one or more unit electrostatic release protection modules from the multiple unit electrostatic release protection modules according to the electrostatic release protection level and connects the selected one or unit electrostatic release protection modules to provide an electrostatic release protection capability corresponding to the electrostatic release protection level.

[0044] According to an embodiment of the present disclosure, when some or all MOS modules in a selected unit electrostatic discharge protection module are selected by a custom EDA tool to be connected to a control signal input port of the selected unit electrostatic discharge protection module, the connected part or all MOS modules simultaneously provide corresponding electrostatic discharge protection capability and output current capability;

[0045] When some or all MOS modules in the selected unit ESD protection module are not selected by the custom EDA tool to be disconnected from the control signal input port of the selected unit ESD protection module, the disconnected some or all MOS modules provide corresponding ESD protection capabilities.

[0046] According to an embodiment of the present disclosure:

[0047] When some MOS modules in the selected unit electrostatic release protection module are selected by the custom EDA tool to be connected to the control signal input port of the selected unit electrostatic release protection module, among the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port;

[0048] When all MOS modules in a selected unit electrostatic release protection module are not selected by the customized EDA tool to be disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of a part of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the MOS modules are grounded through the ground port.

[0049] According to an embodiment of the present disclosure:

[0050] When some MOS modules in the selected unit electrostatic release protection module are selected by the custom EDA tool to be connected to the control signal input port of the selected unit electrostatic release protection module, among the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistor module and the ground port;

[0051] When all MOS modules in a selected unit electrostatic release protection module are not selected by the customized EDA tool to be disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of a part of the MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of another part of the MOS modules are grounded through the resistance module and the ground port.

[0052] According to an embodiment of the present disclosure, it also includes: providing a filling module, the filling module including: a power supply voltage port and a ground port, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

[0053] According to an embodiment of the present disclosure, it further includes: providing a bottom module, wherein the bottom module is used to seal the bottom of one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0054] In a third aspect, an embodiment of the present disclosure provides a configuration device for an IO IP core with an adjustable electrostatic discharge protection level, the device being implemented based on a customized EDA tool, and the device comprising:

[0055] A first acquisition module is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module and an electrostatic discharge protection level adjustable module, wherein the electrostatic discharge protection level adjustable module includes a plurality of unit electrostatic discharge protection modules, and wherein the unit electrostatic discharge protection module includes a plurality of MOS modules;

[0056] A second acquisition module is configured to acquire an electrostatic discharge protection level input by a user for a designated pin module of a customized IO IP core;

[0057] The electrostatic discharge protection configuration module is configured to configure the electrostatic discharge protection level adjustable module according to the electrostatic discharge protection level, including: selecting one or more unit electrostatic discharge protection modules from the plurality of unit electrostatic discharge protection modules according to the electrostatic discharge protection level and connecting the selected one or more unit electrostatic discharge protection modules to generate a configured electrostatic discharge protection level adjustable module, wherein the configured electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level;

[0058] A generating module is configured to connect the IO core circuit module and the configured electrostatic discharge protection module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes a power supply voltage port, a ground port, an IO input signal port, and a control signal output port; and the selected unit electrostatic discharge protection module includes a power supply voltage port, a ground port, and a control signal input port;

[0059] The power supply voltage ports of the IO core circuit module and the selected unit electrostatic discharge protection module are both connected to the power supply voltage, and the grounding ports are both grounded;

[0060] The control signal output port of the IO core circuit module is connected to the control signal input port of the selected unit electrostatic discharge protection module, and is used to output a control signal to the selected unit electrostatic discharge protection module based on the IO input signal;

[0061] In the selected unit electrostatic release protection module, the MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute a unit electrostatic release protection capability.

[0062] According to an embodiment of the present disclosure, it further includes: a third acquisition module configured to acquire a bottom module, wherein the bottom module is used to close the bottom of the designated pin module of the custom IO IP core to generate a designated pin module with a closed bottom.

[0063] According to an embodiment of the present disclosure, it also includes: a fourth acquisition module, configured to acquire at least one filling module, the filling module including: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the customized IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the customized IOIP core.

[0064] In a fourth aspect, an embodiment of the present disclosure provides a device for providing a configurable IO IP core, including:

[0065] A first providing module is configured to provide an IO core circuit module, wherein the IO core circuit module includes an IO input signal port, a control signal output port, a power supply voltage port and a ground port, and is used to process the received IO input signal and output a control signal;

[0066] The second providing module is configured to provide an electrostatic release protection level adjustable module, the electrostatic release protection level adjustable module includes multiple unit electrostatic release protection modules, each unit electrostatic release protection module includes: multiple MOS modules, control signal input ports, power supply voltage ports and ground ports, the customized EDA tool selects one or more unit electrostatic release protection modules from the multiple unit electrostatic release protection modules according to the electrostatic release protection level and connects the selected one or unit electrostatic release protection modules to provide an electrostatic release protection capability corresponding to the electrostatic release protection level.

[0067] According to an embodiment of the present disclosure, it also includes:

[0068] A third providing module is configured to provide a filling module, wherein the filling module includes: a power supply voltage port and a ground port, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

[0069] According to an embodiment of the present disclosure, it also includes:

[0070] The fourth providing module is configured to provide a bottom module, wherein the bottom module is used to seal the bottom of one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0071] In a fifth aspect, an embodiment of the present disclosure provides a chip, comprising: a custom IO IP core manufactured using the method generated according to any one of the methods described in the first aspect, or a custom IO IP core manufactured using the configurable IO IP core provided by the method described in the second aspect.

[0072] In a sixth aspect, an embodiment of the present disclosure provides an electronic device, comprising the chip as described in the fifth aspect.

[0073] In a seventh aspect, an embodiment of the present disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any one of the first aspect or the second aspect.

[0074] In an eighth aspect, an embodiment of the present disclosure provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the method as described in any one of the first aspect or the second aspect.

[0075] According to the technical solution provided by the embodiment of the present disclosure, a user requirement (the electrostatic discharge protection level input for the designated pin module of the customized IO IP core) is obtained by using a customized EDA tool, and a configurable IO IP core including multiple unit electrostatic discharge protection modules is configured, one or more unit electrostatic discharge protection modules are selected from the multiple unit electrostatic discharge protection modules and connected to generate a configured electrostatic discharge protection level adjustable module; the IO core circuit module and the configured electrostatic discharge protection level adjustable module are connected to generate a designated pin module of the customized IO IP core.

[0076] The present invention discloses the development of a special customized EDA tool, and at the same time customizes the circuit module and layout of the IO IP core, and reconstructs it into a configurable IO IP core including an IO core circuit module and an ESD protection level adjustable module, which can be adjusted according to the needs of the actual chip to achieve flexible configuration of the ESD protection capability, and meet the ESD protection capability of each pin required by the actual chip, so that the customized IO IP core generated by the customized EDA tool and the configurable IO IP core can meet the design requirements of complex industrial chips with different ESD protection capabilities.

[0077] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0079] Figure 1 A flowchart showing a configuration method of an IO IP core with adjustable electrostatic discharge protection level according to an embodiment of the present disclosure is shown;

[0080] Figure 2 A schematic diagram showing a unit electrostatic discharge protection module according to an embodiment of the present disclosure;

[0081] Figure 3 A schematic diagram showing another unit electrostatic discharge protection module according to an embodiment of the present disclosure;

[0082] Figure 4 A schematic diagram showing another unit electrostatic discharge protection module according to an embodiment of the present disclosure;

[0083] Figure 5 Shown in Figure 3 or Figure 4 A schematic diagram of a connection relationship between a PMOS tube and an NMOS tube corresponding to a MOS module disconnected from a control signal input port in the example shown;

[0084] Figure 6 Shown in Figure 3 or Figure 4 In the example shown, a schematic diagram of another connection relationship between a PMOS tube and an NMOS tube corresponding to the MOS module disconnected from the control signal input port is shown;

[0085] Figure 7 A schematic diagram showing the connection between the IO core circuit module and the configured electrostatic discharge protection level adjustable module in the configuration method of the IO IP core with an adjustable electrostatic discharge protection level according to an embodiment of the present disclosure;

[0086] Figure 8 A schematic diagram showing splicing of pin modules in a configuration method of an IO IP core with adjustable electrostatic discharge protection level according to an embodiment of the present disclosure;

[0087] Fig. 9 A flowchart showing a method for providing a configurable IO IP core according to an embodiment of the present disclosure is shown;

[0088] Fig.10 A schematic diagram showing a configuration device of an IO IP core with adjustable electrostatic discharge protection level according to an embodiment of the present disclosure;

[0089] Fig.11 A schematic diagram showing an apparatus for providing a configurable IO IP core according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0090] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0091] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0092] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0093] In the present disclosure, if it involves operations of obtaining user information or user data or displaying user information or user data to others, the operations are all authorized and confirmed by the user, or actively selected by the user.

[0094] As mentioned above, most of the IO IP cores provided by the current mainstream process plants or IP manufacturers can only provide fixed electrostatic discharge protection capabilities (for example, they can only resist 2kV electrostatic discharge). As a result, the electrostatic discharge protection capabilities provided by the IO IP cores manufactured by the current process plants or IP manufacturers cannot meet the design requirements of chip designs in complex industrial application scenarios such as electromagnetic heating, industrial control, aerospace, etc.

[0095] After research, the inventors found that the reason why the existing IO IP core can only provide a single electrostatic discharge protection capability is that the IO IP core is designed as an integral module, integrating multiple functions such as signal reception and transmission and providing electrostatic discharge protection capability. As an integral module, the IO IP core cannot be easily changed according to chip requirements, resulting in the existing IO IP core only being able to provide a fixed electrostatic discharge protection capability, which brings a lot of inconvenience to chip design in complex industrial application scenarios and increases the difficulty of chip design.

[0096] The present disclosure provides a method for configuring an IO IP core with an adjustable electrostatic discharge protection level, the method being implemented based on a customized EDA tool, the method comprising:

[0097] A configurable IO IP core is obtained, wherein the configurable IO IP core includes an IO core circuit module and an ESD protection level adjustable module, wherein the ESD protection level adjustable module includes multiple unit ESD protection modules, wherein the unit ESD protection module includes multiple MOS modules; an ESD protection level input by a user for a designated pin module of a customized IO IP core is obtained; and according to the ESD protection level, the ESD protection level adjustable module is configured, including: according to the ESD protection level, selecting one or more unit ESD protection modules from the multiple unit ESD protection modules and connecting the selected one or more unit ESD protection modules to generate a configured ESD protection level adjustable module, wherein the configured ESD protection level adjustable module is used to provide a designated ESD protection capability corresponding to the ESD protection level; and connecting the IO core circuit module and the configured ESD protection module to generate a designated pin module of the customized IO IP core.

[0098] Wherein, the IO core circuit module includes a power supply voltage port, a ground port, an IO input signal port and a control signal output port; the selected unit electrostatic discharge protection module includes a power supply voltage port, a ground port and a control signal input port;

[0099] The power supply voltage ports of the IO core circuit module and the selected unit electrostatic release protection module are both connected to the power supply voltage, and the ground ports are both grounded; the control signal output port of the IO core circuit module is connected to the control signal input port of the selected unit electrostatic release protection module, and is used to output a control signal to the selected unit electrostatic release protection module based on the IO input signal; in the selected unit electrostatic release protection module, the MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the unit electrostatic release protection capability.

[0100] The present disclosure splits the overall module of the existing IO IP core into multiple modules (IO core circuit module, multiple unit electrostatic discharge protection modules) to obtain a configurable IO IP core. At the same time, since the existing EDA tools configure the IO IP core as a whole module, it is impossible to use the existing EDA tools to configure the configurable IO IP core of multiple modules obtained after the splitting. Therefore, the present disclosure develops a special EDA tool, and at the same time customizes the circuit module and layout of the IO IP core to reconstruct it into a configurable IO IP core including an IO core circuit module and multiple unit electrostatic discharge protection modules, so as to configure the configurable IO IP core using the obtained customized EDA tool, and adjust the electrostatic discharge protection level requirements input from the customized EDA tool according to the needs of the actual chip, so as to realize flexible and configurable electrostatic discharge protection capability, so that the customized IO IP core generated by the customized EDA tool and the configurable IO IP core can meet the design requirements of complex industrial chips with different electrostatic discharge protection levels.

[0101] Figure 1 FIG. 1 is a flow chart showing a configuration method of an IO IP core with adjustable electrostatic discharge protection level according to an embodiment of the present disclosure. Figure 1 As shown, the method is implemented based on a customized EDA tool, and the method includes the following steps S101 to S104:

[0102] In the present disclosure, since the configurable IO IP core is obtained by splitting and reconstructing the existing IO IP core, it cannot be directly configured using existing EDA tools. Therefore, it is necessary to configure the IO IP core based on a customized EDA tool to implement the following steps S101 to S104.

[0103] According to an embodiment of the present disclosure, the customized EDA tool is used to provide an expected electrostatic discharge protection level input box to obtain the electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core.

[0104] Specifically, an "expected electrostatic release protection level" input box is provided on the GUI (graphical user interface) interface of the customized EDA tool, and the user enters the electrostatic release protection level expected to be achieved for the specified pin module of the customized IO IP core from the input box. The expected electrostatic release protection level corresponds to the specified electrostatic release protection capability, wherein the expected electrostatic release protection level is divided into levels based on the unit electrostatic release protection capability. For example, assuming that the unit electrostatic release protection capability is 1kV, the electrostatic release protection capability corresponding to the first-level electrostatic release protection level is 1kV, the electrostatic release protection capability corresponding to the second-level electrostatic release protection level is 2kV, the electrostatic release protection capability corresponding to the third-level electrostatic release protection level is 3kV, and so on.

[0105] Specifically, in the customized EDA tool: since the expected electrostatic release protection level is divided into levels based on the unit electrostatic release protection capability, the electrostatic release protection level is proportional to the unit electrostatic release protection module, and the customized EDA tool maps the electrostatic release protection level and the unit electrostatic release protection module. For example, the first-level electrostatic release protection level corresponds to the electrostatic release protection capability provided by the unit electrostatic release protection module, and the second-level electrostatic release protection level corresponds to the electrostatic release protection capability provided by two unit electrostatic release protection modules. Then, when the user inputs the electrostatic release protection level through the GUI interface provided by the customized EDA tool, the required number of unit electrostatic release protection modules can be calculated to achieve flexible configuration of the electrostatic release protection capability.

[0106] In step S101, a configurable IO IP core is obtained, wherein the configurable IO IP core includes an IO core circuit module and an ESD protection level adjustable module, wherein the ESD protection level adjustable module includes a plurality of unit ESD protection modules, and wherein the unit ESD protection module includes a plurality of MOS modules.

[0107] In the present disclosure, the configurable IO IP core is no longer an integral module, but includes multiple functional modules such as an IO core circuit module, multiple unit electrostatic release protection modules, etc. Different functional modules implement corresponding functions, and multiple unit electrostatic release protection modules are used to realize the configuration of electrostatic release protection capability, so that the customized EDA tool can not only use the configurable IO IP core to realize customizable configuration to obtain a customized IO IP core, but also realize a more sophisticated and complex configuration of electrostatic release protection capability.

[0108] Among the multiple MOS modules included in each unit electrostatic release protection module, each MOS module corresponds to a PMOS tube or an NMOS tube when the customized IO IP core is implemented as an integrated circuit or a chip, that is, at this time, each unit electrostatic release protection module includes multiple PMOS tubes and multiple NMOS tubes.

[0109] According to an embodiment of the present disclosure, the IO core circuit module includes: a power supply voltage port, a ground port, an IO input signal port and a control signal output port. The power supply voltage port of the IO core circuit module is connected to the power supply voltage, and the ground port is grounded.

[0110] According to an embodiment of the present disclosure, the IO input signal port of the IO core circuit module is used to obtain an IO input signal from the outside, process the IO input signal to obtain a control signal, and output the control signal from a control signal output port.

[0111] The IO core circuit module in the present disclosure can provide basic functions. For example, when it is implemented as a chip or an integrated circuit, it can receive control from the internal circuit of the chip or the integrated circuit and can control the output current capability.

[0112] In step S102, the electrostatic discharge protection level input by the user for the designated pin module of the customized IO IP core is obtained.

[0113] According to an embodiment of the present disclosure, the designated pin module of the customized IO IP core is any pin module to be generated in the customized IO IP core. The electrostatic discharge protection level input by the user is the designated electrostatic discharge protection capability corresponding to the input electrostatic discharge protection level that the designated pin module of the customized IO IP core is expected to be able to achieve.

[0114] In step S103, the electrostatic release protection level adjustable module is configured according to the electrostatic release protection level, including: according to the electrostatic release protection level, one or more unit electrostatic release protection modules are selected from the multiple unit electrostatic release protection modules and the selected one or more unit electrostatic release protection modules are connected to generate a configured electrostatic release protection level adjustable module, and the configured electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level.

[0115] In the present disclosure, the configured electrostatic discharge protection level adjustable module may include one or more unit electrostatic discharge protection modules, that is, the number of the selected unit electrostatic discharge protection modules may be one or more, wherein each selected unit electrostatic discharge protection module uses the multiple MOS modules it includes to provide unit electrostatic discharge protection capability. For example, the unit electrostatic discharge protection capability that the selected unit electrostatic discharge protection module can provide is 0.5kV, and the electrostatic discharge protection capability corresponding to the electrostatic discharge protection level input by the user is 4kV, then it is necessary to select 4kV / 0.5kV=8 unit electrostatic discharge protection modules from the electrostatic discharge protection level adjustable module, and connect the selected 8 unit electrostatic discharge protection modules, so as to obtain the configured electrostatic discharge protection level adjustable module to provide 4kV electrostatic discharge protection capability.

[0116] In step S104, the IO core circuit module and the configured electrostatic discharge protection module are connected to generate a designated pin module of the customized IO IP core.

[0117] When the designated pin module of the customized IO IP core implemented in the present disclosure is implemented as a designated pin in a chip or an integrated circuit, the designated pin can provide the chip or the integrated circuit with a designated electrostatic discharge protection capability corresponding to the electrostatic discharge protection level.

[0118] The control signal output port of the IO core circuit module is connected to the control signal input port of the selected unit electrostatic release protection module, and is used to output a control signal to the selected unit electrostatic release protection module based on the IO input signal.

[0119] According to an embodiment of the present disclosure, the selected unit electrostatic discharge protection module includes: a power supply voltage port, a ground port and a control signal input port. The power supply voltage port of the selected unit electrostatic discharge protection module is connected to the power supply voltage, and the ground port is grounded.

[0120] According to an embodiment of the present disclosure, in the selected unit electrostatic release protection module, the MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and provides an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute a unit electrostatic release protection capability.

[0121] Among them, the IO core circuit module transmits the control signal to the control signal input port of the selected unit electrostatic release protection module through the control signal output port, and the MOS module connected to the control signal input port of the selected unit electrostatic release protection module can not only provide the first electrostatic release protection capability, but also accept the control of the control signal to provide output current capability. The MOS module not connected to the control signal input port of the selected unit electrostatic release protection module can only provide the second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the unit electrostatic release protection capability.

[0122] The present disclosure can utilize a customized EDA tool to input specific electrostatic discharge protection level requirements to configure the configurable IO IP core, and then adjust it according to the needs of the actual chip to achieve flexible and configurable electrostatic discharge protection capabilities, so that the customized IO IP core generated by the customized EDA tool and the configurable IO IP core can meet the design requirements of complex industrial chips with different electrostatic discharge protection levels.

[0123] In the present disclosure, in the unit electrostatic discharge protection module, the control signal sent by the IO core circuit module is obtained from the control signal input port to respectively control the PMOS module and the NMOS module connected to the control signal input port, so that the unit electrostatic discharge protection module can provide the unit electrostatic discharge protection capability while controlling the PMOS module and the NMOS module connected to the control signal input port to provide the corresponding output current capability. The present disclosure can provide the desired output current capability while providing the desired electrostatic discharge protection capability.

[0124] Reference below Figure 2-Figure 4 , the unit electrostatic discharge protection module in the configured electrostatic discharge protection level adjustable module, that is, the selected unit electrostatic discharge protection module is described, and those skilled in the art should understand that Figure 2-Figure 4The examples shown are various specific implementations of the selected unit electrostatic discharge protection module. When the number of the selected unit electrostatic discharge protection modules is multiple, the various specific implementations can be combined according to user needs.

[0125] In the first embodiment: all MOS modules in the selected unit electrostatic discharge protection module are connected to the control signal input port of the selected unit electrostatic discharge protection module, and all connected MOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time, such as Figure 2 At this time, all MOS modules in the selected unit electrostatic discharge protection module not only provide unit electrostatic discharge protection capability, but also provide unit output current capability.

[0126] In a second embodiment: some MOS modules in the selected unit electrostatic discharge protection module are connected to the control signal input port of the selected unit electrostatic discharge protection module, and the connected part of the MOS modules simultaneously provide part of the unit electrostatic discharge protection capability and the corresponding output current capability, and the remaining MOS modules provide the remaining unit electrostatic discharge protection capability, such as Figure 3 At this time, some MOS modules in the selected unit electrostatic release protection module provide both partial unit electrostatic release protection capability and corresponding output current capability, while the remaining MOS modules only provide the remaining unit electrostatic release protection capability, and the partial unit electrostatic release protection capability and the remaining unit electrostatic release protection capability together constitute the unit electrostatic release protection capability.

[0127] In a third embodiment: all MOS modules in the selected unit electrostatic discharge protection module are disconnected from the control signal input port of the selected unit electrostatic discharge protection module, and all disconnected MOS modules provide unit electrostatic discharge protection capability, such as Figure 4 At this time, all MOS modules in the selected unit electrostatic discharge protection module only provide unit electrostatic discharge protection capability, but cannot provide unit output current capability.

[0128] exist Figure 3 In the example shown, that is, when some MOS modules in the selected unit electrostatic release protection module are connected to the control signal input port of the selected unit electrostatic release protection module, in the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0129] Specifically, in the remaining MOS modules of the selected unit electrostatic release protection module: the gate and source of a part of the MOS modules are short-circuited and connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and grounded through the ground port. For example, when the configured unit electrostatic release protection module is implemented as a chip or an integrated circuit, the remaining MOS modules correspond to one or more PMOS tubes and one or more NMOS tubes. It is necessary to short-circuit the gate and source of one or more PMOS tubes corresponding to the remaining MOS modules and connect the power supply voltage through the power supply voltage port VDD to form a GDPMOS (Gate VDD PMOS) structure, and short-circuit the gate and source of one or more NMOS tubes corresponding to the remaining MOS modules and connect them to the power supply voltage through the ground port VSS to form a GGNMOS (Gate Ground NMOS) structure, such as Figure 6 shown.

[0130] Alternatively, in the remaining MOS modules of the selected unit electrostatic release protection module: gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and gates of other MOS modules are grounded through the resistor module and the ground port.

[0131] Specifically, in the remaining MOS modules of the selected unit electrostatic release protection module: the gate and source of a part of the MOS modules are short-circuited and then connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and then grounded through the resistor module and the grounding port. For example, when the configured unit electrostatic release protection module is implemented as a chip or an integrated circuit, the remaining MOS modules correspond to one or more PMOS tubes and one or more NMOS tubes. It is necessary to short-circuit the gate and source of one or more PMOS tubes corresponding to the remaining MOS modules and then connect the power supply voltage through the resistor module and the power supply voltage port VDD to form an RGPMOS (Resistor-Gate PMOS) structure, and short-circuit the gate and source of one or more NMOS tubes corresponding to the remaining MOS modules and then connect to the power supply voltage through the resistor module and the grounding port VSS to form an RGNMOS (Resistor-Gate NMOS) structure, such as Figure 6 shown.

[0132] exist Figure 4In the example shown, that is, when all MOS modules in the selected unit electrostatic release protection module are disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0133] Specifically, in all MOS modules of the selected unit electrostatic release protection module: in all MOS modules of the selected unit electrostatic release protection module: the gate and source of a part of the MOS modules are short-circuited and connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and grounded through the ground port. For example, when the configured unit electrostatic release protection module is implemented as a chip or an integrated circuit, all the MOS modules correspond to a plurality of PMOS tubes and a plurality of NMOS tubes, then it is necessary to short-circuit the gate and source of the plurality of PMOS tubes corresponding to the entire MOS modules and connect the power supply voltage through the power supply voltage port VDD to form a GDPMOS structure, and short-circuit the gate and source of the plurality of NMOS tubes corresponding to the entire MOS modules and connect them to the ground through the ground port VSS to form a GGNMOS structure, such as Figure 5 shown.

[0134] Alternatively, among all MOS modules of the selected unit electrostatic discharge protection module: gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and gates of other MOS modules are grounded through the resistor module and the ground port.

[0135] Specifically, in all MOS modules of the selected unit electrostatic release protection module: the gate and source of a part of the MOS modules are short-circuited and then connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and then grounded through the resistor module and the grounding port. For example, when the configured unit electrostatic release protection module is implemented as a chip or an integrated circuit, the whole MOS modules correspond to a plurality of PMOS tubes and a plurality of NMOS tubes, then the gate and source of the plurality of PMOS tubes corresponding to the whole MOS modules need to be short-circuited and then connected to the power supply voltage through the resistor module and the power supply voltage port VDD to form an RGPMOS structure, and the gate and source of the plurality of NMOS tubes corresponding to the whole MOS modules need to be short-circuited and then connected to the power supply voltage through the resistor module and the grounding port VSS to form a GGNMOS structure, such as Figure 6 shown.

[0136] Figure 7A schematic diagram showing the connection between an IO core circuit module and the configured module with adjustable electrostatic discharge protection level in a configuration method of an IO IP core with adjustable electrostatic discharge protection level according to an embodiment of the present disclosure. Figure 7 The example shown shows an ESD protection level adjustable module configured with Figure 4 The example shown is used for illustration. Those skilled in the art should understand that the configured electrostatic discharge protection level adjustable module can also be Figure 2 , Figure 3 Examples shown, etc.

[0137] like Figure 7 As shown, the customized IO IP core includes: an IO core circuit module and a configured unit electrostatic release protection module, the control signal output port of the IO core circuit module is connected to the control signal input port of the configured unit electrostatic release protection module, and the control signal input port of the configured unit electrostatic release protection module is disconnected from all MOS modules of the configured unit electrostatic release protection module.

[0138] Among them, the IO core circuit module includes: a power supply voltage port, a ground port, an IO input signal port and a control signal output port; the selected unit electrostatic release protection module includes: a power supply voltage port, a ground port and a control signal input port.

[0139] The power supply voltage ports of the IO core circuit module and the configured unit electrostatic release protection module are both connected to the power supply voltage, and the ground ports are both grounded. The IO input signal port of the IO core circuit module receives an external IO input signal, obtains a control signal after processing and outputs it through a control signal output port. The configured unit electrostatic release protection module obtains the control signal through the control signal input port to control the MOS module connected to the control signal input port of the configured unit electrostatic release protection module to simultaneously provide partial unit electrostatic release protection capability and corresponding output current capability. Figure 7 In the example shown, the control input port of the configured unit electrostatic release protection module is disconnected from all MOS modules included therein, and therefore, the configured unit electrostatic release protection module can only provide unit electrostatic release protection capability.

[0140] For example, when a pin module of a customized IO IP core needs to have a 5kV electrostatic discharge protection capability, when the configured electrostatic discharge protection module is implemented as an integrated circuit or a chip, assuming that the unit electrostatic discharge protection capability that can be provided by a unit electrostatic discharge protection module in the configured electrostatic discharge protection module is 0.5kV, then under the 0.18um design process, 5kV / 0.5kV=10 unit electrostatic discharge protection modules need to be connected to the IO core circuit.

[0141] For another example, a pin module of a customized IO IP core needs to have both 4kV electrostatic discharge protection capability and 4mA output current capability. When the configured electrostatic discharge protection module is implemented as an integrated circuit or chip, assuming that the unit electrostatic discharge protection capability that can be provided by a unit electrostatic discharge protection module in the configured electrostatic discharge protection module is 0.5kV, then under the 0.18um design process, when all MOS tubes in a unit electrostatic discharge protection module are used, the unit output current capability that can be provided is 1mA, then 4kV / 0.5kV=8 unit electrostatic release protection modules need to be connected to the IO core circuit, of which 4 unit electrostatic release protection modules need to provide both unit electrostatic release protection capability and unit output current capability, and the remaining 4 unit electrostatic release protection modules only need to provide unit electrostatic release protection capability.

[0142] According to an embodiment of the present disclosure, based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

[0143] According to an embodiment of the present disclosure, a bottom module is obtained, and the bottom of the designated pin module of the customized IO IP core is sealed using the bottom module to generate a designated pin module with a sealed bottom.

[0144] The present disclosure inserts a bottom module at the bottom of a designated pin module to achieve the requirement of closing the overall circuit layout and satisfy the design rule check.

[0145] According to an embodiment of the present disclosure, a second designated pin circuit layout of the customized IO IP core is generated based on the bottom-enclosed designated pin module.

[0146] The present disclosure can automatically generate a designated pin circuit layout based on the designated pin module of the designed custom IO IP core, thereby facilitating the subsequent manufacture of integrated circuits or chips.

[0147] Figure 8 A schematic diagram of splicing pin modules in a configuration method of an IO IP core with adjustable electrostatic discharge protection level according to an embodiment of the present disclosure is shown.

[0148] like Figure 8 As shown, at least one filling module is obtained, and the filling module includes: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; multiple pin modules of the customized IO IP core are generated; the multiple pin modules are spliced ​​to obtain a spliced ​​pin module; and the vacancies in the spliced ​​pin module are filled with the at least one filling module to obtain a filled spliced ​​pin module.

[0149] According to an embodiment of the present disclosure, a multi-pin circuit layout of the customized IO IP core is generated based on the filled spliced ​​pin module.

[0150] The present disclosure can flexibly configure multiple pin modules of a customized IO IP core, further increasing the flexible configuration of electrostatic discharge protection levels of different pin modules.

[0151] In order to meet the design rule check (DRC) of the layout design, the present disclosure also provides a filling module so that the integrated circuit or chip can meet the design requirements during the manufacturing process.

[0152] According to an embodiment of the present disclosure, a plurality of bottom modules are provided, and the number of the bottom modules is consistent with the number of the plurality of pin modules; after obtaining the filled splicing pin module, the bottom of the filled splicing pin module is closed using the plurality of bottom modules to generate a splicing pin module with a closed bottom.

[0153] According to an embodiment of the present disclosure, when a corresponding plurality of module layouts are generated based on the IO core circuit module and the configured electrostatic discharge protection module, the widths of the plurality of module layouts are consistent.

[0154] According to an embodiment of the present disclosure, when a corresponding plurality of module layouts are generated based on the IO core circuit module, the configured electrostatic discharge protection module, the filling module and the bottom module, the widths of the plurality of module layouts are consistent.

[0155] In order to save the design area of ​​the circuit layout, the widths of the modules in the designated pin modules are set to be consistent, thereby saving design costs and reducing resource waste.

[0156] The present disclosure can automatically generate a designated pin circuit layout based on the designated pin module of the generated custom IO IP core, which facilitates the subsequent manufacture of integrated circuits or chips. When manufacturing based on the above circuit layout, it is necessary to manufacture according to the layout border. The layout border defines the physical shape of the circuit board after processing. The chip process manufacturer or manufacturer will cut and process the circuit board according to the layout border to ensure that the size and shape of the circuit board meet the design requirements.

[0157] Fig. 9 FIG. 1 is a flow chart showing a method for providing a configurable IO IP core according to an embodiment of the present disclosure. Fig. 9 As shown, the method includes steps S901 to S902.

[0158] In step S901, an IO core circuit module is provided, wherein the IO core circuit module includes an IO input signal port, a control signal output port, a power supply voltage port and a ground port, and is used to process the received IO input signal and output a control signal.

[0159] In step S902, an electrostatic release protection level adjustable module is provided, and the electrostatic release protection level adjustable module includes multiple unit electrostatic release protection modules, each unit electrostatic release protection module includes: multiple MOS modules, a control signal input port, a power supply voltage port and a ground port, and the customized EDA tool selects one or more unit electrostatic release protection modules from the multiple unit electrostatic release protection modules according to the electrostatic release protection level and connects the selected one or unit electrostatic release protection modules to provide an electrostatic release protection capability corresponding to the electrostatic release protection level.

[0160] The present disclosure can provide a configurable IO IP core for a customized EDA tool, so that the configurable IO IP core can be configured through the customized EDA tool to achieve flexible and adjustable electrostatic discharge protection capability.

[0161] According to an embodiment of the present disclosure, when some or all MOS modules in a selected unit electrostatic release protection module are selected by a customized EDA tool to be connected to the control signal input port of the selected unit electrostatic release protection module, the connected some or all MOS modules simultaneously provide corresponding electrostatic release protection capability and output current capability.

[0162] According to an embodiment of the present disclosure, when some or all MOS modules in a selected unit electrostatic release protection module are not selected by a customized EDA tool to be disconnected from the control signal input port of the selected unit electrostatic release protection module, the disconnected some or all MOS modules provide corresponding electrostatic release protection capabilities.

[0163] According to an embodiment of the present disclosure, when some MOS modules in a selected unit electrostatic release protection module are selected by a customized EDA tool to be connected to the control signal input port of the selected unit electrostatic release protection module, in the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0164] According to an embodiment of the present disclosure, when all MOS modules in a selected unit electrostatic release protection module are not selected by a customized EDA tool to be disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of a part of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the MOS modules are grounded through the ground port.

[0165] According to an embodiment of the present disclosure, when some MOS modules in a selected unit electrostatic release protection module are selected by a customized EDA tool to be connected to the control signal input port of the selected unit electrostatic release protection module, in the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through a resistance module and a power supply voltage port, and the gates of other MOS modules are grounded through a resistance module and a ground port.

[0166] According to an embodiment of the present disclosure, when all MOS modules in a selected unit electrostatic release protection module are not selected by a customized EDA tool to be disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of a part of the MOS modules are connected to the power supply voltage through a resistance module and a power supply voltage port, and the gates of another part of the MOS modules are grounded through a resistance module and a ground port.

[0167] According to an embodiment of the present disclosure, it also includes:

[0168] A filling module is provided, the filling module comprising: a power supply voltage port and a ground port, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

[0169] According to an embodiment of the present disclosure, it also includes:

[0170] A bottom module is provided, and the bottom module is used to close the bottom of one or more pin modules when one or more pin modules of a customized IO IP core are generated based on the provided configurable IO IP core.

[0171] The configurable IO IP core provided by the present disclosure has various forms, which can be an IP soft core designed by hardware description language (HDL), which allows users to flexibly modify and customize according to their needs, and each module in the provided configurable IO IP core can be in the form of a soft core; it can also be an IP solid core provided in the form of a gate-level circuit netlist to provide users with a more specific and optimized circuit design implementation, and each module in the provided configurable IO IP core can be in the form of a solid core; it can also be an IP hard core that provides a verified design circuit layout, and each module in the provided configurable IO IP core can be in the form of a hard core, which ensures the stability and reliability of the chip circuit design, and users can use it directly without further verification.

[0172] In a specific embodiment, the HDL codes for implementing each module in the customized IO IP core may be stored in a code library, so that users can conveniently download and use the code library.

[0173] Fig.10 A schematic diagram of a configuration device for an IO IP core with adjustable electrostatic discharge protection level according to an embodiment of the present disclosure is shown, and the device is implemented based on an EDA tool.

[0174] like Fig.10 As shown, the device 1000 includes: a first acquisition module 1001 , a second acquisition module 1002 , an electrostatic discharge protection configuration module 1003 and a generation module 1004 .

[0175] A first acquisition module 1001 is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module and an electrostatic discharge protection level adjustable module, wherein the electrostatic discharge protection level adjustable module includes a plurality of unit electrostatic discharge protection modules, and wherein the unit electrostatic discharge protection module includes a plurality of MOS modules;

[0176] The second acquisition module 1002 is configured to acquire the electrostatic discharge protection level input by the user for the designated pin module of the customized IO IP core;

[0177] The electrostatic discharge protection configuration module 1003 is configured to configure the electrostatic discharge protection level adjustable module according to the electrostatic discharge protection level, including: selecting one or more unit electrostatic discharge protection modules from the multiple unit electrostatic discharge protection modules according to the electrostatic discharge protection level and connecting the selected one or more unit electrostatic discharge protection modules to generate a configured electrostatic discharge protection level adjustable module, wherein the configured electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level;

[0178] The generating module 1004 is configured to connect the IO core circuit module and the configured electrostatic discharge protection module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes a power supply voltage port, a ground port, an IO input signal port, and a control signal output port; and the selected unit electrostatic discharge protection module includes a power supply voltage port, a ground port, and a control signal input port;

[0179] The power supply voltage ports of the IO core circuit module and the selected unit electrostatic discharge protection module are both connected to the power supply voltage, and the grounding ports are both grounded;

[0180] The control signal output port of the IO core circuit module is connected to the control signal input port of the selected unit electrostatic discharge protection module, and is used to output a control signal to the selected unit electrostatic discharge protection module based on the IO input signal;

[0181] In the selected unit electrostatic release protection module, the MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute a unit electrostatic release protection capability.

[0182] According to an embodiment of the present disclosure, it further includes: a third acquisition module configured to acquire a bottom module, wherein the bottom module is used to close the bottom of the designated pin module of the custom IO IP core to generate a designated pin module with a closed bottom.

[0183] According to an embodiment of the present disclosure, it also includes: a fourth acquisition module, configured to acquire at least one filling module, the filling module including: a power supply voltage port and a ground port, the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the customized IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the customized IOIP core.

[0184] Fig.11 A schematic diagram of an apparatus 1100 for providing a configurable IO IP core according to an embodiment of the present disclosure is shown.

[0185] like Fig.11 As shown, the device 1100 includes a first providing module 1101 and a second providing module 1102 .

[0186] The first providing module 1101 is configured to provide an IO core circuit module, which includes an IO input signal port, a control signal output port, a power supply voltage port and a ground port, and is used to process the received IO input signal and output a control signal.

[0187] The second providing module 1102 is configured to provide an electrostatic release protection level adjustable module, wherein the electrostatic release protection level adjustable module includes multiple unit electrostatic release protection modules, each unit electrostatic release protection module includes: multiple MOS modules, a control signal input port, a power supply voltage port and a ground port, and the customized EDA tool selects one or more unit electrostatic release protection modules from the multiple unit electrostatic release protection modules according to the electrostatic release protection level and connects the selected one or unit electrostatic release protection modules to provide an electrostatic release protection capability corresponding to the electrostatic release protection level.

[0188] According to an embodiment of the present disclosure, it also includes:

[0189] A third providing module is configured to provide a filling module, wherein the filling module includes: a power supply voltage port and a ground port, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

[0190] According to an embodiment of the present disclosure, it also includes:

[0191] The fourth providing module is configured to provide a bottom module, wherein the bottom module is used to seal the bottom of one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

[0192] The present disclosure provides a chip, including: a custom IO IP core manufactured according to the method described above, or a custom IO IP core manufactured according to the configurable IO IP core provided by the method described above.

[0193] The present disclosure provides an electronic device, comprising: the chip as described above.

[0194] The present disclosure provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the configuration method of an IO IP core as described in any of the preceding items or the method for providing a configurable IO IP core is implemented.

[0195] The present disclosure provides a computer program product, including computer instructions, which, when executed by a processor, implement the configuration method of an IO IP core as described in any of the preceding items or the method for providing a configurable IO IP core.

[0196] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0197] The units or modules involved in the embodiments described in the present disclosure may be implemented by software or programmable hardware. The units or modules described may also be set in a processor, and the names of these units or modules do not constitute limitations on the units or modules themselves in some cases.

[0198] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into a device. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the method described in the present disclosure.

[0199] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A configuration method for an IO IP core with adjustable electrostatic discharge protection level, characterized in that: The method is implemented based on a customized EDA tool, and the method includes: Acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module and an electrostatic release protection level adjustable module, wherein the electrostatic release protection level adjustable module includes a plurality of unit electrostatic release protection modules, and wherein the unit electrostatic release protection module includes a plurality of MOS modules; Get the electrostatic discharge protection level entered by the user for the specified pin module of the custom IO IP core; According to the electrostatic discharge protection level, configuring the electrostatic discharge protection level adjustable module includes: according to the electrostatic discharge protection level, selecting one or more unit electrostatic discharge protection modules from the multiple unit electrostatic discharge protection modules and connecting the selected one or more unit electrostatic discharge protection modules to generate a configured electrostatic discharge protection level adjustable module, wherein the configured electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level; Connecting the IO core circuit module and the configured electrostatic discharge protection module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes a power supply voltage port, a ground port, an IO input signal port, and a control signal output port; and the selected unit electrostatic discharge protection module includes a power supply voltage port, a ground port, and a control signal input port; The power supply voltage ports of the IO core circuit module and the selected unit electrostatic discharge protection module are both connected to the power supply voltage, and the grounding ports are both grounded; The control signal output port of the IO core circuit module is connected to the control signal input port of the selected unit electrostatic discharge protection module, and is used to output a control signal to the selected unit electrostatic discharge protection module based on the IO input signal; In the selected unit electrostatic release protection module, the MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute a unit electrostatic release protection capability.

2. The method according to claim 1, characterized in that Also includes: Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

3. The method according to claim 1, characterized in that The MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and provides an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute a unit electrostatic release protection capability, including: All MOS modules in the selected unit electrostatic discharge protection module are connected to the control signal input port of the selected unit electrostatic discharge protection module, and all connected MOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time; Alternatively, some MOS modules in the selected unit electrostatic release protection module are connected to the control signal input port of the selected unit electrostatic release protection module, and the connected part of the MOS modules simultaneously provide part of the unit electrostatic release protection capability and the corresponding output current capability, and the remaining MOS modules provide the remaining unit electrostatic release protection capability; Alternatively, all MOS modules in the selected unit electrostatic release protection module are disconnected from the control signal input port of the selected unit electrostatic release protection module, and all disconnected MOS modules provide unit electrostatic release protection capability.

4. The method according to claim 3, characterized in that: When some MOS modules in the selected unit electrostatic release protection module are connected to the control signal input port of the selected unit electrostatic release protection module, in the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port; When all MOS modules in the selected unit electrostatic release protection module are disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

5. The method according to claim 4, characterized in that The gates of a part of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the MOS modules are grounded through the ground port, including: The gate and source of a part of MOS modules are short-circuited and then connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of MOS modules are short-circuited and then grounded through the ground port.

6. The method according to claim 3, characterized in that: When some MOS modules in the selected unit electrostatic release protection module are connected to the control signal input port of the selected unit electrostatic release protection module, in the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistor module and the grounding port; When all MOS modules in the selected unit electrostatic release protection module are disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistance module and the grounding port.

7. The method according to claim 6, characterized in that The gates of a part of the MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of another part of the MOS modules are grounded through the resistor module and the ground port, including: The gate and source of a part of MOS modules are short-circuited and then connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another part of MOS modules are short-circuited and then grounded through the resistor module and the ground port.

8. The method according to claim 1, characterized in that The method further comprises: A bottom module is obtained, and the bottom of the designated pin module of the customized IO IP core is sealed by using the bottom module to generate a designated pin module with a sealed bottom.

9. The method according to claim 8, characterized in that The method further comprises: Based on the bottom-enclosed designated pin module, a second designated pin circuit layout of the customized IO IP core is generated.

10. The method according to claim 1, characterized in that The method further comprises: Acquire at least one filling module, the filling module comprising: a power supply voltage port and a ground port, the power supply voltage port of the filling module being connected to a power supply voltage, and the ground port of the filling module being grounded; Generate multiple pin modules of the customized IO IP core; Splicing the plurality of pin modules to obtain a spliced ​​pin module; The at least one filling module is used to fill the empty space in the splicing tube foot module to obtain a filled splicing tube foot module.

11. The method according to claim 10, characterized in that The method further comprises: Based on the filled spliced ​​pin module, a multi-pin circuit layout of the customized IO IP core is generated.

12. The method according to claim 1, characterized in that The customized EDA tool is used to provide an expected electrostatic discharge protection level input box to obtain the electrostatic discharge protection level input by the user for the designated pin module of the customized IO IP core.

13. The method according to claim 1, characterized in that When a corresponding plurality of module layouts are generated based on the IO core circuit module and the configured electrostatic discharge protection module, the widths of the plurality of module layouts are consistent.

14. A method for providing a configurable IO IP core, characterized in that: include: Providing an IO core circuit module, the IO core circuit module includes an IO input signal port, a control signal output port, a power supply voltage port and a ground port, and is used to process the received IO input signal and output a control signal; An electrostatic release protection level adjustable module is provided, wherein the electrostatic release protection level adjustable module includes multiple unit electrostatic release protection modules, each unit electrostatic release protection module includes: multiple MOS modules, a control signal input port, a power supply voltage port and a ground port, and a customized EDA tool selects one or more unit electrostatic release protection modules from the multiple unit electrostatic release protection modules according to the electrostatic release protection level and connects the selected one or unit electrostatic release protection modules to provide an electrostatic release protection capability corresponding to the electrostatic release protection level.

15. The method according to claim 14, characterized in that: When some or all of the MOS modules in the selected unit electrostatic discharge protection module are selected by the custom EDA tool to be connected to the control signal input port of the selected unit electrostatic discharge protection module, the connected part or all of the MOS modules simultaneously provide corresponding electrostatic discharge protection capability and output current capability; When some or all MOS modules in the selected unit ESD protection module are not selected by the custom EDA tool to be disconnected from the control signal input port of the selected unit ESD protection module, the disconnected some or all MOS modules provide corresponding ESD protection capabilities.

16. The method according to claim 14, characterized in that: When some MOS modules in the selected unit electrostatic release protection module are selected by the custom EDA tool to be connected to the control signal input port of the selected unit electrostatic release protection module, among the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port; When all MOS modules in a selected unit electrostatic release protection module are not selected by the customized EDA tool to be disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of a part of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the MOS modules are grounded through the ground port.

17. The method according to claim 14, characterized in that: When some MOS modules in the selected unit electrostatic release protection module are selected by the custom EDA tool to be connected to the control signal input port of the selected unit electrostatic release protection module, among the remaining MOS modules of the selected unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistor module and the ground port; When all MOS modules in a selected unit electrostatic release protection module are not selected by the customized EDA tool to be disconnected from the control signal input port of the selected unit electrostatic release protection module, among all MOS modules in the selected unit electrostatic release protection module: the gates of a part of the MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of another part of the MOS modules are grounded through the resistance module and the ground port.

18. The method according to claim 14, characterized in that Also includes: A filling module is provided, the filling module comprising: a power supply voltage port and a ground port, which is used to fill empty positions in a spliced ​​pin module of a custom IO IP core when generating multiple pin modules of a custom IO IP core based on a provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

19. The method according to claim 14, characterized in that Also includes: A bottom module is provided, and the bottom module is used to close the bottom of one or more pin modules when one or more pin modules of a customized IO IP core are generated based on the provided configurable IO IP core.

20. A configuration device for an IO IP core with adjustable electrostatic discharge protection level, the device being implemented based on a customized EDA tool, the device comprising: A first acquisition module is configured to acquire a configurable IO IP core, wherein the configurable IO IP core includes an IO core circuit module and an electrostatic discharge protection level adjustable module, wherein the electrostatic discharge protection level adjustable module includes a plurality of unit electrostatic discharge protection modules, and wherein the unit electrostatic discharge protection module includes a plurality of MOS modules; A second acquisition module is configured to acquire an electrostatic discharge protection level input by a user for a designated pin module of a customized IO IP core; The electrostatic discharge protection configuration module is configured to configure the electrostatic discharge protection level adjustable module according to the electrostatic discharge protection level, including: selecting one or more unit electrostatic discharge protection modules from the plurality of unit electrostatic discharge protection modules according to the electrostatic discharge protection level and connecting the selected one or more unit electrostatic discharge protection modules to generate a configured electrostatic discharge protection level adjustable module, wherein the configured electrostatic discharge protection level adjustable module is used to provide a specified electrostatic discharge protection capability corresponding to the electrostatic discharge protection level; A generating module is configured to connect the IO core circuit module and the configured electrostatic discharge protection module to generate a designated pin module of the customized IO IP core, wherein the IO core circuit module includes a power supply voltage port, a ground port, an IO input signal port, and a control signal output port; and the selected unit electrostatic discharge protection module includes a power supply voltage port, a ground port, and a control signal input port; The power supply voltage ports of the IO core circuit module and the selected unit electrostatic discharge protection module are both connected to the power supply voltage, and the grounding ports are both grounded; The control signal output port of the IO core circuit module is connected to the control signal input port of the selected unit electrostatic discharge protection module, and is used to output a control signal to the selected unit electrostatic discharge protection module based on the IO input signal; In the selected unit electrostatic release protection module, the MOS module connected to the control signal input port of the selected unit electrostatic release protection module simultaneously provides a first electrostatic release protection capability and an output current capability under the control of the control signal of the IO core circuit module, and the MOS module disconnected from the control signal input port of the selected unit electrostatic release protection module provides a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute a unit electrostatic release protection capability.

21. The device according to claim 20, characterized in that Also includes: The third acquisition module is configured to acquire a bottom module, where the bottom module is used to close the bottom of the designated pin module of the customized IO IP core to generate a designated pin module with a closed bottom.

22. The device according to claim 20, characterized in that Also includes: A fourth acquisition module is configured to acquire at least one filling module, wherein the filling module includes: a power supply voltage port and a ground port, wherein the power supply voltage port of the filling module is connected to the power supply voltage, and the ground port of the filling module is grounded; the filling module is used to fill the vacancies in the splicing pin module of the custom IO IP core to obtain the filled splicing pin module, wherein the splicing pin module is obtained by splicing multiple pin modules of the custom IO IP core.

23. A device for providing a configurable IO IP core, characterized in that: include: A first providing module is configured to provide an IO core circuit module, wherein the IO core circuit module includes an IO input signal port, a control signal output port, a power supply voltage port and a ground port, and is used to process the received IO input signal and output a control signal; The second providing module is configured to provide an electrostatic release protection level adjustable module, the electrostatic release protection level adjustable module includes multiple unit electrostatic release protection modules, each unit electrostatic release protection module includes: multiple MOS modules, control signal input ports, power supply voltage ports and ground ports, the customized EDA tool selects one or more unit electrostatic release protection modules from the multiple unit electrostatic release protection modules according to the electrostatic release protection level and connects the selected one or unit electrostatic release protection modules to provide an electrostatic release protection capability corresponding to the electrostatic release protection level.

24. The device according to claim 23, characterized in that Also includes: A third providing module is configured to provide a filling module, wherein the filling module includes: a power supply voltage port and a ground port, which is used to fill the empty positions in the spliced ​​pin module of the custom IO IP core when generating multiple pin modules of the custom IO IP core based on the provided configurable IO IP core, wherein the spliced ​​pin module is obtained by splicing the multiple pin modules.

25. The device according to claim 23, characterized in that Also includes: The fourth providing module is configured to provide a bottom module, wherein the bottom module is used to seal the bottom of the one or more pin modules when generating one or more pin modules of a customized IO IP core based on the provided configurable IO IP core.

26. A chip, characterized in that: The method comprises manufacturing a customized IO IP core generated by the method according to any one of claims 1 to 13, or manufacturing a customized IO IP core generated by the configurable IO IP core provided by the method according to any one of claims 14 to 19.

27. An electronic device, characterized in that: Comprising a chip according to claim 26.

28. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 19 is implemented.

29. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the method according to any one of claims 1 to 19.

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