Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a preparation method of the semiconductor device, and the semiconductor device comprises a synaptic unit which comprises a synaptic circuit, and the synaptic circuit comprises at least one first conduction element and is used for receiving at least one input signal and outputting at least one synaptic pulse signal; the neuron unit comprises at least one integrated circuit, and the integrated circuit comprises a second conduction element and is used for receiving the synaptic pulse signal and outputting an integrated signal; wherein the first conduction element and the second conduction element are conduction elements with threshold value overturning characteristics. According to the semiconductor device and the preparation method of the semiconductor device provided by the invention, the semiconductor device not only has good reliability, but also can receive an external continuous signal, convert the external continuous signal into a pulse signal and transmit the pulse signal to the neuron unit for charge accumulation and ignition, and can control the weight of an input signal through a current, thereby improving the reliability of the semiconductor device. Therefore, array learning characteristics are realized, and a complete artificial neural network based on a single OTS device is realized.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more particularly to a semiconductor device serving as an artificial neural network and a method for preparing the semiconductor device. Background Art

[0002] Artificial neural networks, due to their event-based and data-driven characteristics, have shown significant potential in reducing computing energy consumption. Current artificial neural networks are gradually formed by semiconductor devices, especially using memories with memory functions.

[0003] However, the synaptic units and neuron unit structures in the current artificial neural network seriously affect the speed of information transmission, and are not conducive to integration, and are even more unfavorable to the adjustment of training and learning, and there have always been problems. Although the industry has made remedies for this problem from many aspects, it has not yet been well solved. Summary of the invention

[0004] The purpose of this application is to provide a semiconductor device as an artificial neural network to solve the problems of information input type and speed as well as integration and adjustment.

[0005] In a first aspect, the present application provides a semiconductor device, the semiconductor device comprising:

[0006] A synaptic unit, comprising a synaptic circuit, wherein the synaptic circuit comprises at least one first conductive element, and is used to receive at least one input signal and output at least one synaptic pulse signal; and

[0007] The neuron unit comprises at least one accumulation circuit, wherein the accumulation circuit comprises a second conduction element and is used to receive the synaptic pulse signal and output an accumulation signal;

[0008] The first conduction element and the second conduction element are both conduction elements with threshold reversal characteristics.

[0009] Optionally, the first conduction element and the second conduction element are both bidirectional threshold switch (OTS) devices, and the bidirectional threshold switch (OTS) device has current-controllable relaxation behavior and the threshold flip characteristic.

[0010] Optionally, the accumulation circuit also includes a capacitor connected in parallel with the second conduction element, for accumulating one of the synaptic pulse signals.

[0011] Optionally, the synapse unit also includes a weighting circuit, which includes at least one current setting circuit and is used to provide at least one weighted current to the output end of the at least one first conduction element, so that the synapse unit outputs the at least one synaptic pulse signal in response to the at least one weighted current.

[0012] Optionally, the current setting circuit includes a current mirror and an adjustable current source, and the adjustable current source can be used to control the pulse frequency of the synaptic pulse signal and the weighted size of the input signal.

[0013] Optionally, the synapse circuit includes a plurality of first conduction elements, and the plurality of first conduction elements form a conduction array, the conduction array includes at least one first input line and at least one first output line connected to the plurality of first conduction elements, the at least one first input line receives the at least one input signal, and the at least one first output line outputs the at least one synaptic pulse signal.

[0014] Optionally, the at least one first input line includes a plurality of first input lines for respectively receiving a plurality of the input signals, and each of the input signals represents a bit in a binary value.

[0015] Optionally, the at least one first output line includes a plurality of the first output lines, and the plurality of first output lines respectively output a plurality of the synaptic pulse signals. The at least one accumulation circuit includes a plurality of the accumulation circuits for respectively accumulating the plurality of synaptic pulse signals and outputting a plurality of the accumulation signals.

[0016] Optionally, the at least one current setting circuit includes a plurality of current setting circuits, which are respectively connected to the plurality of first output lines and are used to respectively provide a plurality of weighted currents to the plurality of first output lines so that the plurality of first output lines respectively output a plurality of synaptic pulse signals.

[0017] Optionally, the at least one accumulation signal is connected to an input terminal or an output comparator of a synaptic unit in a next layer.

[0018] In a second aspect, the present application provides a method for preparing a semiconductor device, the method comprising:

[0019] forming a synaptic unit, and making the synaptic unit include a synaptic circuit, wherein the synaptic circuit includes at least one first conductive element, and is used to receive at least one input signal and output at least one synaptic pulse signal; and

[0020] Forming a neuron unit, and making the neuron unit include at least one accumulation circuit, and making the accumulation circuit include a second conducting element, and used for receiving the synaptic pulse signal and outputting an accumulation signal;

[0021] And wherein the method further includes forming the first conduction element and the second conduction element by a conduction element having a threshold flip characteristic.

[0022] Optionally, the step of forming the first conduction element and the second conduction element includes forming the first conduction element and the second conduction element by a bidirectional threshold switch (OTS) device having current-controllable relaxation behavior and the threshold flipping characteristic.

[0023] Optionally, the step of forming a neuron unit further includes forming a capacitor in parallel with the second conduction element in the accumulation circuit for accumulating one of the synaptic pulse signals.

[0024] Optionally, the step of forming a synaptic unit also includes forming a weighting circuit, and the weighting circuit includes at least one current setting circuit, and is used to provide at least one weighted current to the output end of the at least one first conduction element, so that the synaptic unit responds to the at least one weighted current and outputs the at least one synaptic pulse signal.

[0025] Optionally, the step of forming a weighted circuit also includes forming a current mirror and an adjustable current source to form the current setting circuit, and the adjustable current source is used to control the pulse frequency of the synaptic pulse signal and the weighted size of the input signal.

[0026] Optionally, the step of forming a synaptic unit also includes making the synaptic circuit include a conductive array composed of a plurality of the first conductive elements, and at least one first input line and at least one first output line connected to the plurality of first conductive elements, and making the at least one first input line receive the at least one input signal and making the at least one first output line output the at least one synaptic pulse signal.

[0027] Optionally, the step of forming a synaptic unit further includes forming a plurality of the first input lines for respectively receiving a plurality of the input signals, and each of the input signals represents a bit in a binary value.

[0028] Optionally, the step of forming a synapse unit also includes forming a plurality of the first output lines, and making the plurality of the first output lines respectively output a plurality of the synaptic pulse signals, and forming a plurality of the accumulation circuits for respectively accumulating the plurality of synaptic pulse signals and outputting a plurality of the accumulation signals.

[0029] Optionally, the step of forming a synapse unit also includes forming a plurality of the current setting circuits, and connecting them to the plurality of first output lines respectively, so as to provide a plurality of the weighted currents to the plurality of first output lines respectively, and enable the plurality of first output lines to output a plurality of the synaptic pulse signals respectively.

[0030] Optionally, the preparation method further includes forming a next-layer synaptic unit or an output comparator, so that the at least one accumulation signal is connected to an input terminal of the next-layer synaptic unit or the output comparator.

[0031] The semiconductor device and the method for preparing the semiconductor device provided by the present application not only have good reliability and can receive external continuous signals and convert them into pulse signals, thereby transmitting them to neurons for charge accumulation and ignition, but also can control the weight of the input signal through current, thereby realizing array learning characteristics, and further realizing a complete artificial neural network based on a single OTS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0033] Figure 1 is a schematic diagram of a circuit structure of a semiconductor device provided according to some embodiments of the present application;

[0034] Figure 2a is a schematic diagram of the structure of a conduction element provided according to some embodiments of the present application;

[0035] Figure 2b is a schematic diagram of threshold reversal characteristics of a conduction element provided according to some embodiments of the present application;

[0036] Figure 3 is a waveform diagram of an input signal converted into a pulse signal according to some embodiments of the present application;

[0037] Figure 4 is another circuit structure schematic diagram of a semiconductor device provided according to some embodiments of the present application;

[0038] Figure 5 is a waveform diagram of a pulse signal under different weightings provided in some embodiments of the present application;

[0039] Figure 6 is another circuit structure schematic diagram of a semiconductor device provided according to some embodiments of the present application;

[0040] Figure 7 is a schematic block diagram of a semiconductor device provided according to some embodiments of the present application;

[0041] Figure 8 is a schematic diagram of mapping a semiconductor device and a graphical neural network according to some embodiments of the present application;

[0042] Fig. 9 The present invention is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0044] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0045] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0046] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer and one or more dielectric layers.

[0047] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0048] Figure 1 is a schematic diagram of a circuit structure of a semiconductor device provided according to some embodiments of the present application. Figure 1As shown, a semiconductor device 100 provided according to some embodiments of the present application includes a synaptic unit 101 and a neuron unit 102. The synaptic unit 101 includes a synaptic circuit 101a, and the synaptic circuit 101a includes at least one first transmission element 11a, and is used to receive at least one input signal Vin and output at least one synaptic pulse signal Pa. The neuron unit 102 includes at least one accumulation circuit 13, and the accumulation circuit 13 includes a second transmission element 13a, and is used to receive the synaptic pulse signal Pa and output an accumulation signal Vout; wherein the first transmission element 11a and the second transmission element 13a are both transmission elements with threshold flip characteristics.

[0049] The synaptic circuit 101a also includes at least one first input line 11b (also referred to as a word line WL) connected to the input end of the at least one first conduction element 11a and at least one first output line 11b (also referred to as a bit line BL) connected to the output end of the at least one first conduction element 11a, which respectively receive the input signal Vin and output the synaptic pulse signal Pa.

[0050] In some embodiments, the first conduction element 11a and the second conduction element 13a are both bidirectional threshold switch (OTS) devices, and the bidirectional threshold switch (OTS) device has current-controllable relaxation behavior and the threshold flip characteristic.

[0051] Specifically, Figure 2a and Figure 2b As shown, Figure 2a is a schematic diagram of the structure of a conduction element provided according to some embodiments of the present application; Figure 2b It is a schematic diagram of the threshold reversal characteristics of the conduction element provided according to some embodiments of the present application.

[0052] Figure 2a A schematic diagram of the structure of a bidirectional threshold switch (OTS) device 111 serving as the first conductive element 11a and the second conductive element 13a is shown. Figure 2aAs shown, the bidirectional threshold switch (OTS) device 111 includes a top electrode 111a and a bottom electrode 111b respectively connected to the word line (WL) 11b and the bit line (BL) 11c, and a chalcogenide compound material 111c located between the top electrode 111a and the bottom electrode 111b. A dielectric material or an insulating material 11d is also provided between the word line 11b and the bit line 11c to separate each bidirectional threshold switch (OTS) device 111. The chalcogenide compound material 111c of the bidirectional threshold switch (OTS) device 111 may include one or more phase change materials such as a material based on germanium-antimony-tellurium (Ge-Sb-Te, GST), one example of which may be Ge2Sb2Te5, or may be composed of a phase change material such as Ge-Te-As-Si. The top electrode 111a and the bottom electrode 111b are arranged opposite to each other, and their positions may be interchanged and overlapped with the outer bit line BL and the word line WL to form a 3D structure.

[0053] Figure 2b A graph showing the logarithmic current of the OTS device 111 versus the voltage applied across the two electrodes is shown. Starting from the high resistance cut-off state (reset) under low electric field, the current in the OTS device 111 increases with increasing voltage at a very small current value Ic until reaching the threshold voltage V at the fast return point 115. TH OTS After that, it will enter the low resistance conduction state (set state) and enter the holding voltage V H OTS .

[0054] After the fast return point 115, as long as a current higher than the holding current I H OTS When a current of 100V flows through the OTS device 111, a highly conductive dynamic ON state is maintained in the OTS device 111, and an ON current Io is provided. The transient highly conductive state is electronically originated and does not involve any phase change in the OTS device 111.

[0055] When the threshold voltage V of the OTS device 111 is exceeded TH OTS When the bidirectional threshold switch (OTS) device 111 is switched from the cut-off (OFF) state to the conduction (ON) state, and current flows through the bidirectional threshold switch (OTS) device 111. In the ON state, as the current flowing through the bidirectional threshold switch (OTS) device 111 increases, the voltage across the bidirectional threshold switch (OTS) device 111 remains close to the holding voltage (VH OTS ).

[0056] The OTS device 111 may be kept in the ON state until the current through the OTS device 111 is lower than the holding current (I H OTS ). H OTS ) value, the OTS device 111 may return to a high-resistance, non-conductive OFF state until V is exceeded again. TH OTS or I TH OTS Whenever guided, the bidirectional threshold switch (OTS) device 111 can be repeatedly and reversibly switched between the OFF state and the ON state, but it is not crystallized, which makes the OTS device 111 have a threshold flip characteristic and can be said to have a nonlinear characteristic of a negative resistance region in the on state beyond the threshold voltage.

[0057] Furthermore, as long as the current passing through the OTS device 111 is properly controlled, for example, by controlling the applied current from the first output line 11c, the OTS device 111 will recover from an unbalanced state (on state) to a balanced state (off state), and this process of recovery to a balanced state is called relaxation behavior or relaxation phenomenon. Therefore, when the applied current is lower than the holding current of the OTS device 111, according to the relaxation characteristics of the device, the OTS device 111 will repeatedly turn on and off, and generate a relaxation resonance behavior combined with current control, thereby outputting a pulse signal Pa from the first output line 11c. Therefore, the OTS device 111 as the first conduction element 11a and the second conduction element 13a can also be said to be a device with current-controllable relaxation behavior.

[0058] Therefore, if Figure 1 As shown, when a pulse voltage Vin is received from the first input line 11b / WL connected to the input end of the first transmission element 11a, a synaptic pulse signal Pa also having a pulse can be generated on the first output line 11c / BL connected to the output end of the first transmission element 11a.

[0059] It can be further understood that if a continuous signal Vin is received from the first input line 11b / WL connected to the input end of the first conduction element 11a, based on the relaxation phenomenon described above, when the current on the first output line 11c is appropriately controlled, a synaptic pulse signal Pa also having pulses can be generated on the first output line 11c / BL connected to the output end of the first conduction element 11a.

[0060] Specifically, Figure 3The waveform diagram showing the continuous signal Vin mentioned in the previous paragraph is converted into the pulse signal Pa. Figure 3 As shown, when the input signal Vin is a continuous wave, a synaptic pulse signal Pa can be output on the first output line as long as an appropriate current is applied to the first output line.

[0061] Through the relaxation characteristics of the OTS device 111, in addition to receiving pulse signals, it can also receive external continuous signals and convert them into pulse signals, which are then transmitted to the neuron unit 102 for charge accumulation and ignition operations.

[0062] When the OTS device 111 is used as the first and second conduction elements of the neuron, the number of switching times can reach 10E8 times, so the artificial neural network composed of the OTS device 111 will have good reliability. In addition, by using the OTS device 111 as both the first conduction element 11a and the second conduction element 13a, due to the same device structure, good integration and reliability can be achieved in process manufacturing.

[0063] Furthermore, in further research of the present application, it is understood that the threshold voltage Vth in the OTS device 111 is affected by many factors, such as changes in device structure, amplitude of applied pulses, pulse width, ramp rate and relaxation time. In further research, it is found that when the OTS device is composed of a phase change material such as Ge-Te-As-Si, the threshold voltage Vth of the OTS device 111 will be controlled by the polarity of the applied voltage and change, more specifically, the threshold voltage changes with the change of the polarity of the applied voltage. Therefore, the OTS device can be used independently for binary storage devices, so the OTS device 111 is called SOM memory (selector only memory) or SSM memory (self-selecting memory) in addition to being called a fast return selector or access element. Therefore, for the convenience of description, the bidirectional threshold switch (OTS) device is used here as a general term for the aforementioned various names, so the aforementioned various names are included in the OTS device described in the present application. .

[0064] Furthermore, it is understandable that although the OTS device 111 is used as an example of the first conductive element 11a and the second conductive element 13a, it should be understood that any device that can achieve current-controllable relaxation behavior and / or threshold flip characteristics can be used as the first conductive element 11a in the synaptic unit 101 and the second conductive element 13a in the neuron unit 102. Therefore, the present application uses conductive element as the general name of the OTS device to cover equivalent devices of various OTS devices, and the conductive element should be understood to be not limited to the OTS device 111 exemplified here.

[0065] In some embodiments, the accumulation circuit 13 further includes a capacitor 13b connected in parallel with the second conductive element 13a for accumulating the synaptic pulse signal Pa.

[0066] Specifically, Figure 1 As shown, at least one of the accumulation circuits 13 in the neuron unit 102 is composed of a second conduction element 13a and a capacitor 13b connected in parallel. When the synaptic pulse signal Pa output by the synaptic unit 101 is sent to the accumulation circuit 13 in the neuron unit 102, the synaptic pulse signal Pa will be input into the capacitor 13b and charge the membrane potential of the capacitor. Once the membrane potential reaches the threshold voltage of the second conduction element 13a (that is, the OTS device 111), the second conduction element 13a (that is, the OTS device 111) will be turned on, and after being turned on, the output voltage Vout of the accumulation circuit 13 will be quickly pulled up, and the neuron unit 102 will send a spike pulse voltage, that is, an accumulation signal, to the next synaptic layer or comparator, and reset the membrane potential of the capacitor 13b, and then the second conduction element 13a (that is, the OTS device 111) will be turned off, and the pulse will end at this time. It can be understood here that the single capacitor 13b will accumulate the pulses of the synaptic pulse signal Pa it receives and establish the membrane potential.

[0067] Through the front Figure 1 In the embodiment shown, due to the nonlinear characteristics of the negative resistance region of OTS111 and the current-controllable relaxation resonance behavior, a synaptic unit 101 based on the OTS device 111 is constructed, and based on the threshold flip characteristics of the OTS device 111 itself, a pulse neuron unit 102 based on the OTS device is constructed, which will realize a complete artificial neural network based on a single OTS device.

[0068] The following further describes further embodiments of the present application. Figure 4 , Figure 4 FIG. 1 is another schematic diagram of a circuit structure of a semiconductor device provided according to some embodiments of the present application. Figure 4As shown, in some embodiments, the semiconductor device 150 also includes a synaptic unit 151 and a neuron unit 102. However, the synaptic unit 151 includes a weighting circuit 101b in addition to the synaptic circuit 101a described above. The weighting circuit 101b includes at least one current setting circuit 12, and is used to provide at least one weighted current Iw to the output end of the at least one first conduction element 11a, so that the synaptic unit 151 responds to the at least one weighted current Iw and outputs the at least one synaptic pulse signal Pa.

[0069] It should be noted here that, for the sake of convenience, regardless of whether the weighting circuit 101b and the weighted current provided by the weighting circuit 101b are included or not, the synaptic pulse signal output by the synaptic unit 101 / 151 is labeled as Pa. Because the weighted current provided in this embodiment allows the pulse frequency of the synaptic pulse current Pa to be changed according to the size of the weighted current, but does not change its nature as a pulse signal, which will be further explained later.

[0070] In some embodiments, Figure 4 As shown, one of the current setting circuits 12 includes an adjustable current source 12a and a current mirror 12b. The adjustable current source 12a can be used to control the pulse frequency of the synaptic pulse signal Pa and the weighted magnitude of the input signal Vin.

[0071] Specifically, Figure 4 As shown, the adjustable current source 12a in the current setting circuit 12 can provide different constant current sources, such as 1 to 15 mA, and then provide a weighted current Iw to an output end of the synaptic circuit 101a through the current mirror circuit 12b to change the frequency of the pulse signal output by the synaptic circuit 101a.

[0072] Please refer to Figure 5 , Figure 5 1 is a waveform diagram of a pulse signal under different weightings according to some embodiments of the present application. For example, Figure 5 It shows that when the weighted current is given as 1, 10, and 13 current units, the synaptic pulse output signals Pa with different pulse frequencies are obtained.

[0073] Since the relaxation behavior of the OTS device itself can control the frequency of the output pulse signal Pa through current, the weighted weight of the input signal Vin can be controlled through the weighted current Iw, thereby realizing the learning characteristics. In other words, the size of the neural touch can be simulated, and the ideal neuron triggering time and intensity can be obtained by adjusting the size of the weighted current, thereby realizing the learning characteristics.

[0074] The following further describes further embodiments of the present application. Figure 6 , Figure 6 Another circuit structure diagram of a semiconductor device provided according to some embodiments of the present application is shown. Figure 6 As shown, the semiconductor device 200 provided according to some embodiments of the present application also includes a synaptic unit 201 and a neuron unit 202 . Figure 6 The semiconductor device 200 is shown with Figure 4 The semiconductor device 100 shown is different in that each circuit component is changed from one to multiple. That is, Figure 6 The synaptic unit 201 shown also includes a synaptic circuit 201a, but the synaptic circuit 201a includes a plurality of first conduction elements 11a, and the plurality of first conduction elements 11a form a conduction array, the conduction array includes at least one first input line 11b (also called word line WL) and at least one first output line 11c (also called bit line BL) connected to the plurality of first conduction elements 11a, the at least one first input line 11b (word line WL) receives the at least one input signal Vin, and the at least one first output line 11c (bit line BL) outputs the at least one synaptic pulse signal Pa.

[0075] in addition, Figure 6 The neuron unit 202 shown in the figure includes a plurality of accumulation circuits 13, each of which is composed of Figure 4 The accumulation circuit 13 shown is the same, that is, it includes a second conductive element 13a and a capacitor 13b connected in parallel. One accumulation circuit 13 accumulates one synaptic pulse signal Pa and outputs one accumulation signal Vout. Therefore, multiple accumulation circuits 13 can output multiple accumulation signals, such as the three accumulation signals Vout1, Vout2, and Vout3 shown in the figure.

[0076] Furthermore, Figure 6 The synaptic unit 201 shown is Figure 4 The synaptic unit 101 shown in FIG. 1 also includes a weighting circuit 201 b, but the weighting circuit 201 b includes a plurality of Figure 4 The current setting circuit 12 shown is the same as the current setting circuit 12, which is respectively connected to the multiple first output lines 11c (bit lines BL) and is used to provide the multiple weighted currents to the multiple first output lines 11c (bit lines BL) respectively, so that the multiple first output lines 11c (bit lines BL) respectively output the multiple synaptic pulse signals Pa.

[0077] However, it is understandable that Figure 6Although an example is shown in which a plurality of first conducting elements 11a arranged in an array, a plurality of word lines WL (first input lines 11b), a plurality of bit lines BL (first output lines 11c), a plurality of current setting circuits 12, and a plurality of accumulation circuits 13 are connected one by one, the semiconductor device 200 may also be designed in various variations without departing from the spirit of the present application. For example, the conducting array composed of a plurality of first conducting elements 11a may be composed of N rows x N columns (not shown) or a combination of N rows x 1 column (not shown) or 1 row x N columns (not shown), in addition to the composition of N rows x N columns shown in the figure, which is further explained as follows.

[0078] Take the array of N rows x 1 columns as an example, that is, the at least one first input line 11b (word line WL) includes N (N is greater than 2) first input lines 11b, which are used to receive multiple (N) input signals Vin_[1:n] respectively, and each input signal Vin_n represents a bit in a binary value. In this example, there will be a transmission array composed of multiple first transmission elements 11a arranged in a row, multiple word lines WL connecting the first transmission elements 11a in the row, and a bit line BL, and there is only one accumulation circuit 13 connected to the bit line BL. Through this example, it is represented that what is to be performed is to perform neuron synaptic sensing on an input Vin_[1:n] representing a binary value (that is, each Vin represents a bit), and then output an accumulation signal Vout through an accumulation circuit 13, and the output Vout at this time can represent the integrated sum neuron sensing of a binary value. If the weighting circuit is added, it means that the input of each bit representing the binary value is weighted before being sent to the accumulation circuit 13 for output, and if the weighting circuit is to be set together, only one current setting circuit 12 needs to be set to be connected to the one bit line BL. At this time, the same weighting value can be given to each of the multiple input signals Vin_n, but because the current setting circuit 12 can adjust the current, different weighted currents can also be given to the input signals Vin_[1:n] on each input line in turn.

[0079] Take the array of 1 row x N columns as an example, that is, the at least one first input line 11b (word line WL) includes one first input line 11b for receiving one input signal Vin, but the at least one first output line 11c includes multiple first output lines 11c, and each first output line 11c (bit line BL) is configured with an accumulation circuit 13. In this example, there will be a conductive array composed of multiple first conductive elements 11a arranged in a row, a word line WL connecting the first conductive elements 11a in one row, and multiple bit lines BL. Since there are multiple bit lines BL, there will be multiple accumulation circuits 13, each of which is connected to one bit line BL. Through this example, it is represented that the synaptic sensing of one input Vin is to be performed, but different relaxation phenomenon settings can be selectively given through different bit lines BL, and then the selected accumulation signals Vout are output respectively through multiple accumulation circuits 13. In this example, the weighting circuit can also be added, and a plurality of current setting circuits 12 can be set in the weighting circuit. Each current setting circuit 12 is connected to a bit line BL, and different weighted currents Iw are applied to each bit line BL. This means that an input signal Vin can be selectively weighted differently to generate synaptic pulse signals Pa with different weights, thereby giving different accumulation signals Vout.

[0080] From the above description, it can be understood that when the conduction array is composed of N rows x N columns of first conduction elements, it means that it can receive multiple input signals Vin_[1:n] and selectively give different relaxation phenomena or different weighted currents Iw through different bit lines BL to generate different synaptic pulse signals Pa, and then output different accumulation signals Vout respectively.

[0081] Furthermore, it can be understood that in an example where there are multiple accumulated signals Vout outputs, for example Figure 6 The accumulated signals Vout1, Vout2, and Vout3 can be output individually or summed up (not shown). These individual or summed accumulated signals can be sent to the synaptic unit (not shown) of the next layer or to the comparator (not shown) for direct comparison and output.

[0082] See below for further information. Figure 7 FIG. 1 is a schematic block diagram of a semiconductor device provided according to some embodiments of the present application. Figure 7 As shown, Figure 7The example shown can be regarded as equivalent to the case where the conduction array is NxN as described above, or it can be regarded as equivalent to the case where the conduction array is Nx1. That is, after the input signal Vin has multiple Vin[1:4] input into the synaptic unit 201, different weights W1, W2, W3, and W4 are respectively given in the synaptic unit 201 to generate multiple synaptic pulse signals Pa, and then these multiple synaptic pulse signals Pa are sent to the individual accumulation circuits 13 of the neuron unit 202, respectively integrated and ignited, and then one or more accumulation signals Vout can be output. It can be understood that in the aforementioned weighting actions W1~W4, there may be multiple bit lines BL (NxN case), each connected to a different current setting circuit 12, or there may be only one bit line BL (Nx1 case), but the input signal Vin[1:4] is weighted in turn as described above. In addition, Figure 7 Although the output setting shown in the figure outputs only one accumulated signal Vout for multiple input signals Vin[1:4], as mentioned above, Vout can be output individually or can be set to be summed and output together. This can be set according to actual needs and is not limited to the example shown in the figure.

[0083] In order to facilitate understanding of the relationship between the semiconductor device as an artificial neural network and the neural network shown in the present application, further Figure 8 A schematic diagram of mapping a semiconductor device and a graphical neural network according to some embodiments of the present application is shown in the figure to help understand the application of the semiconductor device disclosed in the present application to an artificial neural network. Figure 8 As shown, a neuron Ne of a neural network includes multiple synapses Sy, and a synapse Sy can be regarded as receiving an input Vin of the aforementioned semiconductor device 200. The aforementioned input signals Vin1 to Vin4 can be sent to multiple synapses of the same synaptic unit 201, or to different multiple synaptic units 201, and then sent to the neuron unit 202, and output an accumulation signal Vout. The accumulation signal Vout can be input to a new synapse Sy as an input signal of the next layer of neurons Ne.

[0084] To summarize the foregoing, the semiconductor device provided by the present application can provide an artificial neural network similar to a neural network, which not only has good reliability, but also can accept external continuous signals and convert them into pulse signals, thereby transmitting them to the neuron units for charge accumulation and ignition, and can control the weighted weight of the input signal by current, thereby realizing array learning characteristics, and further realizing a complete artificial neural network based on a single OTS device.

[0085] With respect to the aforementioned semiconductor device, the present application also provides a method for preparing a semiconductor device according to some embodiments of the present application. Fig. 9Flow chart of a method for preparing a semiconductor device according to some embodiments of the present application. Fig. 9 Please refer to the previous Figure 1 , Figure 4 ,and Figure 6 As shown in the circuit diagram, a method for manufacturing a semiconductor device 100 / 150 / 200 according to some embodiments of the present application includes:

[0086] In step S1, a synaptic unit 101 / 151 / 201 is formed, and the synaptic unit 101 / 151 / 201 includes a synaptic circuit 101a / 201a, and the synaptic circuit 101a / 201a includes at least one first conductive element 11a, and is used to receive at least one input signal Vin and output at least one synaptic pulse signal Pa; and

[0087] In step S2, a neuron unit 102 / 202 is formed, and the neuron unit 102 / 202 includes at least one accumulation circuit 13, and the accumulation circuit 13 includes a second transmission element 13a, and is used to receive the at least one synaptic pulse signal Pa and output an accumulation signal Vout;

[0088] The method further includes forming the first conductive element 11a and the second conductive element 13a by using a conductive element having a threshold flip characteristic.

[0089] Specifically, in some embodiments, the step of forming the first conduction element 11a and the second conduction element 13a includes forming the first conduction element 11a and the second conduction element 13a by a bidirectional threshold switch (OTS) device 111 having current-controllable relaxation behavior and the threshold flipping characteristic.

[0090] In some embodiments, the step of forming the neuron unit 102 / 202 further includes forming a capacitor 13 b connected in parallel with the second conductive element 13 a in the accumulation circuit 13 for accumulating the synaptic pulse signal Pa.

[0091] In some embodiments, the step of forming the synapse unit 151 / 201 also includes forming a weighting circuit 101b / 201b, and making the weighting circuit 101b / 201b include at least one current setting circuit 12, and is used to provide at least one weighted current Iw to the output end of the at least one first conduction element 11a, so that the synapse unit 151 / 201 responds to the at least one weighted current Iw and outputs the at least one synaptic pulse signal Pa.

[0092] In some embodiments, the step of forming the weighted circuit 101b / 201b also includes forming an adjustable current source 12a and a current mirror 12b to form the current setting circuit 12, and the adjustable current source 12a can be used to control the pulse frequency of the synaptic pulse signal Pa and the weighted size of the input signal Vin.

[0093] In some embodiments, the step of forming the synapse unit 201 also includes making the synapse circuit 201a include a conductive array composed of a plurality of the first conductive elements 11a, and at least one first input line 11b (word line WL) and at least one first output line 11c (bit line BL) connected to the plurality of first conductive elements 11a, and making the at least one first input line 11b receive the at least one input signal Vin, and making the at least one first output line 11c output the at least one synaptic pulse signal Pa.

[0094] In some embodiments, the step of forming the synaptic unit 201 further includes forming a plurality of the first input lines 11 b for respectively receiving a plurality of the input signals Vin, and each of the plurality of input signals Vin represents a bit of a binary value.

[0095] In some embodiments, the step of forming the synapse unit 201 also includes forming a plurality of the first output lines 11c, and making the plurality of first output lines 11c respectively output a plurality of the synaptic pulse signals Pa, and forming a plurality of the accumulation circuits 13 for respectively accumulating the plurality of synaptic pulse signals Pa and outputting a plurality of the accumulation signals Vout.

[0096] In some embodiments, the step of forming the synapse unit 201 also includes forming a plurality of the current setting circuits 12, and connecting them to the plurality of first output lines 11c respectively, and being used to provide a plurality of the weighted currents Iw to the plurality of first output lines 11c respectively, and making the plurality of first output lines 11c output a plurality of the synaptic pulse signals Pa respectively.

[0097] In some embodiments, the manufacturing method further includes forming a next-layer synaptic unit or an output comparator (not shown) for connecting the at least one accumulation signal Vout to an input terminal Vin of the next-layer synaptic unit or the output comparator.

[0098] Through the preparation method of the semiconductor device provided in some embodiments of the present application, it is possible to provide an artificial neural network similar to a neural network, which not only has good reliability, but can also accept external continuous signals and convert them into pulse signals, thereby transmitting them to the neuron units for charge accumulation and ignition, and can control the weight of the input signal by current, thereby realizing array learning characteristics, and further realizing a complete artificial neural network based on a single OTS device.

[0099] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A synaptic unit, comprising a synaptic circuit, wherein the synaptic circuit comprises at least one first conductive element, and is used to receive at least one input signal and output at least one synaptic pulse signal; and The neuron unit comprises at least one accumulation circuit, wherein the accumulation circuit comprises a second conduction element and is used to receive the synaptic pulse signal and output an accumulation signal; The first conduction element and the second conduction element are both conduction elements with threshold reversal characteristics.

2. The semiconductor device according to claim 1, wherein: The first conduction element and the second conduction element are both bidirectional threshold switch (OTS) devices, and the bidirectional threshold switch (OTS) device has current-controllable relaxation behavior and the threshold flip characteristic.

3. The semiconductor device according to claim 1, wherein: The accumulation circuit also includes a capacitor connected in parallel with the second conductive element, which is used to accumulate one of the synaptic pulse signals.

4. The semiconductor device according to claim 1, wherein: The synapse unit also includes a weighting circuit, which includes at least one current setting circuit and is used to provide at least one weighted current to the output end of the at least one first conduction element, so that the synapse unit outputs the at least one synaptic pulse signal in response to the at least one weighted current.

5. The semiconductor device according to claim 4, characterized in that The current setting circuit includes a current mirror and an adjustable current source. The adjustable current source can be used to control the pulse frequency of the synaptic pulse signal and the weighted size of the input signal.

6. The semiconductor device according to claim 4, characterized in that The synapse circuit includes a plurality of first conduction elements, and the plurality of first conduction elements form a conduction array, the conduction array includes at least one first input line and at least one first output line connected to the plurality of first conduction elements, the at least one first input line receives the at least one input signal, and the at least one first output line outputs the at least one synaptic pulse signal.

7. The semiconductor device according to claim 6, characterized in that The at least one first input line includes a plurality of first input lines for respectively receiving a plurality of input signals, and each of the input signals represents a bit in a binary value.

8. The semiconductor device according to claim 6, characterized in that The at least one first output line includes a plurality of the first output lines, and the plurality of first output lines respectively output a plurality of the synaptic pulse signals. The at least one accumulation circuit includes a plurality of the accumulation circuits for respectively accumulating the plurality of synaptic pulse signals and outputting a plurality of the accumulation signals.

9. The semiconductor device according to claim 8, characterized in that The at least one current setting circuit includes a plurality of current setting circuits, which are respectively connected to the plurality of first output lines and are used to respectively provide a plurality of weighted currents to the plurality of first output lines so that the plurality of first output lines respectively output a plurality of synaptic pulse signals.

10. The semiconductor device according to claim 1, wherein: The at least one accumulation signal is connected to an input terminal or an output comparator of a synaptic unit of a next layer.

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