Storage and calculation method of signed data based on storage unit array

Abstract

According to the technology, an 8-transistor SRAM (Static Random Access Memory) is adopted as a basic unit for weight storage and point multiplication operation, and an in-memory calculation macro circuit model based on a complement mapping method is designed based on the characteristic of bitwise operation of complement operation. Under the condition that symbol weight storage exists and the calculation scale is the same, the area overhead of the SRAM array is reduced, the complexity of the circuit is reduced, and the calculation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing technology, and in particular to a storage method for signed data based on a storage unit array and a corresponding computing method. Background Art

[0002] With the continuous advancement and popularization of technologies such as the Internet and the Internet of Things, we have entered the era of "big data". In this era, data is growing exponentially, and companies are in urgent need of a large amount of computing resources to process massive amounts of data. Data processing capabilities have become one of the core driving forces of corporate competitiveness, so the importance of computing power has become increasingly prominent, and computing devices with powerful computing power have become an indispensable infrastructure in scientific research, commercial applications, and national security.

[0003] Von Neumann architecture computers can no longer meet people's needs for data processing because their computing speed is limited by the "storage wall". Therefore, GPUs with better data parallel processing capabilities have gradually attracted attention from the industry. Although they alleviate the problems caused by the "storage wall", they still cannot overcome the limitations of the "storage wall". In order to solve the "storage wall" problem, architectures for new computing have received widespread attention. In-memory computing is an architecture that integrates computing and storage functions, and achieves fast data processing and analysis through in-memory computing technology. The advantages of in-memory computing architecture mainly include: in-memory computing architecture can greatly shorten data access and transmission paths by integrating computing and storage, reduce data delays in the computing process, and improve computing efficiency; in-memory computing architecture can support large-scale data parallel processing through the parallel computing characteristics of the array, thereby achieving high-throughput data processing.

[0004] In-memory computing technology uses its physical behavior and electrical characteristics to realize multiplication operations through the relationship between voltage, conductivity and current, and realizes multiplication and accumulation operations through integrated arrays. This effectively avoids the high-frequency data interaction between storage and computing, thereby breaking through the limitations of the "storage wall" and greatly improving the data processing capabilities. The in-memory computing circuit based on SRAM uses SRAM as the storage unit, and adds CMOS-based analog operation units or logic operation units on the basis of the storage unit to realize MAC operations through the array. Although the in-memory computing circuit represented by SRAM has a large area and is volatile, it has broad application prospects in the in-memory computing architecture due to its advantages such as fast access speed, low power consumption, no need for refresh, high reliability, mature technology, low commercial cost, and easy integration and design, and has been applied to a certain extent in the commercial world.

[0005] When performing vector matrix operations, conventional in-memory calculation methods decompose signed weights into positive and negative parts in order to realize the storage and calculation of signed weights, and map them in different SRAM groups, which consumes nearly double the SRAM resources and increases the area overhead of the SRAM array. At the same time, additional functional circuits such as inverters, differential circuits or subtractors are required to assist the array in realizing vector matrix operations with signed weights, which increases the complexity of the circuit. Compared with the unsigned weight calculation method, not only does it use double the SRAM resources, but it also increases the calculation steps, reducing the calculation efficiency of the in-memory calculation macro.

[0006] In the prior art, the in-memory computing macro based on SRAM mainly realizes efficient multiplication and accumulation operations through the storage characteristics and parallel computing characteristics of the SRAM array. The in-memory computing macro stores the weights of the neural network through the SRAM array, avoiding the movement of weight data, greatly shortening the data access and transmission path, reducing the delay of data in the calculation process, and improving the computing efficiency and performance. The SRAM array realizes parallel acceleration of multiplication and accumulation operations through Ohm's law and Kirchhoff's current law, thereby realizing high-throughput data processing. However, when performing multiplication and accumulation operations in neural network calculations, the weights are positive and negative, and the SRAM unit can only store and calculate unsigned numbers, so it is necessary to design the storage and calculation scheme of the SRAM array to ensure that signed multiplication and accumulation operations can be performed. Among them, there are three common processing schemes:

[0007] (1) Reverse voltage method

[0008] Reverse voltage method Figure 1 As shown, a signed weight is stored in two adjacent storage cells in the upper and lower rows. When storing signed weights, the value of the weight is judged. If it is a positive number, the positive part will be written to the upper storage cell, and the lower storage cell will be written to zero. On the contrary, if it is a negative number, the negative part will be written to the lower storage cell, and the upper storage cell will be written to zero. In this way, the writing of signed weights can be completed. During the calculation process, the input end converts the input signal into two voltage signals with opposite polarities, which are applied to the upper and lower rows of storage cells respectively. According to Kirchhoff's current theorem, the multiplication and accumulation operations of signed numbers are realized by controlling the direction of the current. This scheme not only uses twice the storage resources when storing weights, but also introduces a large number of inverters, resulting in a large waste of resources and increasing the time of signal transmission.

[0009] (2) Differential current method

[0010] The differential current method is similar to the reverse voltage method. The calculation scheme is as follows: Figure 2As shown in the figure, the storage of signed numbers is realized by the left and right columns of storage units. The storage unit on the left is responsible for storing positive numbers with signed weights, and the storage unit on the right is responsible for storing negative numbers with signed weights. During the in-memory calculation macro calculation process, the differential circuit will subtract the currents of the positive and negative columns to obtain the operation result of the signed weight. This scheme is the same as the reverse voltage method, requiring double the storage resources and introducing a large number of differential circuits, resulting in waste of resources and output delays.

[0011] (3) Array subtraction method

[0012] The calculation scheme of array subtraction method is as follows Figure 3 As shown, unlike the differential current method and the reverse voltage method which use two columns or two rows to store signed numbers, the array subtraction method uses the same storage unit of two identical arrays to store signed numbers. The array subtraction method divides the two arrays into a positive array and a negative array. The positive array stores positive numbers with signed weights, while the negative array stores negative numbers with signed weights. During the calculation process, the input data will be operated on the positive array and the negative array respectively. Subsequently, the positive and negative results are processed by the analog-to-digital converter and then subtracted by the subtractor to obtain the final signed number calculation result. Compared with the first two methods, this method also requires double the storage resources and introduces a subtractor, resulting in resource waste and output delay.

[0013] The above three methods all solve the storage and calculation of signed weights. Although each has its own strengths, they all require double storage resources and introduce other functional circuits, resulting in waste of resources and output delay. The present invention optimizes the in-memory calculation method by means of the characteristics of bitwise operation during complement operation, uses an 8T-SRAM array to store quantized weights, and then combines the array peripheral auxiliary calculation circuit digital to analog converter (DAC), current to voltage circuit, analog to digital converter (ADC) and shift weighting unit (Shift & Add), so as to realize efficient in-memory calculation of signed weights. Summary of the invention

[0014] In view of the problems existing in the prior art, the present invention provides a method for storing signed data based on a storage cell array, characterized in that each row or column of the storage cell array stores the signed data A in the following manner: int :

[0015] A int =-2 N-1 ×A N-1 +…2 1 ×A1+2 0 ×A0,

[0016] Wherein, N is the number of bits of binary signed data that the storage cell array can store, A0-A N-1 Represents the decimal signed data A int The value of each bit when converted into the corresponding binary complement, and A N-1 At the same time, it can represent the signed data A int is positive or negative, when A N-1 When A is equal to 0, int is a positive number, when A N-1 When A is equal to 1, int is a negative number.

[0017] Preferably, the memory cell array is a volatile memory cell array or a non-volatile memory cell array.

[0018] Preferably, each memory cell of the memory cell array adopts an 8T-SRAM memory calculation unit, and the calculation result of the 8T-SRAM memory calculation unit is output in the form of current. The current is collected in the memory cell array by sharing the same bit line RBL, thereby realizing the accumulation operation.

[0019] The present invention also provides a storage and calculation method for signed data based on the above storage method, wherein the storage and calculation of signed data are used for multiplication and accumulation operations, vector dot multiplication operations, vector matrix multiplication operations, and neural network type calculations.

[0020] The present invention also provides an in-memory computing method based on the above storage method, the method comprising the following steps:

[0021] Writing step: the storage cell array writes weights row by row or column by column through a weight writing port, wherein the weights are signed data;

[0022] Digital-to-analog conversion step: The digital-to-analog converter is used to receive the data sent by the pooling module in the previous layer of the network, complete the conversion of the data from digital signals to analog signals, and apply it to the data input end of the storage cell array in the form of voltage, and perform multiplication and accumulation operations with the stored signed weights. Finally, the storage cell array outputs the calculation results by column or row;

[0023] Voltage conversion step: a current-to-voltage circuit connects the output of the storage cell array and the input of the analog-to-digital converter to convert the output current into a voltage amplitude of corresponding magnitude according to a corresponding ratio;

[0024] Analog-to-digital conversion step: an analog-to-digital converter is connected to the output of the current-to-voltage circuit, converts the pulse voltage output by the current-to-voltage circuit into a digital signal of corresponding magnitude according to the voltage amplitude, and outputs it to the shift weighting unit;

[0025] Weighting step: The shift weighting unit receives the digital signal output by the analog-to-digital converter, and performs shift weighting processing on the digital signals output by all analog-to-digital converters according to the weights of each column or row, so as to obtain the final result of the vector matrix operation in the neural network calculation.

[0026] Compared with the prior art solutions, the present invention has at least the following beneficial effects:

[0027] 1) The technology of the present invention uses 8-transistor SRAM as the basic unit for storing weights and dot multiplication operations. Based on the characteristics of bitwise operations during complement operations, a macro circuit model for in-memory calculation based on the complement mapping method is designed. Under the conditions of the same signed weight storage and calculation scale, the area overhead of the SRAM array is reduced, the complexity of the circuit is reduced, and the calculation efficiency is improved;

[0028] 2) When the signed weights are mapped on the SRAM array, the present invention reduces the SRAM array required for mapping the signed weights and reduces the area overhead of the SRAM array;

[0029] 3) Compared with the conventional signed weight in-memory calculation method, the present invention simplifies the calculation steps of the signed number in the in-memory calculation macro and reduces the circuit complexity;

[0030] 4) When performing signed number calculations of the same scale weights, the present invention can implement the signed weight calculations using nearly 1 / 2 of the SRAM resources, thereby improving the calculation efficiency of the in-memory calculation macro. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the reverse voltage method calculation of signed numbers in the prior art;

[0032] Figure 2 It is a schematic diagram of differential current method calculation of signed numbers in the prior art;

[0033] Figure 3 It is a signed number array subtraction calculation scheme in the prior art;

[0034] Figure 4 It is an 8-transistor SRAM storage and calculation unit structure of the present invention;

[0035] Figure 5 It is a structural diagram of a 32×8 SRAM array of the present invention;

[0036] Figure 6 It is a mapping diagram of the vector dot multiplication operation on the SRAM array of the present invention;

[0037] Figure 7 It is a diagram showing the two's complement representation of an N-bit binary number of the present invention;

[0038] Figure 8 It is a schematic diagram of in-memory computing macro calculation based on the complement mapping method of the present invention;

[0039] Fig. 9 (a) In-memory computing macro based on the complement mapping method: (a) Overall block diagram of the in-memory computing macro;

[0040] Fig. 9 (b) Overall flow chart of the in-memory computation macro.

[0041] The present invention is further described in detail below. However, the following examples are only simplified examples of the present invention and do not represent or limit the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the claims. Specific embodiments

[0042] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0043] In-memory computing technology is the key to in-memory computing neural network accelerators. In-memory computing integrates computing and storage functions to achieve fast data processing and analysis, reduces data access and transmission, and improves computing efficiency. It is a new architecture suitable for neural network intensive computing. With the development of technology, the in-memory computing architecture has increasingly higher requirements for the access speed, power consumption, reliability and commercial cost of storage units. SRAM is compatible with the in-memory computing architecture due to its advantages such as fast access speed, low power consumption, no need to refresh, high reliability, mature technology, low commercial cost, easy integration and design. Therefore, the in-memory computing architecture based on SRAM has also become an important research direction. Figure 4The figure shows the structure of the 8T-SRAM storage unit. The writing method of the 8T-SRAM storage unit is the same as that of the traditional 6T-SRAM storage unit. However, the reading method of the 8T-SRAM storage unit is to connect the Q point of the traditional 6T-SRAM to the Q point of the dot multiplication function calculation circuit to realize the reading of the stored data. When performing the reading operation of the SRAM storage unit, according to the conditions of the dot multiplication circuit calculation, only when the data in the SRAM storage unit is "1" and the read enable signal RWL is high, the two transistors in the dot multiplication circuit can form a path to realize the dot multiplication operation of the input voltage and the stored data. If the data in the SRAM storage unit is "0", or the read enable signal RWL is low, M7 and M8 in the dot multiplication circuit will not form a path, and the current flowing through RBL can be ignored. Due to the read-write separation characteristics of the 8T-SRAM storage unit, it will not cause feedback to the storage node when reading data, thereby improving the stability of the stored data. In addition, the calculation results of the 8T-SRAM storage and calculation unit are output in the form of current. In the SRAM array, the current can be collected by sharing the same bit line RBL to achieve accumulation operation. By performing multiplication and accumulation operations on the entire column of SRAM storage and calculation units and the shared bit line RBL, the entire array can achieve vector matrix operations.

[0044] like Figure 5 As shown, a 32×8 SRAM array of the present invention can store 8 1-bit weights in each row, and a total of 32 rows can be stored. The read and write of each row of SRAM storage and calculation units are controlled by the same set of WL and RWL, and the calculation input port of each row of SRAM storage and calculation units is the same SL. Each column of SRAM storage and calculation units is also written through the same BL and BLB. According to Kirchhoff's current law, each column of SRAM storage and calculation units realizes current collection by outputting a shared RBL, thereby realizing the addition operation in the multiplication and accumulation operation. The 32×8 SRAM array can realize the multiplication and accumulation operation of at most 1 group of inputs and 8 groups of binary weights, and each group of data does not exceed 32, that is, the maximum multiplication of a 32-dimensional vector and a 32×8 matrix can be realized, and the output 8-dimensional row vector flows out in the form of current through the RBL. When the SRAM array stores multi-valued weights, since there are only 8 SRAM storage and calculation units in each row, a maximum of 8-bit weights can be stored, and a maximum of 32 can be stored. During the calculation process, the SRAM array can only perform multiplication and accumulation operations on one group of multi-valued weights, and each group does not exceed 32, that is, the maximum point multiplication operation that can be realized is a group of 32-dimensional vectors. The calculation result of the multi-valued weights needs to be shifted and weighted by the current output by each column of RBL.

[0045] After the SRAM array is built, the vector matrix multiplication in the neural network calculation needs to be mapped to the SRAM array model for calculation. However, since the neural network weights of the present invention are all 8 bits, and each SRAM array can only map one column of weights, multiple columns of weights require multiple arrays to be implemented together. The mapping of the vector dot multiplication operation on the SRAM array is as follows: Figure 6 As shown in the figure, the input row vector needs to be transposed into a column vector and then applied to the input of the SRAM array in the form of an analog voltage. Each element in each column of the weight vector is written into the SRAM array row by row, so that the output of each array is the product of the input vector and the weight vector of the column. Multiple such arrays are combined to realize the function of vector-matrix multiplication.

[0046] When implementing the three signed number in-memory storage and operation schemes mentioned above through the SRAM array, subtraction and weighted addition operations are required. Weighted addition can be decomposed into two operations: shift and addition. When performing subtraction and weighted addition operations, the existing calculation methods, regardless of whether subtraction or shift addition is performed first, divide the weights into two unsigned numbers for operation, and then process the operation results to obtain the signed number operation results. In response to this problem, this paper proposes an optimization method for the signed number storage calculation scheme of the in-memory calculation array based on the calculation characteristics of the complement code. Starting from the characteristics of the complement code, this paper directly involves the weights in the form of signed numbers in the calculation, avoiding the process of decomposing the weights into two unsigned numbers and participating in the calculation. The representation of an N-bit binary complement code is as follows. Figure 7 shown.

[0047] In the two's complement code, each binary value has a different weight. In the process of converting the two's complement code to a decimal real number, each number represented by the two's complement code must be multiplied by a weight and then added to get the actual value. The formula for converting an N-bit two's complement code A to a decimal real number is:

[0048] A int =-2 N-1 ×A N-1 +…2 1 ×A1+2 0 ×A0 (1)

[0049] Wherein, N is the number of bits of binary signed data that the storage cell array can store, A0-A N-1 Represents the decimal signed data A int The value of each bit when converted into the corresponding binary complement, and A N-1 At the same time, it can represent the signed data A int is positive or negative, when A N-1 When A is equal to 0, int is a positive number, when AN-1 When A is equal to 1, int is a negative number.

[0050] From the representation of the binary complement and the conversion process to the decimal real number, it can be seen that the conversion from the binary complement to the decimal real number is realized through shifting and addition and subtraction operations. Then the conversion from the binary complement to the decimal real number can also be seen as a process of multiplying a "+1" by each bit of a binary signed number, and then converting it into a decimal real number by shifting and adding and subtracting. Then the multiplication of a positive number A and a 2's complement B can be expressed as formula (2):

[0051] A×B=-2 N-1 ×B N-1 ×A+…+2 1 ×B1×A+2 0 ×B0×A (2)

[0052] Then the operation method of a positive number and a 2's complement code is expanded to the dot product operation between a set of positive vectors A and a set of 2's complement code vectors B. The dot product operation of vector A and vector B is expanded into formula (3):

[0053] A×B=A0×B0+A1×B1+…+A n-1 ×B n-1 (3)

[0054] Expand each element of the vector B in the above formula into a two's complement representation, and the formula after the dot product operation is expanded is (4):

[0055]

[0056] Simplifying the above formula, we get:

[0057]

[0058] According to the simplified formula (5), it can be concluded that the dot multiplication operation of a positive vector and a two's complement vector can be decomposed into a vector-matrix operation of a positive vector and a two's complement matrix. First, the positive vector is dot-multiplied with the column vector composed of the same binary bits in the two's complement matrix, and then the dot multiplication results on each bit are shifted and added according to the weights, and finally the dot multiplication operation of the positive vector and the signed vector is obtained. Each SRAM storage unit can perform a multiplication of a positive number and a binary value, so the multiplication of a positive number and an N-bit two's complement code can be implemented using N SRAM storage unit circuits. If an n-dimensional positive vector is dot-multiplied with an N-bit n-dimensional two's complement code vector, according to the resolved formula (5), an n-row and N-column SRAM array can be used to implement the vector multiplication operation. If each row of the array has N SRAM storage and calculation units, it can complete the multiplication of a positive number and an N-bit 2's complement code, and n rows can complete the multiplication of n positive numbers and N-bit 2's complement code. Each column of the array is connected through the corresponding bit line, and the product of the bit vector of the corresponding bit in the complement matrix and the positive number vector is added, and finally the weighted addition and subtraction operation is realized by shift addition. This paper optimizes the storage and calculation scheme of the in-memory calculation macro by deriving the complement operation, and stores the signed weights in the SRAM in-memory calculation array in the form of complement code, and then performs vector dot multiplication operation through the SRAM array, and finally shifts and adds the output current of each column according to the corresponding bit of the complement code to obtain the output result. Taking 8-bit signed weights as an example, the in-memory calculation macro signed weight storage calculation method based on the complement mapping method proposed in this paper has improved the calculation efficiency by 0.75 times and reduced the area consumption by 42.9% compared with the previous use of double resources to realize signed weight operations. The schematic diagram of the in-memory calculation macro calculation based on the complement mapping method proposed in this paper is shown in the figure. Figure 8 shown.

[0059] like Fig. 9 (a) shows the overall architecture of the in-memory computing macro based on the complement mapping method. The in-memory computing macro in this design includes a digital-to-analog converter, an SRAM array, a current-to-voltage circuit, an analog-to-digital converter, and a shift weighting unit. The workflow diagram of the in-memory computing macro is shown in Fig. 9 (b) as shown.

[0060] (1) Digital-to-analog converter: It is used to receive the data sent by the pooling module in the previous layer of the network, complete the conversion of the data from digital signal to analog signal, and apply it to the data input end of the array in the form of voltage; this module is only connected to the data input port of the array, and the number of digital-to-analog converters depends on the actual number of rows of the array.

[0061] (2) SRAM array: It is built with the basic storage and computing unit 8T-SRAM, which realizes the most basic vector matrix operations in neural network calculations. The size of the array depends not only on the size of the convolution kernel, but also on the number of convolution kernels. The weights are written row by row through the weight write port, and then multiplied and added with the analog voltage input by the digital-to-analog converter, and finally the calculation results are output by column.

[0062] (3) Current-to-voltage circuit: Connect the output of the SRAM array to the input of the analog-to-digital converter, convert the current output by each column of the array into a voltage amplitude of corresponding magnitude according to the corresponding ratio, and complete the current-to-voltage conversion.

[0063] (4) Analog-to-digital converter: connects the output of the current-to-voltage circuit to the input of the shift-weighted unit, converts the pulse voltage output by the current-to-voltage circuit into a digital signal of corresponding size according to the voltage amplitude, and outputs it to the shift-weighted unit.

[0064] (5) Shift weighting unit: receives the digital signal output by the analog-to-digital converter and performs shift weighting processing on the digital signals output by all analog-to-digital converters in the in-memory calculation macro according to the weight of each column, thereby obtaining the final result of the vector matrix operation in the neural network calculation.

[0065] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0066] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0067] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A method for storing signed data based on a storage cell array, characterized in that: Each row or column of the memory cell array stores the signed data A in the following manner: int : A int =-2 N-1 ×A N-1 +…2 1 ×A1+2 0 ×A0, Wherein, N is the number of bits of binary signed data that the storage cell array can store, A0-A N-1 Represents the decimal signed data A int The value of each bit when converted into the corresponding binary complement, and A N-1 At the same time, it can represent the signed data A int is positive or negative, when A N-1 When A is equal to 0, int is a positive number, when A N-1 When A is equal to 1, int is a negative number.

2. The storage method according to claim 1, characterized in that: The memory cell array is a volatile memory cell array or a nonvolatile memory cell array.

3. The storage method according to claim 2, characterized in that: Each memory cell of the memory cell array adopts an 8T-SRAM memory calculation unit, and the calculation result of the 8T-SRAM memory calculation unit is output in the form of current. The current is collected in the memory cell array by sharing the same bit line RBL, thereby realizing the accumulation operation.

4. A method for storing and calculating signed data based on any one of the storage methods in claims 1 to 3, characterized in that: The storage and calculation of the signed data are used for multiplication and accumulation operations, vector dot multiplication operations and vector matrix multiplication operations as well as neural network type calculations.

5. An in-memory computing method for signed data stored in any storage method according to any one of claims 1 to 3, characterized in that: The method comprises the following steps: Writing step: the storage cell array writes weights row by row or column by column through a weight writing port, wherein the weights are signed data; Digital-to-analog conversion step: The digital-to-analog converter is used to receive the data sent by the pooling module in the previous layer of the network, complete the conversion of the data from digital signals to analog signals, and apply it to the data input end of the storage cell array in the form of voltage, and perform multiplication and accumulation operations with the stored signed weights. Finally, the storage cell array outputs the calculation results by column or row; Voltage conversion step: a current-to-voltage circuit connects the output of the storage cell array and the input of the analog-to-digital converter to convert the output current into a voltage amplitude of corresponding magnitude according to a corresponding ratio; Analog-to-digital conversion step: an analog-to-digital converter is connected to the output of the current-to-voltage circuit, converts the pulse voltage output by the current-to-voltage circuit into a digital signal of corresponding magnitude according to the voltage amplitude, and outputs it to the shift weighting unit; Weighting step: The shift weighting unit receives the digital signal output by the analog-to-digital converter, and performs shift weighting processing on the digital signals output by all analog-to-digital converters according to the weights of each column or row, so as to obtain the final result of the vector matrix operation in the neural network calculation.

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