Shielding slot type grid metal oxide semi-field effect transistor and grid manufacturing method thereof
By adding a buffer layer to the shielded groove trench process (SGT), the component damage caused by defects in the process is solved, and the process yield is improved and the cost is reduced.
Patent Information
- Application Number
- CN202410002977.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-31
- Filing Date
- 2024-01-02
- Publication Date
- 2025-02-18
AI Technical Summary
The actual shielded groove trench process (SGT) often suffers from defects, resulting in component damage, causing process difficulties for metal oxide semiconductors and reduced product yield.
By adding a buffer layer in the process, the thickness of the polysilicon layer to be etched is increased, thereby avoiding gate polysilicon thickness defects caused by excessive etching during subsequent back-etching.
The risk of breaking down the gate polysilicon during the contact window process is effectively avoided, the process yield is increased, and the cost of the process is substantially reduced.
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Figure CN119480629A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor process technology, and in particular to a shielded trench gate metal oxide semi-field effect transistor and a gate manufacturing method thereof. Background Art
[0002] Power Metal Oxide Semiconductor Field Effect Transistor, generally referred to as Power MOSFET, is a field effect transistor that can be widely used in analog circuits and digital circuits. It has become the mainstream of power devices, and it occupies a dominant position in the market. It is often used in many electronic power applications. Power Metal Oxide Semiconductor Field Effect Transistor has a very low on-resistance, and because the gate input impedance of the Power Metal Oxide Semiconductor Field Effect Transistor is very large, the power dissipation at the input end is quite small. Furthermore, compared with the Power Bipolar Transistor, the Power Metal Oxide Semiconductor Field Effect Transistor has only a single carrier and does not have the disadvantage of minority carrier storage, so it also has the advantage of very fast switching speed. Therefore, the Power Metal Oxide Semiconductor Field Effect Transistor has become the mainstream of high-frequency and low-voltage (<200V) power components.
[0003] Compared with ordinary trench metal oxide semiconductor field effect transistors, shielded gate trench (SGT) process metal oxide semiconductor field effect transistors are simpler, have lower switching losses, narrow Miller platform, and low internal resistance. Specifically, the SGT process is 3-5 times deeper than the ordinary trench process, and a polysilicon electrode, namely the shielding electrode or coupling electrode, is added under the gate. The shielding electrode is connected to the source electrode, which realizes the function of shielding the gate and the drift region, reduces the Miller capacitance, and speeds up the switching speed of the component. At the same time, it realizes the charge coupling effect, reduces the critical electric field strength of the drift region, reduces the on-resistance of the component, and can reduce the switching loss. Compared with ordinary trench metal oxide semiconductor field effect transistors, the internal resistance of SGT process metal oxide semiconductor field effect transistors is more than 2 times lower.
[0004] However, actual SGT processes often have defects that lead to component damage, causing difficulties in the metal oxide semiconductor process and reduced product yield. Summary of the invention
[0005] The present application provides a shielded trench gate metal oxide half field effect transistor and a gate manufacturing method thereof and the shielded trench gate metal oxide half field effect transistor manufactured thereby, so as to correct defects generated in a process.
[0006] An embodiment of the present application provides a method for manufacturing the gate of a shielded trench-type gate metal oxide semi-field effect transistor. The method for manufacturing the shielded trench-type gate metal oxide semi-field effect transistor includes: providing a drain substrate having an epitaxial layer; etching a trench; configuring a first oxide layer to insulate the inner wall of the trench; depositing a first polysilicon; performing an etching process to form a source polysilicon; configuring a gate oxide layer to cover the source polysilicon; depositing a second polysilicon; configuring a buffer layer on the second polysilicon; etching the buffer layer; and etching back the gate polysilicon to retain only the second polysilicon in the trench as a gate polysilicon.
[0007] According to the preferred embodiment of the present application, the method for manufacturing the gate of the shielded trench gate metal oxide semi-field effect transistor, wherein the buffer layer is arranged on the second polysilicon, including: coating the surface with a photoresist; and performing an exposure process to cure the photoresist. In another preferred embodiment, the buffer layer is arranged on the second polysilicon, including: performing a spin-on glass (Spin On Glass, SOG) on the surface; and performing a heat treatment to remove the solution.
[0008] According to the preferred embodiment of the present application, the method for manufacturing the gate of the shielded trench gate metal oxide half field effect transistor further includes: configuring a dielectric layer; and configuring a contact window (contact) on the dielectric layer to electrically connect the gate polysilicon.
[0009] According to the gate manufacturing method of the shielded groove gate metal oxide semi-field effect transistor described in the preferred embodiment of the present application, the gate polysilicon is etched back to retain only the gate polysilicon in the groove, including: performing a dry etching to remove the second polysilicon on the surface and retaining the second polysilicon in the groove as the gate polysilicon.
[0010] According to the preferred embodiment of the present application, a method for manufacturing the gate of a shielded trench-gate metal oxide semi-field effect transistor is described, wherein an etching process is performed to form source polysilicon, and further includes: etching the first polysilicon to expose a portion of the trench; etching the first oxide layer to remove the first oxide layer on the surface of the epitaxial layer and remove a portion of the first oxide layer in the trench, so that the first oxide layer is lower than or equal to the source polysilicon in the trench.
[0011] The embodiment of the present application further provides a shielded trench gate metal oxide semi-field effect transistor, which includes a drain substrate, an epitaxial layer and a trench. The epitaxial layer is arranged on the drain substrate. The inner wall of the trench is covered with a first oxide layer, and a source polysilicon is arranged in the trench, a gate oxide layer is arranged on the source polysilicon, and a gate polysilicon is arranged on the gate oxide layer. The process of the above-mentioned gate polysilicon includes: performing a second polysilicon deposition process on the gate oxide layer; configuring a buffer layer on the second polysilicon; etching the buffer layer; and etching back the gate polysilicon, retaining only the second polysilicon in the trench as the gate polysilicon.
[0012] According to the shielded trench gate metal oxide half field effect transistor described in the preferred embodiment of the present application, a P-type body region and an N+ doped region are further included on one side of the trench, wherein the N+ doped region is arranged adjacent to the trench. In a preferred embodiment, a P+ doped region is further included, which is arranged in the P-type body region. In another preferred embodiment, the shielded trench gate metal oxide half field effect transistor further includes a source metal layer.
[0013] In summary, the embodiment of the present application increases the thickness of the polysilicon layer to be etched by adding a buffer layer in the process, thereby avoiding the thickness defect of the gate polysilicon caused by over-etching in the subsequent back-etching process. This avoids the risk of breaking through the gate polysilicon during the contact process, increases the process yield, and substantially reduces the process cost.
[0014] In order to further understand the technology, means and effects of the present application, reference may be made to the following detailed description and drawings, so that the purpose, features and concepts of the present application can be thoroughly and specifically understood. However, the following detailed description and drawings are only used for reference and explanation of the implementation of the present application, and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings are provided to enable a person with ordinary knowledge in the technical field to which the present application belongs to further understand the present application, and are incorporated into and constitute a part of the specification of the present application. The accompanying drawings illustrate exemplary embodiments of the present application, and are used together with the specification of the present application to explain the principles of the present application.
[0016] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to an embodiment of the present application.
[0017] Figure 2AFIG. 1 is a schematic diagram of step S101 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0018] Figure 2B FIG. 1 is a schematic diagram of step S102 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0019] Figure 2C FIG. 1 is a schematic diagram of step S103 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0020] Figure 2D FIG. 1 is a schematic diagram of step S104 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0021] Figure 2E FIG. 1 is a schematic diagram of step S105 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0022] Figure 2F FIG. 1 is a schematic diagram of step S106 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0023] Figure 2G FIG. 1 is a schematic diagram of step S107 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0024] Figure 3 FIG. 1 is a flow chart of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to an embodiment of the present application.
[0025] Figure 4A FIG. 1 is a schematic diagram of step S301 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0026] Figure 4B FIG. 1 is a schematic diagram of step S302 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0027] Figure 4CFIG. 1 is a schematic diagram of step S303 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0028] Figure 4D FIG. 1 is a schematic diagram of step S304 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0029] Figure 4E FIG. 1 is a schematic diagram of step S305 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0030] Figure 4F FIG. 1 is a schematic diagram of step S306 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0031] Figure 4G FIG. 1 is a schematic diagram of step S307 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0032] Figure 4H FIG. 1 is a schematic diagram of step S308 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0033] Fig. 4I FIG. 1 is a schematic diagram of step S309 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0034] Figure 4J FIG. 1 is a schematic diagram of step S310 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0035] Figure 4K FIG. 1 is a schematic diagram of step S310 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0036] Figure 5 FIG. 1 is a flow chart showing the sub-steps of step S305 of a method for manufacturing a gate of a shielded trench-gate metal oxide semiconductor field effect transistor according to a preferred embodiment of the present application.
[0037] Figure 6FIG. 1 is a schematic diagram of step S501 of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to a preferred embodiment of the present application.
[0038] Figure 7 Another flowchart of sub-steps of step S308 of the method for manufacturing a gate of a shielded trench-gate metal oxide semiconductor field effect transistor according to a preferred embodiment of the present application is shown.
[0039] Figure 8 FIG. 1 is a flow chart showing the sub-steps of step S308 of a method for manufacturing a gate of a shielded trench-gate metal oxide semiconductor field effect transistor according to a preferred embodiment of the present application.
[0040] Fig.9A FIG. 1 is a cross-sectional view of a shielded trench gate metal oxide semi-field effect transistor according to a preferred embodiment of the present application.
[0041] Fig. 9B Another cross-sectional view of a shielded trench gate metal oxide half field effect transistor according to a preferred embodiment of the present application is shown. DETAILED DESCRIPTION
[0042] Reference will now be made in detail to the exemplary embodiments of the present application, which are illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and the specification to refer to the same or similar components. In addition, the exemplary embodiments are only one of the implementation methods of the design concept of the present application, and the following examples are not intended to limit the present application.
[0043] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a gate of a shielded trench gate metal oxide semiconductor field effect transistor (SGTMOSFET) according to an embodiment of the present invention. Figure 1 In this embodiment, the gate manufacturing method of the shielded trench gate metal oxide semi-field effect transistor includes the following steps:
[0044] Step S101: Etching a groove 20. Figure 2A shown.
[0045] Step S102: forming a first oxide layer 201 in the trench 20. Figure 2B The first oxide layer 201 is mainly used to insulate the inner wall of the trench 20. The first oxide layer 201 is specifically a thermal oxide layer or a deposited oxide layer, but is not limited to these two types.
[0046] Step S103: depositing a first polysilicon 202a. Figure 2C shown.
[0047] Step S104: Etching is performed to form a source polysilicon 202b. Figure 2D As shown, the etching process removes the first oxide layer 201 and the first polysilicon 202a from the surface, and the etching method can be etch back.
[0048] Step S105: forming a gate oxide layer 203. Figure 2E Generally, the thickness of the gate oxide layer 203 is lower than that of the first oxide layer 201. The gate oxide layer 203 is generally formed by thermal oxidation or thermal oxidation plus deposition.
[0049] Step S106: deposit a second polysilicon 204a. Figure 2F shown.
[0050] Step S107: Perform etching back to obtain the gate polysilicon 204b in the trench. Figure 2G shown.
[0051] In the above embodiment, since steps S106 and S107 will cause surface depression during back etching, resulting in insufficient center thickness of the gate polysilicon 204b, there is a certain probability that the gate polysilicon 204b will be penetrated during the subsequent contact window configuration process, thereby causing a short circuit between the gate polysilicon 204b and the source polysilicon 202b.
[0052] In order to solve the above problems, the present application further provides a method for manufacturing a gate of a shielded trench gate metal oxide half field effect transistor. Figure 3 The flowchart of the method for manufacturing the gate of the shielded trench gate metal oxide semi-field effect transistor according to a preferred embodiment of the present application is shown. Figure 3 In this embodiment, the gate manufacturing method of the shielded trench gate metal oxide semi-field effect transistor comprises the following steps:
[0053] Step S301: Provide a drain substrate having an epitaxial layer. Figure 4A As shown, there is an epitaxial layer 31 on the N+ drain layer 30.
[0054] Step S302: Etching a groove 301. Figure 4B As shown, a trench 301 is etched on the epitaxial layer 31 .
[0055] Step S303: configure a first oxide layer 302. Figure 4C As shown, the first oxide layer 302 is a thicker oxide layer, which is used to insulate the inner wall of the trench 301 .
[0056] Step S304: depositing a first polysilicon 303a. Figure 4D As shown, by depositing the first polysilicon, the first polysilicon 303 a is deposited into the trench 301 .
[0057] Step S305: Perform an etching process. Figure 4E As shown, through this etching process, the first polysilicon 303a and the first oxide layer 302 are removed from the surface, and the thickness of the first polysilicon 303a and the first oxide layer 302 are reduced to form the source polysilicon 303b.
[0058] Step S306: configure a gate oxide layer 304. Figure 4F As shown, the gate oxide layer 304 is a thin oxide layer used to cover the source polysilicon 303b.
[0059] Step S307: deposit a second polysilicon 305a. Figure 4G As shown, on the gate oxide layer 304, a second polysilicon 305a is deposited.
[0060] Step S308: Dispose a buffer layer on the second polysilicon 305a. Figure 4H As shown, the buffer layer is generally in the form of a coating, such as photoresist or spin on glass (SOG), so that the entire buffer layer 306 can be flat.
[0061] Step S309: Etching the buffer layer 306. Fig. 4I As shown, the etching process uniformly removes the buffer layer and retains the second polysilicon 305 a , and leaves a portion of the buffer layer 306 material above the trench 301 .
[0062] Step S310: Carry out polysilicon etching back, and only retain the second polysilicon 305a in the trench 301 as the gate polysilicon 305b. Figure 4J or Figure 4K As shown, in this embodiment, the polysilicon etching back is, for example, a dry etching to remove the second polysilicon 305 on the surface and retain the second polysilicon 305a in the trench 301 as the gate polysilicon 305b. Since the material of the lower part of the buffer layer 306 is retained in the previous step, the material above the trench 301 (the material of the second polysilicon 305a and the buffer layer 306) is flat, so after the polysilicon etching back is performed, the result is, for example Figure 4J or Figure 4K As shown, it has a relatively flat surface. And the thickness of the center of the gate polysilicon 305b is obviously greater than Figure 2GThe gate polysilicon 204b is thicker than the gate polysilicon 204b. This can avoid the gate polysilicon 305b from being broken through during the subsequent contact process. Figure 4J and Figure 4K It is only a schematic diagram of the cross section after the process step S310 is completed. Although the surface after the actual process is completed will not be such an ideal polygon or arc shape, after many experiments by the applicant, it is indeed better than Figure 2G The situation is better.
[0063] Figure 5 FIG. 1 is a flowchart of the sub-steps of step S305 of the method for manufacturing the gate of a shielded trench gate metal oxide semi-field effect transistor according to a preferred embodiment of the present application. Figure 5 , this step S305 includes the following steps:
[0064] Step S501: Etching the first polysilicon 303a. Figure 6 As shown, the first polysilicon 303 a is etched to expose a portion of the trench 301 .
[0065] Step S502: Etching the first oxide layer 302. Figure 4E As shown, this step is used to remove the first oxide layer 302 on the surface of the epitaxial layer and remove a portion of the first oxide layer 302 in the trench 301 , so that the first oxide layer 302 is lower than or equal to the source polysilicon 303 b in the trench 301 .
[0066] Figure 7 FIG. 1 is a flowchart of the sub-steps of step S308 of the method for manufacturing the gate of a shielded trench gate metal oxide semi-field effect transistor according to a preferred embodiment of the present application. Figure 7 , this step S308 includes the following steps:
[0067] Step S701: Perform a spin coating on glass (SOG) on the surface. In this step, a liquid solvent containing a dielectric material is evenly coated on the wafer surface by spin coating to fill the recess of the deposited dielectric layer.
[0068] Step S702: Perform a heat treatment to remove most of the solvent in the spin-on-glass (SOG), so that the spin-on-glass (SOG) becomes a solid silicon glass.
[0069] The above steps are sub-steps of using spin-on-glass (SOG) as a buffer layer. In another embodiment, the buffer layer may also be made of photoresist.
[0070] Figure 8Another flowchart of the sub-steps of step S308 of the method for manufacturing the gate of a shielded trench gate metal oxide semi-field effect transistor according to a preferred embodiment of the present application is shown. Figure 8 , this step S308 includes the following steps:
[0071] Step S801: coating the surface with photoresist.
[0072] Step S802: performing a curing of the photoresist. In this embodiment, it is not limited to use positive photoresist or negative photoresist.
[0073] Fig.9A The figure shows a cross-sectional view of a shielded trench gate metal oxide semi-field effect transistor according to a preferred embodiment of the present application. Fig.9A In this embodiment, the structure of the shielded trench gate metal oxide semi-field effect transistor includes a drain substrate, an epitaxial layer is provided on the drain substrate, a trench 301 is arranged on the epitaxial layer, and the trench 301 includes an oxide layer 302, a source polysilicon 303b, a gate oxide layer 304, and a gate polysilicon 305b. There are P body doping regions 901 on both sides of the trench 301. The P body doping region 901 and the N+ doping region 902 are arranged adjacent to both sides of the trench 301, wherein the N+ doping region 902 has a larger coverage area. In the process, the P+ doping region 903 is implanted along the hole of the contact window when the contact window is etched (contact etch) and the photoresist is not removed. The position is directly below the contact window, and the depth is deeper than the N+ doping region 902, but shallower than the P body doping region 901. In this embodiment, the P+ doping region 903 and the N+ doping region 902 overlap. In addition, a dielectric layer 904 for insulation is disposed on the trench 301. In this embodiment, it can be seen that the gate polysilicon 305b is much thicker than the gate polysilicon 305b after being repaired by the buffer layer process. Figure 2G The gate polysilicon 204b has a high flatness and a high thickness. Although the above process can also use a chemical mechanical polishing process (CMP) to replace the buffer layer and the back etching process, the chemical polishing process is obviously much more expensive. Therefore, the embodiment of the present application can use a lower cost process to achieve the same result.
[0074] Fig. 9B Another cross-sectional view of a shielded trench gate metal oxide half field effect transistor according to a preferred embodiment of the present application is shown. Fig. 9B In this embodiment, a contact window 905 is disposed on the dielectric layer 904. A person skilled in the art should know that when the routing of the section position is different, the section view will also be different. Fig.9A and Fig. 9B are different components.
[0075] In summary, the embodiment of the present application increases the thickness of the polysilicon layer to be etched by adding a buffer layer in the process, thereby avoiding the thickness defect of the gate polysilicon caused by over-etching in the subsequent back-etching process. This avoids the risk of breaking through the gate polysilicon during the contact process, increases the process yield, and substantially reduces the process cost.
[0076] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in view thereof will be suggested to those skilled in the art and are to be included within the spirit and scope of the present application and the scope of the appended claims.
Claims
1. A method for manufacturing a gate of a shielded trench gate metal oxide semi-field effect transistor, characterized in that: include: Providing a drain substrate having an epitaxial layer; etching a groove; Disposing a first oxide layer to insulate the inner wall of the trench; depositing a first polysilicon; Performing an etching process to form a source polysilicon; Disposing a gate oxide layer to cover the source polysilicon; depositing a second polysilicon; Disposing a buffer layer on the second polysilicon; etching the buffer layer; and The gate polysilicon is etched back to keep only the second polysilicon in the trench as a gate polysilicon.
2. The method for manufacturing a gate of a shielded trench gate metal oxide semi-field effect transistor according to claim 1, characterized in that: A buffer layer is disposed on the second polysilicon, comprising: coating the surface with a photoresist; and A photoresist curing process is performed.
3. The method for manufacturing a gate of a shielded trench gate metal oxide semi-field effect transistor according to claim 1, characterized in that: A buffer layer is disposed on the gate polysilicon, comprising: Spin coating the surface with glass; and Perform a heat treatment.
4. The method for manufacturing a gate of a shielded trench gate metal oxide semi-field effect transistor according to claim 1, characterized in that: Also includes: disposing a dielectric layer; and A contact window is arranged on the dielectric layer to be electrically connected to the gate polysilicon.
5. The method for manufacturing a gate of a shielded trench gate metal oxide semi-field effect transistor according to claim 1, characterized in that: Carrying back the gate polysilicon to retain only the gate polysilicon in the trench includes: A dry etching is performed to remove the second polysilicon on the surface and retain the second polysilicon in the trench as the gate polysilicon.
6. The method for manufacturing a gate of a shielded trench gate metal oxide semi-field effect transistor according to claim 1, characterized in that: The etching process is performed to form the source polysilicon, further comprising: Etching the first polysilicon to expose a portion of the trench; The first oxide layer is etched to remove the first oxide layer on the surface of the epitaxial layer and a portion of the first oxide layer in the trench, so that the first oxide layer is lower than or equal to the source polysilicon in the trench.
7. A shielded trench gate metal oxide semi-field effect transistor, characterized in that: include: a drain substrate; an epitaxial layer, disposed on the drain substrate; A trench, the inner wall of which is covered with a first oxide layer, a source polysilicon is disposed in the trench, a gate oxide layer is disposed on the source polysilicon, and a gate polysilicon is disposed on the gate oxide layer; Wherein, the process of gate polysilicon includes: Performing a second polysilicon deposition process on the gate oxide layer; Disposing a buffer layer on the second polysilicon; etching the buffer layer; and The gate polysilicon is etched back to retain only the second polysilicon in the trench as the gate polysilicon.
8. The shielded trench gate metal oxide semi-field effect transistor according to claim 7, characterized in that: On one side of the groove further comprises: a P-type body region adjacent to the trench; and An N+ doped region is adjacent to the trench.
9. The shielded trench gate metal oxide semi-field effect transistor according to claim 8, characterized in that: On one side of the N+ doped region further comprises: A P+ type doped region is disposed in the P type body region.
10. The shielded trench gate metal oxide semi-field effect transistor according to claim 8, characterized in that: Also includes: A source metal layer is electrically connected to the N+ doped region.