Wafer testing method and wafer testing equipment

Abstract

The embodiment of the invention provides a wafer testing method and wafer testing equipment, and the method comprises the steps: providing a wafer which is provided with a wafer device region and a wafer edge region, and enabling the wafer edge region to surround the wafer device region; wafer testing equipment with a testing table disc is provided, the testing table disc comprises a main body bearing part and an edge bearing part, and the edge bearing part surrounds the main body bearing part and comprises a vacuum adsorption channel and an isolation air leakage channel; a wafer is placed on the test board disc, the wafer device area is located on the main body bearing part, and the wafer edge area is located on the edge bearing part; gas in the vacuum adsorption channel and between the wafer edge area and the edge bearing part is extracted through the vacuum adsorption channel, so that the wafer is fixed on the test board disc, and the isolation gas release channel is communicated with ambient air pressure and separates a space between the wafer device area and the main body bearing part from the vacuum adsorption channel; and testing the wafer by using the probe. According to the wafer testing method and device, the accuracy of wafer testing can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a wafer testing method and a wafer testing device. Background Art

[0002] Chip testing is an important step in the semiconductor manufacturing process. After completing the main manufacturing steps of the semiconductor wafer, the chips on the wafer are tested to screen out defective or failed chips to ensure that the chips entering the subsequent process are qualified chips. However, conventional testing methods may have problems such as inaccurate testing or inability to effectively test all chips, resulting in inaccurate test results on whether the chip is a qualified chip, which may affect subsequent processes. How to improve the accuracy of testing is an important research topic in this field. Summary of the invention

[0003] According to at least one embodiment of the present disclosure, a wafer testing method is provided, comprising: providing a wafer, wherein the wafer has a wafer device area and a wafer edge area, wherein the wafer device area includes a semiconductor device, and the wafer edge area surrounds the wafer device area; providing a wafer testing equipment having a test table, wherein the test table includes a main body bearing part and an edge bearing part, wherein the edge bearing part surrounds the main body bearing part and includes a vacuum adsorption channel and an isolation exhaust channel arranged at intervals; placing the wafer on the test table of the wafer testing equipment, wherein the wafer device area is located on the main body bearing part; the wafer edge area is located on the main body bearing part; and the wafer device area is located on the main body bearing part. The area is located on the edge supporting part, and the vacuum adsorption channel and the isolation air release channel each have an opening facing the edge area of ​​the wafer; the gas in the vacuum adsorption channel and between the edge area of ​​the wafer and the edge supporting part is extracted through the vacuum adsorption channel, so that the air pressure between the edge area of ​​the wafer and the edge supporting part is lower than the ambient air pressure, thereby adsorbing and fixing the wafer on the test table, wherein the isolation air release channel is connected to the ambient air pressure, and the space between the wafer device area and the main supporting part is separated from the vacuum adsorption channel; and the wafer is tested using a probe.

[0004] In the wafer testing method provided according to at least one embodiment of the present disclosure, the semiconductor device has a cavity and a diaphragm, and the cavity is located between the diaphragm and the main body supporting part, and the space between the wafer device area and the main body supporting part includes the cavity and the space at the contact interface between the wafer device area and the main body supporting part; during the test, the air pressure in the cavity is the same as the air pressure on the side of the diaphragm away from the cavity.

[0005] In the wafer testing method provided according to at least one embodiment of the present disclosure, the orthographic projection of the isolated air leakage channel on a reference plane parallel to the main surface of the wafer is located between the orthographic projection of the cavity on the reference plane and the orthographic projection of the vacuum adsorption channel on the reference plane.

[0006] In the wafer testing method provided according to at least one embodiment of the present disclosure, the air pressure on the side of the diaphragm away from the cavity is the ambient air pressure, and the space between the wafer device area and the main body supporting part is connected to the ambient air pressure through the isolation leakage channel.

[0007] In the wafer testing method provided according to at least one embodiment of the present disclosure, the test table has a first surface and a second surface opposite to each other in a direction perpendicular to the main surface of the wafer, the first surface is in contact with the wafer, and the vacuum adsorption channel includes: a first groove, which is recessed from the first surface of the test table toward the second surface; and a first connecting channel, which is connected to the first groove and is connected to a vacuum pump.

[0008] In the wafer testing method provided according to at least one embodiment of the present disclosure, the first connecting channel extends from the first groove to the side wall of the test table.

[0009] In the wafer testing method provided according to at least one embodiment of the present disclosure, the first groove is ring-shaped, or the first groove includes a plurality of first holes.

[0010] In the wafer testing method provided according to at least one embodiment of the present disclosure, the isolated air leakage channel includes: a second groove, which is recessed from a first surface of the test table in contact with the wafer toward a second surface of the test table opposite to the first surface; and a second connecting channel, which is connected to the second groove and the ambient air pressure.

[0011] In the wafer testing method provided according to at least one embodiment of the present disclosure, the second groove is located in the upper portion of the test table, and the second connecting channel extends from the bottom of the second groove to the second surface of the test table.

[0012] In the wafer testing method provided according to at least one embodiment of the present disclosure, the second groove is ring-shaped, or the second groove includes a plurality of second holes.

[0013] In a wafer testing method provided according to at least one embodiment of the present disclosure, the wafer testing equipment includes a probe assembly, the probe assembly includes the probe and an elastic probe fixing bracket, the elastic probe fixing bracket includes a fixing portion and an elastic extension portion connected to each other, the elastic extension portion is elastically movable in a direction perpendicular to the main surface of the wafer, and the probe is fixed on the elastic extension portion.

[0014] In the wafer testing method provided according to at least one embodiment of the present disclosure, the fixing portion extends in a direction perpendicular to the main surface of the wafer, an initial angle between the elastic extension portion and the fixing portion is an obtuse angle, and an angle between the probe and the wafer is an acute angle.

[0015] In the wafer testing method provided according to at least one embodiment of the present disclosure, using the probe to test the wafer includes: using the probe to contact the wafer, in response to the reaction force of the wafer on the probe, the elastic extension portion that fixes the probe undergoes elastic displacement, and the probe slides from a first position to a second position on the wafer, wherein the sliding distance between the first position and the second position ranges from 10 microns to 30 microns.

[0016] At least one embodiment of the present disclosure provides a wafer testing device, comprising: a test table, configured to carry wafers during a wafer testing process, wherein the test table comprises a main body carrying portion and an edge carrying portion, the edge carrying portion surrounds the main body carrying portion and comprises a vacuum adsorption channel and an isolation and leakage channel arranged at intervals, the vacuum adsorption channel is configured to be connected to a vacuum pump, the isolation and leakage channel is configured to be connected to the ambient air pressure, and is arranged on a side of the vacuum adsorption channel away from a side wall of the test table; and a probe assembly, comprising a probe, the probe being configured to test the wafer during the wafer testing process.

[0017] In the wafer testing equipment provided according to at least one embodiment of the present disclosure, the probe assembly also includes: an elastic probe fixing bracket, the elastic probe fixing bracket including a fixing portion and an elastic extension portion, the elastic extension portion being configured to fix the probe and being elastically movable in a direction perpendicular to the main surface of the test table.

[0018] In the wafer testing method and wafer testing equipment provided according to at least one embodiment of the present disclosure, when testing the wafer, the wafer can be stably fixed on the test table while preventing the device structure of the semiconductor device in the wafer device area from being affected by vacuum adsorption during the testing process, thereby preventing the accuracy of the wafer testing from being affected by vacuum adsorption, thereby improving the accuracy of the wafer testing, and all semiconductor devices in the wafer device area can be comprehensively, effectively and accurately tested to ensure that the chips entering the subsequent process are suitable chips, thereby improving the process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0020] Figure 1 A schematic diagram showing a wafer testing device and a wafer according to some embodiments of the present disclosure.

[0021] Figure 2 A schematic cross-sectional view showing a test platen of a wafer testing device and a wafer carried by the test platen according to some embodiments of the present disclosure.

[0022] Figure 3 A schematic plan view showing a test table plate of a wafer testing device according to some embodiments of the present disclosure.

[0023] Figure 4 A schematic cross-sectional view showing a test table plate of a wafer testing device according to some embodiments of the present disclosure.

[0024] Figure 5 Another schematic cross-sectional view of a test table plate of a wafer testing device according to some embodiments of the present disclosure is shown.

[0025] Figure 6 A schematic plan view of a wafer according to some embodiments of the present disclosure is shown.

[0026] Figure 7 A schematic cross-sectional view of a wafer according to some embodiments of the present disclosure is shown.

[0027] Figure 8 A schematic diagram showing displacement of an elastic probe fixing bracket and a probe when a wafer is tested using a wafer testing device during a wafer testing process according to some embodiments of the present disclosure.

[0028] Fig. 9 A schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0029] Fig.10 A schematic flow chart of a wafer testing method according to some embodiments of the present disclosure is shown.

[0030] Explanation of symbols: 11: first surface; 12: second surface; 30: substrate; 31: first dielectric layer; 32: second dielectric layer; 33: back plate; 34: additional cavity; 35: first conductive pad; 36: second conductive pad; 50: wafer test equipment; 100: test table; 101: main body bearing part; 102: edge bearing part; 103: vacuum adsorption channel; 103a: first groove; 103b: first connection channel; 105: isolation and degassing channel; 105a: second groove; 105b: second connection channel; 120: probe base; 121: extension cantilever; 122: fixing part; 123: elastic extension part; 1 24: elastic probe fixing bracket; 125: probe; 150: probe assembly; 200: wafer; 201: wafer device area; 202: wafer edge area; 204: semiconductor device; 205: cavity; 206: diaphragm; α: initial angle; β: first angle; θ: second angle; D1: first direction; D2: second direction; w1: first width; w2: second width; d1: first distance; d2: second distance; d3: third distance; P1: first position; P2: second position; S1: sliding distance; S10: first step; S20: second step; S30: third step; S40: fourth step. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0033] A semiconductor wafer generally includes a plurality of dies, each of which includes one or more semiconductor devices. After the main manufacturing process of the semiconductor wafer is completed, the wafer can be tested, for example, the electrical properties and other properties of the semiconductor devices in the dies on the wafer can be tested. For example, during the wafer testing process, the semiconductor wafer can be placed on a test table of a test device, for example, the wafer can be fixed on the test table by vacuum adsorption, and the wafer can be probed with a probe. In some examples, the die can also be referred to as a chip.

[0034] Generally speaking, the vacuum adsorption method will adsorb and fix the entire wafer on the test table; however, for some semiconductor devices with special structures, vacuum adsorption may affect the device structure of the semiconductor devices in the wafer, which may affect the accuracy of the test results and cause inaccurate test results.

[0035] For instance, in some examples, the wafer may include semiconductor devices with special structures such as cavities and diaphragms. For the testing of such products, due to the influence of these special structures, conventional testing methods may be difficult to meet the special requirements of these products, resulting in inaccurate test results or the inability to test all devices on all dies.

[0036] For example, for a device with a cavity and a diaphragm, when the wafer is fixed by vacuum adsorption, the gas in the cavity will also be pumped out, causing the air pressure in the cavity to be lower than the ambient air pressure, that is, causing an air pressure difference on both sides of the diaphragm, which in turn causes the diaphragm to move and deform. However, this movement and deformation of the diaphragm will affect the accuracy of the test results, resulting in the test results being unable to accurately reflect the true characteristics of the device.

[0037] In some examples, a test chip with a dedicated test pattern may be provided in the wafer, and the diaphragm of the test chip is provided with an air vent to maintain the air pressure balance on both sides of the diaphragm during the test to prevent the diaphragm from being displaced due to vacuum adsorption. However, the diaphragms of other device chips are not provided with air vents and will not be used directly for testing. However, this test method can only perform sampling tests on the devices on the wafer, and infer the parameters of other chips through the test chip, but cannot truly test the true parameters of all chips, and therefore cannot guarantee the test accuracy of all chips.

[0038] In some examples, the chip is tested after a film is attached to the back of the wafer and a dicing process is performed. However, the presence of sealed air pressure in the cavity between the film and the chip will also affect the pressure deformation of the diaphragm during the test, thereby affecting the test accuracy.

[0039] In response to the above-mentioned problem of inaccurate testing, the present disclosure provides a wafer testing method and wafer testing equipment, which can improve the accuracy of wafer testing, realize a comprehensive and effective initial screening of chip performance in the wafer, ensure that chips entering subsequent processes (for example, packaging process) are all qualified chips, and thereby improve product yield.

[0040] For example, an embodiment of the present disclosure provides a wafer testing method, comprising: providing a wafer, wherein the wafer has a wafer device area and a wafer edge area, wherein the wafer device area includes a semiconductor device, and the wafer edge area surrounds the wafer device area; providing a wafer testing device having a test table, wherein the test table includes a main body bearing part and an edge bearing part, wherein the edge bearing part surrounds the main body bearing part and includes a vacuum adsorption channel and an isolation exhaust channel arranged at intervals; placing the wafer on the test table of the wafer testing device, wherein the wafer device area is located on the main body bearing part; and the wafer edge area is located on the main body bearing part. on the edge supporting part, and the vacuum adsorption channel and the isolation air release channel each have an opening toward the edge area of ​​the wafer; the gas in the vacuum adsorption channel and between the edge area of ​​the wafer and the edge supporting part is extracted through the vacuum adsorption channel, so that the air pressure between the edge area of ​​the wafer and the edge supporting part is lower than the ambient air pressure, thereby adsorbing and fixing the wafer on the test table, wherein the isolation air release channel is connected to the ambient air pressure, and the space between the wafer device area and the main supporting part is separated from the vacuum adsorption channel; and the wafer is tested using a probe.

[0041] An embodiment of the present disclosure provides a wafer testing device, comprising: a test table, configured to carry a wafer during a wafer testing process, wherein the test table comprises a main body carrying portion and an edge carrying portion, the edge carrying portion surrounds the main body carrying portion and comprises a vacuum adsorption channel and an isolation air release channel arranged at intervals, the vacuum adsorption channel is configured to be connected to a vacuum pump, the isolation air release channel is configured to be connected to the ambient air pressure, and is arranged on a side of the vacuum adsorption channel away from a side wall of the test table; and a probe assembly, comprising a probe, the probe being configured to test the wafer during the wafer testing process.

[0042] In the wafer testing method of the embodiment of the present disclosure, a wafer adsorption channel and an isolation air release channel are set in the test table of the wafer testing equipment, and the air pressure between the edge area of ​​the wafer and the edge bearing part is made lower than the ambient air pressure through the wafer adsorption channel, so that the wafer is adsorbed and fixed to the test table. At the same time, the isolation air release channel is connected to the ambient air pressure, and the space between the wafer device area and the main body bearing part is separated from the vacuum adsorption channel, so that the device structure of the semiconductor device in the wafer device area can be prevented from being adversely affected by vacuum adsorption during the test process, and the accuracy of the wafer test can be prevented from being affected by vacuum adsorption. Therefore, the accuracy of the wafer test can be improved, and all semiconductor devices in the wafer device area can be comprehensively, effectively and accurately tested to ensure that the chips entering the subsequent process are suitable chips, thereby improving the process yield. The wafer testing equipment disclosed in the present disclosure has the same technical effect as the above-mentioned wafer testing method, which will not be repeated here.

[0043] In some embodiments, the semiconductor device has a cavity and a diaphragm, and the cavity is located between the diaphragm and the main body supporting part, and the space between the wafer device area and the main body supporting part includes the cavity and the space at the contact interface between the wafer device area and the main body supporting part; during the test, the air pressure in the cavity is the same as the air pressure on the side of the diaphragm away from the cavity.

[0044] Therefore, for semiconductor devices with special structures such as cavities and diaphragms, the wafer testing method disclosed in the present invention makes it possible, through the above-mentioned arrangement, to fix the wafer by vacuum adsorption while the air pressure in the cavity located in the wafer device area is the same as the air pressure on the side of the diaphragm away from the cavity, thereby avoiding displacement of the diaphragm due to vacuum adsorption, and further avoiding the accuracy of the test being affected by the displacement of the diaphragm, thereby improving the accuracy of the wafer test.

[0045] Figure 1 A schematic diagram showing a wafer testing device and a wafer according to some embodiments of the present disclosure. Figure 2 Schematic cross-sectional view of a test table and a wafer carried by the test table in a wafer testing device according to some embodiments of the present disclosure is shown. It should be understood that for the sake of simplicity of the figure, Figure 1 The specific structure of the test table and wafer is not shown in detail.

[0046] refer to Figure 1 In some embodiments, the wafer testing device 50 includes a test table 100 and a probe assembly 150. The test table 100 is configured to carry and fix a wafer to be tested, such as wafer 200, during the wafer testing process. The probe assembly 150 is configured to use a probe 125 to perform a test on the wafer during the wafer testing process, such as an electrical test.

[0047] refer to Figure 2In some embodiments, the test table 100 includes a main body bearing portion 101 and an edge bearing portion 102, wherein the edge bearing portion 102 is close to the edge of the test table 100 (i.e., the side wall thereof) and surrounds the main body bearing portion 101. In some embodiments, the edge bearing portion 102 includes vacuum adsorption channels 103 and isolated air release channels 105 that are spaced apart.

[0048] The wafer 200 has a wafer device region 201 and a wafer edge region 202; the wafer device region 201 includes a semiconductor device having a cavity 205 and a diaphragm 206; the wafer edge region 202 is a region of the wafer 200 outside the region having the cavity 205, and may surround the wafer device region 201. No cavity and no diaphragm are provided in the wafer edge region 202.

[0049] In some embodiments, when performing wafer testing, the wafer 200 is placed on the test table 100, wherein the wafer device area 201 is located on the main body supporting part 101 of the test table 100, and the cavity 205 is located between the diaphragm 206 and the main body supporting part 101. In other words, part of the surface of the main body supporting part 101 is exposed to the cavity 205 of the wafer 200.

[0050] The wafer edge region 202 is placed on the edge support portion 102 of the test table 100, and the vacuum adsorption channel 103 and the isolation and exhaust channel 105 each have an opening toward the wafer edge region 202. That is, a portion of the surface of the wafer edge region 202 (ie, Figure 2 The bottom surface shown in FIG. 1 is exposed to the opening of the vacuum adsorption channel 103 and the isolation degassing channel 105. In this article, the opening of the channel refers to the opening of the channel exposed on the surface of the table.

[0051] It should be understood that the wafer and the test table have matching sizes in a direction parallel to the main surface of the wafer, and the sizes of the two can be the same or different from each other, as long as the device area portion of the wafer with the cavity can be arranged corresponding to the main body supporting part, and the edge area of ​​the wafer can be arranged corresponding to the vacuum adsorption channel and the isolation exhaust channel of the edge supporting part.

[0052] In some embodiments, the vacuum adsorption channel 103 is configured to be connected to a vacuum pump (not shown) and is used to adsorb and fix the wafer 200 during the wafer test process. The isolation vent channel 105 is configured to be connected to the ambient air pressure and is configured to separate the space between the wafer device area 201 and the main body support part 101 from the vacuum adsorption channel 103 during the wafer test process; the space between the wafer device area 201 and the main body support part 101 includes a cavity 205. In this way, when the wafer 200 is fixed by vacuum adsorption, the gas in the space (e.g., the cavity 205) between the wafer device area 201 and the main body support part 101 can be prevented from being also drawn away by the vacuum pump. In this article, the channel or space is connected to the ambient air pressure means that the channel or space is directly or indirectly connected to the ambient space in the wafer testing equipment (e.g., the environment in the testing equipment, or the ambient atmosphere), and the air pressure in the channel or space is substantially the same as the ambient air pressure.

[0053] In some embodiments, at least part of the isolated gas leakage channel 105 surrounds the main body supporting part 101, and the vacuum adsorption channel 103 is located on the side of the isolated gas leakage channel 105 away from the main body supporting part 101. The orthographic projection of the cavity 205 on the reference plane parallel to the main surface of the wafer can be located within the orthographic projection of the main body supporting part 101 on the reference plane. For example, the orthographic projection of the isolated gas leakage channel 105 on the reference plane parallel to the main surface of the wafer is located between the orthographic projection of the cavity 205 on the reference plane and the orthographic projection of the vacuum adsorption channel 103 on the reference plane, so that the isolated gas leakage channel can effectively isolate the cavity and the vacuum adsorption channel. In some embodiments, the orthographic projections of at least the openings of the isolated gas leakage channel 105 and the vacuum adsorption channel 103 close to the wafer on the above-mentioned reference plane are located within the orthographic projection of the wafer edge area on the reference plane; for example, the orthographic projections of the isolated gas leakage channel 105 and the vacuum adsorption channel 103 on the reference plane parallel to the main surface of the wafer can be located as a whole within the orthographic projection of the wafer edge area (i.e., the area without the cavity) on the reference plane.

[0054] It should be understood that after the wafer 200 is placed on the test table 100, the wafer 200 and the test table 100 are in contact with each other, but the contact interface between the wafer 200 and the test table 100 is not a completely closed space. For example, there is a tiny space (or can be called a gap) between the wafer 200 and the test table 100 (i.e., at the contact interface between the two). Under normal conditions, the air pressure in the space is the same as the ambient air pressure; in a vacuum state, the gas in the space can be pumped away, so that the air pressure in the space is less than the ambient air pressure, for example, it can be in a vacuum state. In this article, the ambient air pressure refers to the ambient air pressure in the wafer testing equipment, such as normal pressure or atmospheric pressure; the vacuum state may include an absolute vacuum state where the gas pressure is zero or a negative pressure state where the air pressure is less than the ambient air pressure.

[0055] In some embodiments, during the wafer test process, a vacuum pump is used to extract gas from the vacuum adsorption channel 103 and the space between the wafer edge region 202 and the edge bearing portion 102 (i.e., at the contact interface between the two) through the vacuum adsorption channel 103, so that the air pressure between the wafer edge region 202 and the edge bearing portion 102 is less than the ambient air pressure, thereby adsorbing and fixing the wafer 200 on the test table 100. Specifically, during the process of using the vacuum pump to evacuate, in addition to the gas in the vacuum adsorption channel directly connected to the vacuum pump being evacuated, since the space between the edge bearing portion 102 and the wafer edge region 202 (i.e., at the contact interface between the two) is connected to the vacuum adsorption channel 103, the gas in the space is also evacuated, thereby making the air pressure between the edge bearing portion 102 and the wafer edge region 202 less than the ambient air pressure, so that the wafer edge region 202 can be adsorbed and fixed on the edge bearing portion of the test table 100, thereby fixing the wafer 200 on the test table 100.

[0056] The isolation leakage channel 105 is connected to the ambient air pressure, and separates the space between the wafer device area 201 and the main body supporting part 101 from the vacuum adsorption channel 103. The space between the wafer device area 201 and the main body supporting part 101 includes the cavity 205, and also includes the space at the contact interface between the wafer device area 201 and the main body supporting part 101; in this way, the gas in the cavity 205 and at the contact interface between the wafer device area 201 and the main body supporting part 101 can be prevented from being sucked away by the vacuum pump.

[0057] For example, the isolation leak channel 105 is connected to the ambient air pressure, the vacuum adsorption channel 103 is located on the outside of the isolation leak channel, and the main body bearing part 101 is located on the inside of the isolation leak channel 105 to be separated from the vacuum adsorption channel. For example, the isolation leak channel 105 can surround the main body bearing part 101. Therefore, the space between the main body bearing part 101 and the wafer device area 201 can be separated from the vacuum adsorption channel 103 by the isolation leak channel 105, so that the gas in the cavity 205 of the wafer device area 201 and the gas in the space at the contact interface between the main body bearing part 101 and the wafer device area 201 will not be pumped away by the vacuum pump. For example, the cavity 205 and the space at the contact interface between the wafer device area 201 and the main body bearing part 101 are connected to the isolation leak channel 105 and the ambient air pressure.

[0058] In some embodiments, the cavity 205 is connected to the isolated gas leakage channel 105 through the space at the contact interface between the wafer device area 201 and the main body bearing part 101. For example, the opening of the isolated gas leakage channel 105 close to the side of the wafer is not directly connected to the cavity 205, that is, the opening of the isolated gas leakage channel 105 and the cavity 205 do not overlap each other in the direction perpendicular to the main surface of the wafer or the test table. In other words, the orthographic projection of at least the opening of the isolated gas leakage channel 105 on the reference plane parallel to the main surface of the wafer or the test table does not overlap (that is, staggered) with the orthographic projection of the cavity 205 on the reference plane. For example, the entire orthographic projection of the isolated gas leakage channel 105 on the reference plane may not overlap with the orthographic projection of the cavity 205 on the reference plane. For example, a portion of the contact interface between the wafer device area 201 and the main body bearing part 101 is located between the opening of the isolated gas leakage channel 105 and the cavity 205 in the direction parallel to the main surface of the wafer. In this way, it can be further ensured that the cavity 205 is separated from the vacuum adsorption channel to prevent the gas in the cavity from being sucked away during the vacuum adsorption process.

[0059] In some embodiments, the air pressure on the side of the diaphragm away from the cavity is the ambient air pressure, and the space between the wafer device area and the main body bearing portion is connected to the ambient air pressure through the isolation air leakage channel. In this way, the air pressure on both sides of the diaphragm is substantially the same, thereby preventing the diaphragm from being displaced due to the pressure difference on both sides.

[0060] For example, a probe can be used to test the wafer, and during the test, while the air pressure between the edge supporting portion and the edge area of ​​the wafer is lower than the ambient air pressure to fix the wafer, the air pressure in the cavity 205 of the wafer device area and the air pressure on the side of the diaphragm 206 away from the cavity can be roughly equal to each other, for example, both are equal to the ambient air pressure.

[0061] It should be understood that since the wafer edge area and the wafer device area of ​​the wafer are connected to each other as a whole, the main supporting part and the edge supporting part of the test table are also connected to each other as a whole, and the wafer edge area surrounds the wafer device area, and the edge supporting part surrounds the main supporting part, so a vacuum is formed between the wafer edge area and the edge supporting part so that the wafer edge area is adsorbed on the main supporting part, and the entire wafer can be stably fixed on the test table.

[0062] For example, during the wafer test process, the vacuum pump can work continuously, and the working power of the vacuum pump can be adjusted as needed, so that the gas in the space between the edge bearing portion 102 and the wafer edge area 202 can be continuously pumped away, that is, the air pressure in the space is continuously maintained in a vacuum state, so that the wafer can be continuously and stably fixed on the test table. Therefore, although the space between the edge bearing portion and the wafer edge area is also connected to the isolation leakage channel, the vacuum pump can be continuously operated to extract the gas between the edge bearing portion and the wafer edge portion in the above manner. For example, the rate at which the gas in the space is pumped away by the vacuum pump is greater than the rate at which the gas from the isolation leakage channel enters the space, so that the air pressure between the wafer edge portion and the edge bearing portion can always be maintained in a vacuum state (for example, a negative pressure state) during the wafer test process, and then the wafer edge portion can be continuously adsorbed and fixed on the edge bearing portion, thereby fixing the entire wafer on the test table.

[0063] In the embodiments disclosed herein, the space between the wafer edge area and the edge supporting portion is in a vacuum state, while the space between the wafer device area and the main supporting portion is separated from the vacuum adsorption channel, for example, is in an ambient air pressure state. Therefore, during the wafer testing process, while keeping the wafer stably fixed on the test table, the device structure of the semiconductor device in the wafer device area will not be generally affected by the vacuum adsorption. For example, when the semiconductor device has special structures such as a cavity and a diaphragm, the pressure difference on both sides of the diaphragm of the semiconductor device can be avoided to prevent deformation, thereby improving the accuracy of the wafer testing.

[0064] In some embodiments, in the wafer testing device, the test table has a first surface and a second surface opposite to each other in a direction perpendicular to the main surface of the wafer, the first surface is configured to contact the wafer during wafer testing, and the vacuum adsorption channel includes: a first groove, which is recessed from the first surface of the test table toward the second surface; and a first connecting channel, which is connected to the first groove and is connected to a vacuum pump. For example, the first connecting channel extends from the first groove to the side wall of the test table. For example, the first groove is annular, or the first groove includes a plurality of first holes.

[0065] In some embodiments, the isolated vent channel of the test bench includes: a second groove recessed from the first surface of the test bench toward the second surface; and a second connecting channel connected to the second groove and the ambient air pressure. For example, the second groove is located in the upper part of the test bench, and the second connecting channel extends from the bottom of the second groove to the second surface of the test bench. For example, the second groove is annular, or the second groove includes a plurality of second holes.

[0066] Figure 3A schematic plan view showing a test table plate of a wafer testing device according to some embodiments of the present disclosure; Figure 4 A schematic cross-sectional view showing a test table plate of a wafer testing device according to some embodiments of the present disclosure; Figure 5 Another schematic cross-sectional view of a test table of a wafer test device according to some embodiments of the present disclosure is shown. For example, Figure 4 and Figure 5 Along Figure 3 A cross-sectional view taken along line AB and line AC; Figure 3 is along Figure 4 A plan view taken along line I-I'.

[0067] refer to Figures 3 to 5 For example, the plane shape of the test table 100 may be circular. The test table 100 is used to carry the wafer to be tested, and has a first surface 11 and a second surface 12 that are opposite to each other in a direction perpendicular to the main surface of the wafer (or the main surface of the test table). The first surface 11 of the test table 100 is configured to contact the wafer during the wafer testing process. The vacuum adsorption channel 103 and the isolation degassing channel 105 have an opening exposed at the first surface 11. The first surface 11 or the second surface 12 may also be referred to as the main surface of the test table. The main surface of the test table is substantially parallel to the main surface of the wafer.

[0068] In some embodiments, the vacuum adsorption channel 103 of the test table 100 includes a first groove 103a and a first connecting channel 103b. For example, the first groove 103a is recessed from the first surface 11 of the test table 100 toward the second surface 12; the first connecting channel 103b is connected to the first groove 103a and is connected to a vacuum pump (not shown). In some embodiments, the first connecting channel 103b extends from the first groove 103a to the side wall of the test table 100.

[0069] like Figure 4 and Figure 5 As shown, for example, the first groove 103a may extend from the first surface 11 of the test table 100 to the test table 100 in a direction perpendicular to the main surface of the wafer, without penetrating the test table 100, that is, in the direction perpendicular to the main surface of the wafer, the depth of the first groove 103a is less than the thickness of the test table 100. For example, the extension direction of the first connecting channel 103b may be different from the extension direction of the first groove 103a (that is, intersecting, such as approximately perpendicular). For example, the first connecting channel 103b may extend in a direction approximately parallel to the main surface of the wafer, and may extend from the bottom of the first groove 103a to the side wall of the edge of the test table 100.

[0070] For example, Figure 3As shown, the first groove 103a may be annular, such as a circular ring; one or more first connecting channels 103b may be connected to the first groove 103a, for example, may be arranged on the side of the annular groove and extend to the side wall of the edge of the test table to connect to the vacuum pump.

[0071] In other embodiments, the first groove may include a plurality of first holes, and the plurality of first holes may be spaced apart from each other and connected to the vacuum pump through one or more first connecting channels. In other embodiments, the first connecting channel may also extend from the first groove to the second surface of the test table to connect to the vacuum pump at the second surface, and the present disclosure is not limited to this. It should be understood that the shape of the vacuum adsorption channel shown in the figure is only for illustration, and the present disclosure is not limited thereto. The vacuum adsorption channel may have any suitable shape or structure, as long as a vacuum pump can be used to extract the gas between the edge bearing portion of the test table and the edge area of ​​the wafer through the channel, so that a vacuum state is maintained between the edge bearing portion and the edge area of ​​the wafer, thereby fixing the wafer on the test table.

[0072] refer to Figures 3 to 5 In some embodiments, the isolation leak channel 105 includes a second groove 105a and a second connecting channel 105b. For example, the second groove 105a is recessed from the first surface 11 of the test table 100 toward the second surface 12; the second connecting channel 105b is connected to the second groove 105a and the ambient air pressure. Figure 5 As shown, the second groove 105a is located in the upper portion of the test bench 100, that is, the depth of the second groove is less than the thickness of the test bench, and the second connecting channel 105b extends from the bottom of the second groove 105a to the second surface of the test bench 100. In other words, the second groove 105a and the second connecting channel 105b may overlap in a direction perpendicular to the main surface of the test bench, and are spatially connected to each other. Figure 4 The cross-sectional view shows the structure at the overlapping position of part of the second groove 105a and the second connecting channel 105b, at which position, the second groove 105a and the second connecting channel 105b are spatially connected in a direction perpendicular to the main surface of the test bench, so that the isolation bleed channel 105 passes through the test bench 100 at this position, that is, extends from the first surface 11 to the second surface 12 of the test bench 100. Figure 5 The cross-sectional view of FIG. 1 shows that the first portion of the second groove 105a overlaps the second connection channel 105b, and the second portion of the second groove 105a does not overlap the second connection channel 105b. At the second portion of the second groove 105a, the isolation vent channel 105 extends from the first surface 11 of the test table 100 into the test table 100 without penetrating the test table 100.

[0073] like Figure 3As shown, in some embodiments, the second groove 105a is annular, for example, a circular ring. One or more second connecting channels 105b are arranged at the bottom of the annular second groove to communicate with the ambient air pressure. It should be understood that in order to clearly show the positional relationship between the second groove and the second connecting channel in the plan view, Figure 2 , the size (e.g., width) of the second connection channel is shown as being larger than the corresponding size of the second groove, but the present disclosure is not limited thereto. In a direction parallel to the main surface of the test table, the size of the second groove 105a and the size of the second connection channel 105b may be the same or different from each other, as long as the second groove can be connected to the ambient air pressure through the second connection channel.

[0074] In other embodiments, the second groove may also be a hole-shaped structure including a plurality of second holes, and the plurality of second holes are connected to the ambient air pressure through one or more second connecting channels. It should be understood that the shape and structure of the isolation air leakage channel shown in the figure are only for illustration, and the present disclosure is not limited thereto, as long as the space between the wafer device area and the main body bearing part can be separated from the vacuum adsorption channel by the isolation air leakage channel during the wafer testing process, so as to prevent the space from being evacuated and / or make the air pressure of the space substantially the same as the ambient air pressure.

[0075] Continue to refer Figures 3 to 5 In some embodiments, the isolated air leakage channel 105 (e.g., the second groove thereof) surrounds the main body bearing portion 101. The vacuum adsorption channel 103 is close to the edge of the test table 100 and is located on the side of the isolated air leakage channel 105 away from the main body bearing portion 101. That is, the isolated air leakage channel 105 is located between the vacuum adsorption channel 103 and the main body bearing portion 101. For example, the vacuum adsorption channel 103 (e.g., the first groove thereof) may surround the isolated air leakage channel 105 and be spaced apart from the isolated air leakage channel 105.

[0076] In some embodiments, the opening of the first connecting channel 103b of the vacuum adsorption channel 103 and the opening of the second connecting channel 105b of the isolation air leakage channel 105 are respectively arranged at the side wall and the second surface of the test bench, which can facilitate the connection of the first connecting channel with the vacuum pump without affecting the opening of the isolation air leakage channel 105, but the present disclosure is not limited to this. The opening of the vacuum adsorption channel and the opening of the isolation air leakage channel can also be arranged at the second surface of the test bench, as long as the two are separated by a suitable distance so that the isolation air leakage channel can be connected to the ambient air pressure and the vacuum adsorption channel can be connected to the vacuum pump. In this article, the opening of each channel refers to the portion of the channel exposed at the surface (first surface, second surface or side wall surface) of the test bench.

[0077] refer to Figure 3In some embodiments, the vacuum adsorption channel 103 is disposed at a position close to the edge of the test table (i.e., its side wall). For example, the first distance d1 of the vacuum adsorption channel 103 from the edge of the test table 100 may range from about 1 millimeter (mm) to 8 millimeters. In some embodiments, the first width w1 of the vacuum adsorption channel 103 may be set in the range of 0.5 mm to 5 mm. The size ranges of the above-mentioned vacuum adsorption channels are all the size ranges of their main parts (i.e., the first grooves). The above-mentioned first distance d1 and first width w1 are both corresponding dimensions in a direction parallel to the main surface of the test table, and are corresponding dimensions in a direction perpendicular to the extension direction of the vacuum adsorption channel, for example, corresponding dimensions in a direction perpendicular to the circumferential direction of the test table.

[0078] In some embodiments, setting the corresponding size of the vacuum adsorption channel within the above range can facilitate the corresponding arrangement of the vacuum adsorption channel and the edge area of ​​the wafer, and enable the wafer to be adsorbed and fixed on the test table through the vacuum adsorption channel.

[0079] Continue to refer Figure 3 In some embodiments, the isolation air leakage channel 105 is disposed on a side of the vacuum adsorption channel 103 away from the edge of the test table, and is spaced apart from the vacuum adsorption channel 103. For example, the second distance d2 of the isolation air leakage channel 105 from the edge of the test table 100 (i.e., its side wall) may range from about 4 mm to 10 mm or 3 mm to 10 mm. In some embodiments, the second width w2 of the isolation air leakage channel 105 may be set in the range of 0.5 mm to 2 mm. The size ranges of the above-mentioned isolation air leakage channels are both the size ranges of their main parts (e.g., the second grooves). The above-mentioned second distance d2 and second width w2 are both corresponding dimensions in a direction parallel to the main surface of the test table, and are corresponding dimensions in a direction perpendicular to the extension direction of the isolation air leakage channel, for example, corresponding dimensions in a direction perpendicular to the circumferential direction of the test table.

[0080] In some embodiments, setting the corresponding size of the isolation leak channel 105 within the above range can be beneficial to isolating the vacuum adsorption channel and the wafer device area during the wafer testing process, avoiding the space between the wafer device area and the main body supporting part from being evacuated, and can also help maintain the space between the wafer device area and the main body supporting part at an air pressure roughly the same as the ambient air pressure.

[0081] Figure 6 A schematic plan view showing a wafer according to some embodiments of the present disclosure, Figure 7 A schematic cross-sectional view of a wafer according to some embodiments of the present disclosure is shown.

[0082] refer to Figure 6 and Figure 7In some embodiments, the wafer 200 may include a wafer device region 201 and a wafer edge region 202. For example, the wafer edge region 202 may be annular and surround the wafer device region 201 in a direction parallel to the main surface of the wafer. A semiconductor device 204 having a cavity 205 and a diaphragm 206 is disposed in the wafer device region 201. In some embodiments, the wafer 200 includes a substrate and a device material layer formed on the substrate. For example, the wafer 200 may be a semiconductor wafer and include a semiconductor substrate; for example, the wafer 200 may be a silicon wafer including a silicon substrate.

[0083] For example, the wafer 200 includes a plurality of tube cores, which may be arranged in an array and spaced apart from each other by a dicing region, and each tube core may include one or more semiconductor devices. Figure 6 and Figure 7 In the example shown, each tube die corresponds to a semiconductor device 204. In some embodiments, at least some of the devices of the plurality of tube dies may be devices including cavities and diaphragms, for example, may include micro-electro-mechanical system (MEMS) devices. For example, the product formed by subsequent cutting of the tube die including the MEMS device may also be called a MEMS chip.

[0084] In some embodiments, multiple dies on a wafer have similar structures, that is, each die may include a MEMS device having a cavity and a diaphragm. For the sake of simplicity of the drawings, Figure 6 The cavity 205 and the diaphragm 206 included in the semiconductor device corresponding to one die are schematically shown. It should be understood that the semiconductor devices corresponding to other dies also have similar structures. The number and arrangement of the multiple dies in the figure are only for illustration, and the present disclosure is not limited thereto.

[0085] In some embodiments, the cavities and diaphragm structures of the semiconductor devices of the plurality of dies are all arranged in the wafer device area, while the cavities and diaphragm structures are not arranged in the wafer edge area, so that the wafer edge area is arranged corresponding to the vacuum adsorption channel of the test table, and the cavities and diaphragm structures are not adversely affected by the vacuum adsorption. That is, in the manufacturing process of the wafer, the cavity process is not performed in its edge area.

[0086] In some embodiments, Figure 7As shown, the third distance d3 between the edge of the outermost cavity in the wafer and the edge of the side wall of the wafer may be in the range of 4 mm to 10 mm or 3 mm to 10 mm, that is, no cavity structure is provided in the region of 3 or 4 mm to 10 mm from the edge of the side wall of the wafer (for example, may be or include the wafer edge region). By not providing a cavity in this region and having the above-mentioned size range, this region may have a sufficient size to fix the entire wafer on the test table by vacuum adsorption.

[0087] It should be understood that Figure 6 The dotted circle schematically shows the boundary between the wafer device area and the wafer edge area, but this is only for illustration. The wafer edge area refers to the area outside the area with the cavity of the wafer, for example, it may include all areas outside the outermost device cavity. The wafer device area and the wafer edge area may also partially overlap, as long as no cavity is set in the wafer edge area.

[0088] In some embodiments, the wafer testing equipment includes a probe assembly, the probe assembly includes the probe and an elastic probe fixing bracket, the elastic probe fixing bracket includes a fixing part and an elastic extension part connected to each other, the elastic extension part is elastically movable in a direction perpendicular to the main surface of the wafer or the main surface of the test table, and the probe is fixed on the elastic extension part.

[0089] In some embodiments, the fixing portion extends in a direction perpendicular to the main surface of the wafer, and the initial angle between the elastic extension portion and the fixing portion is an obtuse angle, and the angle between the probe and the wafer is an acute angle. For example, the angle between the probe and the wafer ranges from 30° to 80°.

[0090] In some embodiments, during the process of testing a wafer using a probe, the probe is used to contact the wafer, and in response to the reaction force of the wafer on the probe, the elastic extension portion that fixes the probe undergoes elastic displacement, and the probe slides from a first position to a second position on the wafer, wherein the sliding distance between the first position and the second position ranges from 10 microns to 30 microns.

[0091] Return to reference Figure 1 In some embodiments, the probe assembly 150 of the wafer testing device 50 may include a probe base 120, an extension cantilever 121, an elastic probe fixing bracket 124, and a probe 125. The extension cantilever 121 is connected to the probe base 120, for example, it may extend outward from the side wall of the probe base 120. The extension cantilever 121 and the probe base 120 may be an integrally formed structure, or they may be fixedly connected to each other using a connecting member.

[0092] The elastic probe fixing bracket 124 is fixed on the extension cantilever 121. For example, a fixing hole may be provided on the extension cantilever 121, and the elastic probe fixing bracket 124 is fixed on the extension cantilever 121 through the fixing hole.

[0093] In some embodiments, the elastic probe fixing bracket 124 includes a fixing portion 122 and an elastic extension portion 123 connected to each other. The fixing portion 122 is fixedly connected to the extension cantilever 121 and will not be substantially displaced during the wafer testing process. The elastic extension portion 123 is used to fix the probe 125, for example, it can extend from the fixing portion 122 to above the test table, so as to facilitate the probe 125 to test the wafer on the test table. The elastic extension portion 123 is elastic, for example, it can be elastically moved in a direction perpendicular to the main surface of the wafer (for example, the first direction D1), for example, it can be displaced up and down in the direction under force. In some embodiments, the fixing portion 122 and the elastic extension portion 123 can be an integrally formed structure.

[0094] In some embodiments, the probe 125 is fixed to the elastic extension 123 of the elastic probe fixing bracket 124, for example, fixed at a position close to the edge of the elastic extension 123. Here, the edge of the elastic extension 123 refers to the edge of the side away from the fixing portion 122. For example, the elastic extension 123 and the probe 125 can be fixedly connected together using a connector such as a screw.

[0095] In some embodiments, suitable materials and dimensions and other structural settings can be selected to make the elastic probe fixing bracket 124 have elasticity while having structural stability. The structural stability means that the elastic probe fixing bracket 124 can effectively fix the probe so that the probe can effectively contact the wafer to test the wafer. Elasticity means that the elastic probe fixing bracket 124 can undergo elastic displacement when subjected to force.

[0096] For example, the elastic modulus of the material of the elastic probe fixing bracket 124 may be set in the range of about 100 GPa to about 300 GPa, such as about 190 GPa to 210 GPa, such as about 200 GPa. For example, the elastic probe fixing bracket 124 may include materials such as stainless steel.

[0097] In some embodiments, the initial angle α between the fixed portion 122 and the elastic extension portion 123 is set to an obtuse angle, that is, 90°<α<180°, the diameter range of the elastic extension portion 123 can be about 2 mm to 5 mm, and the length range of the elastic extension portion can be about 10 cm to 30 cm, 10 cm to 20 cm or 10 cm to 15 cm. Here, the initial angle refers to the angle between the fixed portion and the elastic extension portion when the elastic extension portion does not undergo elastic displacement; the length of the elastic extension portion refers to the length in the direction of its extension, and the diameter of the elastic extension portion generally refers to the width in the direction perpendicular to its extension direction. In some embodiments, while maintaining the elasticity of the elastic extension portion, the length of the elastic extension portion can be set to match the size of the wafer to be tested, so as to facilitate the probe assembly to test the wafer; the above-mentioned length range of the elastic extension portion is only for illustrative purposes, and the present disclosure is not limited thereto, and the length can be adjusted and set according to the size of the wafer to be tested.

[0098] In some embodiments, the elastic extension part can be made to have a certain elasticity by setting the angle between the fixing part and the elastic extension part to be an obtuse angle, setting the diameter of the elastic extension part to be smaller, and / or setting the length of the elastic extension part to be longer. Moreover, the probe fixing bracket can effectively provide probe pressure while being elastic, that is, the probe fixed thereon can apply appropriate pressure to the wafer and contact the wafer, so that the probe can effectively test the wafer.

[0099] In some embodiments, the probe 125 is fixed on the elastic extension 123 at an angle, for example, fixed at a position close to the edge of the elastic extension 123. For example, the distance between the position where the elastic extension 123 fixes the probe 125 and the edge of the elastic extension 123 can range from about 0.5 cm to 3 cm. In some embodiments, the first angle β between the probe 125 and the wafer 200 is set to an acute angle, for example, in the range of 30° to 80°. The angle between the probe and the wafer refers to the angle between the probe and the main surface of the wafer, for example, the angle between the extension direction of the probe and the horizontal direction (for example, the horizontal direction including the second direction D2 shown in the figure). It should be understood that, combined with the above-mentioned angle between the elastic extension 123 and the fixing portion 122 is an obtuse angle, and the angle between the probe 125 and the wafer 200 is an acute angle, it can be inferred that the second angle θ between the probe 125 and the elastic extension 123 is an obtuse angle. In some embodiments, the elastic modulus of the probe 125 is greater than the elastic modulus of the elastic probe fixing bracket 124, that is, the rigidity of the probe 125 is greater than the rigidity of the elastic probe fixing bracket 124, so that when the probe assembly is pressed down to contact the wafer for testing, the probe assembly has elasticity and the probe can effectively contact the wafer to perform effective wafer testing and ensure the accuracy of the test. For example, the probe 125 can be made of wear-resistant material, such as tungsten or its alloys, that is, the probe 125 can be a tungsten needle.

[0100] In some embodiments, during the wafer test process, the probe 125 is used to contact the wafer 200, and in response to the reaction force of the wafer 200 on the probe 125, the elastic extension 123 of the fixed probe 125 is elastically displaced, and the probe 125 slides from the first position to the second position on the wafer 200. For example, the sliding distance between the first position and the second position can be controlled to be in the range of 10 microns to 30 microns.

[0101] For example, during the wafer test process, when the probe 125 is brought into contact with the wafer 200 for testing, the probe 125 will apply a certain pressure to the wafer 200, and the wafer 200 will apply a reaction force to the probe 125 and the elastic extension 123 fixing it. Due to the elasticity of the elastic probe fixing bracket and the above-mentioned angle setting of the elastic probe fixing bracket and the probe, the elastic extension 123 will be elastically displaced when subjected to the reaction force, and at the same time drive the probe 125 to slide a distance on the wafer 200. The sliding distance of the probe may be proportional to the pressure of the probe pressing down, that is, the greater the pressure applied by the probe to the wafer, the longer the sliding distance; the smaller the pressure applied by the probe to the wafer, the smaller the sliding distance. In other words, the sliding distance can reflect the pressure of the probe. For wafers including semiconductor devices with cavities or thinner wafer slices, if the pressure applied by the probe to the wafer is too large during wafer testing, the device structure may be damaged. In the embodiments of the present disclosure, the sliding distance of the probe can be controlled by the elasticity of the probe fixing bracket and the above-mentioned angle and other structural settings, thereby controlling the pressure of the probe on the wafer. Therefore, through the above-mentioned settings, during the test process, when the probe is pressed down, a certain elasticity can be maintained while effectively providing the probe pressure for effective testing, and the pressure of the probe on the wafer can be controlled within a suitable range, and the stability of the probe pressure can be maintained, so that while the wafer test can be effectively carried out, the probe can be prevented from causing damage to the device structure in the wafer, and repeated testing of the wafer device structure by the probe can be achieved.

[0102] Figure 8 The schematic diagram schematically shows the sliding of the probe when pressing down on the wafer during wafer testing, wherein the positions of the elastic extension part and the probe after displacement are schematically shown with dotted lines.

[0103] refer to Figure 8, when performing wafer testing, the probe 125 is used to contact the wafer 200 to perform wafer testing. For example, the probe 125 can contact the test pad on the semiconductor device of the wafer 200 to perform electrical testing on the semiconductor device. When the probe 125 contacts the wafer 200, it will apply pressure to the wafer 200, and the wafer 200 will apply a reaction force to the probe 125, and the reaction force will be transmitted to the elastic extension 123 of the elastic probe fixing bracket through the probe 125; because the elastic extension 123 is elastic and the angle between the probe 125 and the wafer is set at an acute angle, because when subjected to the reaction force, the elastic extension 123 will be elastically displaced, for example, moving away from the wafer in the first direction D1, and at the same time driving the probe 125 to slide a distance on the wafer 200, for example, the probe 125 slides a distance in the horizontal direction such as the second direction D2. For example, the probe 125 slides from the first position P1 to the second position P2 on the wafer 200. The distance between the first position P1 and the second position P2 is the sliding distance S1 of the probe 125 .

[0104] In some embodiments, the sliding distance S1 is controlled within a range of 10 microns to 30 microns. By controlling the sliding distance within a suitable range, the pressure applied by the probe to the wafer can be controlled within a suitable range, thereby preventing the probe from damaging the device structure in the wafer.

[0105] In the embodiment of the present disclosure, compared with using a completely rigid fixing bracket without any elasticity, since the elastic probe fixing bracket is elastic and the angle between the probe and the wafer is set to an acute angle, the pressure or stress on the wafer from the probe can be reduced, thereby avoiding damage to the device structure of the wafer.

[0106] It should be understood that the wafer testing equipment and testing method disclosed in the present invention can be applicable to any type of semiconductor devices, and in particular, can improve the testing accuracy of wafers having device structures with special structures such as cavities. Figure 2 and Figure 7 The cavity and diaphragm of the semiconductor device in the wafer are schematically shown, but the specific structure of all components of the semiconductor device is not specifically shown.

[0107] Fig. 9 A schematic cross-sectional view of a semiconductor device in a wafer according to some embodiments of the present disclosure is shown.

[0108] refer to Fig. 9In some embodiments, the semiconductor device 204 may be a MEMS device, and may include a substrate 30, a first dielectric layer 31, a diaphragm 206, a second dielectric layer 32, a back plate 33, a first conductive pad 35, and a second conductive pad 36. The substrate 30 may be a semiconductor substrate, such as a silicon substrate. The first dielectric layer 31 is disposed on one side of the substrate 30, the diaphragm 206 is disposed on the side of the first dielectric layer 31 away from the substrate 30, and the back plate 33 is disposed on the side of the diaphragm 206 away from the substrate 30, and is spaced from the diaphragm 206. For example, the second dielectric layer 32 is disposed between the back plate 33 and the diaphragm 206. A cavity 205 is disposed on the back side of the semiconductor device 204, for example, the cavity 205 extends from the surface of the substrate 30 on the side away from the diaphragm 206 (i.e., the back surface) through the substrate 30 and the first dielectric layer 31, and exposes the diaphragm 206.

[0109] In some embodiments, an additional cavity 34 is provided between the back plate 33 and the diaphragm 206, and a via is provided on the back plate 33, and the via is connected to the additional cavity 34 space, so that the additional cavity 34 is connected to the external environment, that is, the air pressure of the additional cavity 34 is the same as the ambient air pressure. The cavity 205 and the additional cavity 34 located on opposite sides of the diaphragm 206 are separated by the diaphragm 206. For example, the diaphragm 206 may not be provided with a via.

[0110] The diaphragm 206 and the back plate 33 both include electrode materials, such as doped semiconductor materials.

[0111] The first conductive pad 35 is electrically connected to the diaphragm 206, and the second conductive pad 36 is electrically connected to the back plate 33. In this way, the diaphragm 206 and the back plate 33 as well as the second dielectric layer 32 and the additional cavity 34 constitute a capacitor element, wherein the diaphragm 206 and the back plate 33 respectively serve as electrode plates of the capacitor element, and the second dielectric layer 32 and the additional cavity 34 constitute an inter-electrode dielectric. The first conductive pad 35 and the second conductive pad 36 serve as conductive terminals of the capacitor element and can be used to detect the capacitance value of the capacitor element. The first conductive pad 35 and the second conductive pad 36 can be used as test pads. For example, during wafer inspection, a probe can be used to contact the test pad to test the corresponding electrical properties of the capacitor element.

[0112] The capacitance value of the capacitor element is proportional to the area of ​​the electrode plates facing each other and inversely proportional to the distance between the electrode plates. For example, when the diaphragm 206 is subjected to upward or downward pressure, the diaphragm 206 moves toward or away from the back plate 33 (e.g., bends), and the distance between the diaphragm 206 and the back plate 33 changes, and the capacitance value of the capacitor element also changes accordingly.

[0113] Combination Figure 2 and Fig. 9When performing wafer testing, the substrate 30 of the semiconductor device 204 in the wafer contacts the test table 100, and the cavity 205 is located between the diaphragm 206 and the test table 100. By setting a vacuum adsorption channel and an isolated air release channel in the test table, the wafer can be stably fixed on the test table while avoiding the cavity 205 from being evacuated, and the air pressure of the cavity 205 can be made substantially the same as the ambient air pressure; and the air pressure of the additional cavity 34 is also substantially the same as the ambient air pressure. Therefore, the air pressure on the opposite sides of the diaphragm 206 is substantially the same, so that the diaphragm 206 will not be displaced due to the vacuum adsorption of the wafer, thereby ensuring the accuracy of the wafer test.

[0114] It should be understood that Fig. 9 The specific structure of the semiconductor device 204 shown is only for illustration, and the present disclosure is not limited thereto. For example, in other embodiments, the semiconductor device 204 may include a cavity 205 and a diaphragm 206, but does not have a back plate 33. The present disclosure does not limit the specific type of semiconductor device. For example, the semiconductor device may also be other types of MEMS devices including a cavity and a diaphragm to improve the test accuracy of these semiconductor devices. Of course, the wafer testing equipment and method of the present disclosure can also be applied to semiconductor devices without a cavity and a diaphragm.

[0115] Fig.10 A schematic flow chart of a wafer testing method according to some embodiments of the present disclosure is shown.

[0116] For example, refer to Figures 1 to 8 and Fig.10 In the first step S10, a wafer 200 and a wafer testing device 50 are provided, wherein the wafer 200 has a wafer device area 201 and a wafer edge area 202, and the test table 100 of the wafer testing device 50 includes a main body bearing portion 101 and an edge bearing portion 102. The edge bearing portion 102 of the test table 100 includes a vacuum adsorption channel 103 and an isolation exhaust channel 105. The wafer testing device 50 also includes a probe assembly 150. The specific structure of the wafer 200 and the wafer testing device 50 can be referred to the above description of Figures 1 to 8 The description is not repeated here.

[0117] In the second step S20, the wafer 200 is placed on the test table 100 of the wafer testing equipment, wherein the wafer device area 201 is located on the main body supporting part 101, and the wafer edge area 202 is located on the edge supporting part 102. For example, the vacuum adsorption channel 103 and the isolation air release channel 105 have an opening toward the wafer edge area 202. In some embodiments, the wafer 200 and the test table 100 have sizes and shapes that match each other, so that the wafer device area and the main body supporting part are correspondingly arranged, and the wafer edge area and the edge supporting part are correspondingly arranged.

[0118] In the third step S30, the wafer 200 is fixed on the test table 100 by suction through the vacuum suction channel 103 using a vacuum suction method, wherein the air pressure between the wafer edge region 202 and the edge bearing portion 102 is less than the ambient air pressure, and the space between the wafer device region 201 and the main body bearing portion 101 is separated from the vacuum suction channel 103. For example, a vacuum pump can be used to extract the gas between the vacuum suction channel 103 and the wafer edge region 202 and the edge bearing portion 102 through the vacuum suction channel 103, so that the air pressure between the wafer edge region 202 and the edge bearing portion 102 is less than the ambient air pressure, thereby fixing the wafer 200 on the test table 100 by suction, wherein the isolation venting channel 105 is connected to the ambient air pressure, and the space between the wafer device region 201 and the main body bearing portion 101 is separated from the vacuum suction channel.

[0119] In the fourth step S40, the wafer 200 is tested using the probe 125. The specific configuration of the elastic probe fixing bracket and the probe can refer to the above related description, which will not be repeated here.

[0120] In the above-mentioned wafer testing method, by setting an isolation leak channel to separate the space between the wafer device area and the main body bearing part from the vacuum adsorption channel, it is possible to prevent the gas between the wafer device area and the main body bearing part from being drawn away by the vacuum pump through the vacuum adsorption channel, thereby ensuring the structural stability of the semiconductor device located in the wafer device area, avoiding the device structure of the semiconductor device from changing due to vacuum adsorption, maintaining the structural stability of the device, and thus ensuring the accuracy of the test. For example, in an embodiment where the semiconductor device has a cavity and a diaphragm, the displacement of the diaphragm due to vacuum adsorption can be avoided during the test process, thereby improving the accuracy of the test. Moreover, the testing method can effectively, comprehensively and accurately test all semiconductor devices on the wafer, ensuring that the chips entering the subsequent process stage (for example, the packaging and testing stage) are all qualified chips, and avoiding invalid chips from entering the subsequent process and causing losses.

[0121] In some embodiments, the probe assembly adds an elastic design, and through the elastic probe fixing bracket and the related structural settings of the probe, when the wafer is tested, the pressure from the probe on the wafer can be reduced while the probe can be effectively tested, thereby avoiding damage to the device structure of the wafer. The probe pressure can also be controlled, and the stability of the probe pressure can be tested and improved, which can also help to improve the stability and / or accuracy of the test.

[0122] There are a few points to note: (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0123] (2) Unless there is a conflict, the features of the same embodiment or different embodiments of the present disclosure may be combined with each other.

[0124] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A wafer testing method, comprising: Providing a wafer, wherein the wafer has a wafer device region and a wafer edge region, wherein the wafer device region includes a semiconductor device, and the wafer edge region surrounds the wafer device region; A wafer testing device having a test table is provided, wherein the test table comprises a main body bearing part and an edge bearing part, wherein the edge bearing part surrounds the main body bearing part and comprises a vacuum adsorption channel and an isolation air release channel arranged at intervals; Placing the wafer on the test table of the wafer testing equipment, wherein the wafer device area is located on the main body supporting part; the wafer edge area is located on the edge supporting part, and the vacuum adsorption channel and the isolation air release channel each have an opening facing the wafer edge area; The gas in the vacuum adsorption channel and between the wafer edge area and the edge bearing part is extracted through the vacuum adsorption channel, so that the air pressure between the wafer edge area and the edge bearing part is lower than the ambient air pressure, thereby adsorbing and fixing the wafer on the test table, wherein the isolation air release channel is connected to the ambient air pressure, and the space between the wafer device area and the main body bearing part is separated from the vacuum adsorption channel; as well as The wafer is tested using a probe.

2. The wafer testing method according to claim 1, wherein the semiconductor device has a cavity and a diaphragm, and the cavity is located between the diaphragm and the main body bearing part, and the space between the wafer device area and the main body bearing part includes the cavity and the space at the contact interface between the wafer device area and the main body bearing part; During the test, the air pressure in the cavity is the same as the air pressure on the side of the diaphragm away from the cavity.

3. The wafer testing method according to claim 2, wherein the orthographic projection of the isolated venting channel on a reference plane parallel to the main surface of the wafer is located between the orthographic projection of the cavity on the reference plane and the orthographic projection of the vacuum adsorption channel on the reference plane.

4. The wafer testing method according to claim 2, wherein the air pressure on the side of the diaphragm away from the cavity is the ambient air pressure, and the space between the wafer device area and the main body supporting part is connected to the ambient air pressure through the isolation leakage channel.

5. The wafer testing method according to any one of claims 1 to 4, wherein the test table has a first surface and a second surface opposite to each other in a direction perpendicular to the main surface of the wafer, the first surface contacts the wafer, and the vacuum adsorption channel comprises: A first groove, recessed from the first surface of the test table toward the second surface; as well as The first connecting channel is communicated with the first groove and is connected to a vacuum pump. 6 . The wafer testing method according to claim 5 , wherein the first connecting channel extends from the first groove to a side wall of the testing table. 7 . The wafer testing method according to claim 5 , wherein the first groove is ring-shaped, or the first groove includes a plurality of first holes.

8. The wafer testing method according to any one of claims 1 to 4, wherein the isolated vent channel comprises: A second groove is recessed from a first surface of the test table contacting the wafer toward a second surface of the test table opposite to the first surface; as well as The second connecting channel is connected to the second groove and the ambient air pressure. 9 . The wafer testing method according to claim 8 , wherein the second trench is located in an upper portion of the test table, and the second connecting channel extends from a bottom of the second trench to the second surface of the test table. 10 . The wafer testing method according to claim 8 , wherein the second groove is ring-shaped, or the second groove includes a plurality of second holes.

11. A wafer testing method according to any one of claims 1-4, wherein the wafer testing equipment comprises a probe assembly, the probe assembly comprises the probe and an elastic probe fixing bracket, the elastic probe fixing bracket comprises a fixing portion and an elastic extension portion connected to each other, the elastic extension portion is elastically movable in a direction perpendicular to the main surface of the wafer, and the probe is fixed on the elastic extension portion. 12 . The wafer testing method according to claim 11 , wherein the fixing portion extends in a direction perpendicular to the main surface of the wafer, an initial angle between the elastic extension portion and the fixing portion is an obtuse angle, and an angle between the probe and the wafer is an acute angle.

13. The wafer testing method according to claim 12, wherein using the probe to test the wafer comprises: The probe is used to contact the wafer. In response to the reaction force of the wafer on the probe, the elastic extension portion that fixes the probe undergoes elastic displacement, and the probe slides from a first position to a second position on the wafer, wherein the sliding distance between the first position and the second position ranges from 10 microns to 30 microns.

14. A wafer testing device, comprising: A test table, configured to carry wafers during wafer testing, wherein the test table comprises a main body carrying portion and an edge carrying portion, the edge carrying portion surrounds the main body carrying portion and comprises a vacuum adsorption channel and an isolation air release channel arranged at intervals, the vacuum adsorption channel is configured to be connected to a vacuum pump, the isolation air release channel is configured to communicate with ambient air pressure, and is arranged on a side of the vacuum adsorption channel away from a side wall of the test table; as well as A probe assembly includes a probe configured to test the wafer during the wafer testing process.

15. The wafer testing equipment according to claim 14, wherein the probe assembly further comprises: The elastic probe fixing bracket includes a fixing portion and an elastic extending portion, wherein the elastic extending portion is configured to fix the probe and is elastically movable in a direction perpendicular to a main surface of the test table.

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