Method for forming contact hole
By first forming a first through hole to remove part of the gate structure during the production process of the shared contact hole, and then forming a second through hole below it, the problem of incomplete etching caused by by-product accumulation during etching is solved, and the product is improved yield.
Patent Information
- Application Number
- CN202411589071.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2025-02-18
AI Technical Summary
During the production of shared contact holes, by-products are easily accumulated at the bottom during etching, resulting in incomplete etching and affecting the yield of device products.
By first forming a first through hole to remove part of the gate structure, and then forming a second through hole with a width smaller than the first through hole below the first through hole, the heavily doped region at the bottom of the second through hole is exposed, ensuring the entire etching process The height of the gate structure being etched and the generation of by-products is reduced.
The generation of etching by-products is reduced, and the problem of insufficient etching due to by-product accumulation is avoided, thereby improving the yield of the product.
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Figure CN119480796A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for forming a contact hole. Background Art
[0002] In order to realize the local interconnection function between the gate, source and drain in static random access memory (SRAM), a large-sized contact hole structure pattern is introduced in the production of contact holes (CT). This type of contact hole is called a shared contact hole (share CT).
[0003] refer to Figure 1 , which shows a cross-sectional schematic diagram of the process of making a shared contact hole provided in the related art after etching is completed. For example, Figure 1 As shown, a shallow trench isolation (STI) structure 120 is formed in the substrate 110, and the STI structure 120 surrounds a first region 101 and a second region 102 spaced apart from each other. The first region 101 is used to form a first metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as "MOS") device, and the second region 102 is used to form a second MOS device (for example, the first MOS device may be a P (positive) type MOS device, and the second MOS device may be an N (negative) type MOS device), wherein:
[0004] The first MOS device includes a first gate 161, a work function layer 170 around and at the bottom of the first gate 161, an interface layer 141, a high dielectric constant layer 142 and a cap layer 143 are sequentially formed between the work function layer 170 and the substrate 110 from bottom to top, a doped region 1014 is formed in the substrate 110 on both sides of the first gate 161, and a metal silicide layer 130 is formed in the doped region 1014; the second MOS device includes a second gate 162, a work function layer 170 around and at the bottom of the second gate 162, an interface layer 141, a high dielectric constant layer 142 and a cap layer 143 are sequentially formed between the work function layer 170 and the substrate 110 from bottom to top, a germanium silicon (GeSi) epitaxial layer 1015 is formed in the substrate 110 on both sides of the second gate 162, and a metal silicide layer 130 is formed in the germanium silicon layer 1015. The first MOS device and the second MOS are covered by an inter-layer dielectric (ILD) layer 180, and an etch stop layer 150 is formed on the surface of the first gate 161, the second gate 162 and the substrate 110. After the etching process of the contact hole, a first through hole 301, a second through hole 302 and a third through hole 303 are formed in the ILD layer 180, and the first through hole 301, the second through hole 302 and the third through hole 303 are used to fill the metal layer to form a contact hole. Among them, the second through hole 302 is located on one side of the second gate 162 and the metal silicide layer 130 at the bottom is exposed, the third through hole 303 is located above the second gate 162 and the second gate 162 at the bottom is exposed, in the horizontal direction, the first through hole 301 occupies part of the area in the first gate 161 and part of the active area (active area, AA) of the first MOS device, and in the vertical direction, the metal silicide layer 130 at the bottom of the first through hole 301 is exposed. After the subsequent metal layer is filled, the contact hole formed in the first through hole 301 can electrically connect the first gate 161 and the source or drain (metal silicide layer 130) on one side thereof, so the contact hole formed in the first through hole 301 is a shared contact hole.
[0005] However, if Figure 1 As shown, since the first gate 161 is a metal gate (MG), during the process of etching to form the first through hole 301, after the first gate 161 is etched, the metal-containing byproducts generated are deposited in the active area in the left half of the shared contact hole. Due to the insufficient removal ability of the byproducts during the etching exhaust process, it is difficult to completely remove them, resulting in a slow etching of the area. There is a certain probability that the area cannot be completely opened after the etching is completed, resulting in the problem of the contact hole being disconnected, affecting the yield of the device product. Summary of the invention
[0006] The present application provides a method for forming a contact hole, which can solve the problem that in the method for forming a shared contact hole provided in the related art, byproducts are easily accumulated at the bottom when etching a through hole during the manufacturing process, thereby causing incomplete etching. The method comprises:
[0007] A substrate is provided, wherein an STI structure is formed in the substrate, wherein the region surrounded by the STI structure includes a first region and a second region when viewed from a top view, wherein a first MOS device is formed in the first region, wherein a second MOS device is formed in the second region, wherein the first MOS device includes a first gate structure and heavily doped regions formed in the substrate on both sides thereof, wherein the second MOS device includes a second gate structure and germanium silicon epitaxial layers formed in the substrate on both sides thereof, wherein an interlayer dielectric layer is covered on the substrate, wherein the first MOS device and the second MOS device are covered in the interlayer dielectric layer, wherein the first gate structure includes a first metal gate and work function layers on the surrounding side and the bottom thereof;
[0008] Performing etching by a photolithography process to remove a predetermined area of the first gate structure, and forming a first through hole in the interlayer dielectric layer, wherein the first through hole occupies a predetermined area on one side of the first gate structure and a predetermined area of the active area on the side in a lateral direction, and the bottom of the first through hole is higher than the bottom of the first gate structure;
[0009] Etching is performed by a photolithography process to form a second through hole below the first through hole and in communication with the first through hole, wherein the heavily doped region at the bottom of the second through hole is exposed, and the second through hole and the first gate structure do not have an overlapping region in a lateral direction;
[0010] A metal layer is filled in the first through hole and the second through hole to form a shared contact hole. When the first MOS device is working, the shared contact hole electrically connects the exposed heavily doped region to the gate structure.
[0011] In some embodiments, the second gate structure includes a second metal gate and work function layers around and at the bottom of the second metal gate.
[0012] In some embodiments, the first metal gate and the second metal gate include aluminum metal layers.
[0013] In some embodiments, it is characterized in that an etch stop layer is formed on the surface of the substrate and the peripheral sides of the first gate structure and the second gate structure.
[0014] In some embodiments, the etch stop layer includes a nitride layer.
[0015] In some embodiments, an interface layer, a high dielectric constant layer and a cap layer are sequentially formed between the first gate structure and the substrate from bottom to top, and an interface layer, a high dielectric constant layer and a cap layer are sequentially formed between the second gate structure and the substrate from bottom to top.
[0016] In some embodiments, the high dielectric constant layer includes at least one of hafnium oxide, tantalum oxide, strontium titanium oxide, hafnium silicon oxide, and zirconium oxide.
[0017] In some embodiments, the interface layer includes an oxide layer.
[0018] In some embodiments, the cap layer includes a nitride layer.
[0019] The technical solution of this application has at least the following advantages:
[0020] In the process of making the shared contact hole, a first through hole is formed by a first etching and a part of the gate structure is removed to expose it, and then a second through hole is formed below the first through hole with a width smaller than the first through hole by a second etching and the heavily doped area at the bottom of the second through hole is exposed. Since the through hole formed in the second etching has no overlapping area with the gate structure, the height of the gate structure etched is reduced during the entire etching process, thereby reducing the exposed area of the gate structure and further reducing etching by-products, thereby solving the problem of insufficient etching caused by a large number of by-products caused by etching the gate structure, and improving the product yield to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0022] Figure 1 It is a cross-sectional schematic diagram of a shared contact hole manufacturing process provided in the related art after etching is completed;
[0023] Figure 2 It is a three-dimensional schematic diagram of the manufacturing process of the shared contact hole provided in the related art after etching is completed;
[0024] Figure 3 is a flow chart of a method for forming a contact hole provided by an exemplary embodiment of the present application;
[0025] Figures 4 to 5 It is a schematic diagram of the etching process of a contact hole provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0026] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0027] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0028] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0029] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0030] refer to Figure 2 , which shows a three-dimensional schematic diagram of the process of making a shared contact hole provided in the related art after etching is completed, for example, Figure 2 As shown: the length of the etched through hole 300 of the shared contact hole falling on the active area 100 is a, the length falling on the gate structure (including the gate and its surrounding and bottom work function layer) 160 is b, the etched height in the gate structure 160 is c, and the short axis of the etched through hole 300 falling on one side of the gate structure 160 is d.
[0031] According to the above, it can be obtained that the volume V of the etched area in the gate structure 160 is poly =V poly=K1·b·c·d. Wherein, K1 is a coefficient related to calculating the contact surface sector area. The total volume V to be etched during the etching process is: V=K2·(a+b)·b·c·d. Wherein, K2 is a coefficient related to calculating the ellipse area. Therefore, when the total etching volume remains unchanged, the amount of byproducts can be reduced by reducing the exposed area of the gate structure 160.
[0032] refer to Figure 3 , which shows a flow chart of a method for forming a contact hole provided by an exemplary embodiment of the present application, such as Figure 3 As shown, the method includes:
[0033] Step S1, providing a substrate, in which an STI structure is formed, and when viewed from a top view, an area surrounded by the STI structure includes a first area and a second area, a first MOS device is formed in the first area, and a second MOS device is formed in the second area, the first MOS device includes a first gate structure and heavily doped regions formed in the substrate on both sides thereof, the second MOS device includes a second gate structure and germanium silicon epitaxial layers formed in the substrate on both sides thereof, the substrate is covered with an interlayer dielectric layer, the first MOS device and the second MOS device are covered in the interlayer dielectric layer, and the first gate structure includes a first metal gate and work function layers on its surrounding sides and bottom.
[0034] Step S2, etching is performed through a photolithography process to remove a predetermined area of the first gate structure, and a first through hole is formed in the interlayer dielectric layer. In the lateral direction, the first through hole occupies a predetermined area on one side of the first gate structure and a predetermined area of the active area on the side, and the bottom of the first through hole is higher than the bottom of the first gate structure.
[0035] refer to Figure 4 , which shows a cross-sectional schematic diagram after the first through hole is formed. Figure 4 As shown, an STI structure 220 is formed in the substrate 210. When viewed from a top view, the area surrounded by the STI structure 220 includes a first area 201 and a second area 202. A first MOS device is formed in the first area 201, and a second MOS device is formed in the second area 202. The first MOS device includes a first gate structure and heavily doped regions 2014 formed in the substrate 210 on both sides thereof. The second MOS device includes a second gate structure and germanium silicon epitaxial layers 2015 formed in the substrate 210 on both sides thereof. The substrate 210 is covered with an interlayer dielectric layer, and the first MOS device and the second MOS device are covered in the interlayer dielectric layer.
[0036] The first MOS device may be a P-type MOS device, and the second MOS device may be an N-type MOS device; the first gate structure includes a first metal gate 261 and a work function layer on the side and bottom thereof, and the second gate structure includes a second metal gate 262 and a work function layer on the side and bottom thereof, and the first metal gate 261 and the second metal gate 262 may include an aluminum (Al) metal layer; the work function layer may include a nitride layer, for example, Figure 4 As shown, the work function layer may include a tantalum nitride (TaN) layer 271, a titanium nitride (TiN) layer 272 and a tantalum nitride layer 273 from the inside out; a metal silicide layer 230 may be formed in the heavily doped region 2014, and when the first MOS device is working, the heavily doped regions 2014 on both sides may serve as the source and drain of the device. Similarly, a metal silicide layer 230 may be formed in the silicon germanium epitaxial layer 2015, and when the second MOS device is working, the silicon germanium epitaxial layer 2015 on both sides may serve as the source and drain of the device; the interlayer dielectric layer includes a first interlayer dielectric layer 281 and a second interlayer dielectric layer 282 from bottom to top, and the first MOS device and the second MOS device are covered in the first interlayer dielectric layer 281, and the peripheral side of the first gate structure, the peripheral side of the second gate structure and the substrate 210 are connected to the substrate 210. An etch stop layer 250 is formed on the surface of the substrate 210, and the etch stop layer 250 may include a nitride layer (for example, a silicon nitride (Si3N4) layer); an interface layer 241, a high dielectric constant layer (composed of a material with a dielectric constant k greater than 10) 242 and a cap layer 242 are formed in sequence from bottom to top between the first gate structure, the second gate structure and the substrate 210, and the high dielectric constant layer 242 may include at least one of hafnium oxide (HfO2), tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium silicon oxide (HfSiO), and zirconium oxide (ZrO2), the interface layer 241 may include an oxide layer (for example, a silicon dioxide (SiO2) layer may be formed on the substrate 210 by a thermal oxidation process), and the cap layer 242 may include a nitride layer (for example, a titanium nitride layer).
[0037] Optionally, a deep well region 2011 is formed in the first region 201, a well region 2013 is formed in the deep well region 2011, a heavily doped region 2014 is formed in the well region 2013, a lightly doped drain (LDD) region 2017 is also formed in the substrate 210 on both sides of the first gate structure, and a pocket injection region 2015 is formed below the LDD region 2017; a well region 2012 is formed in the second region 202, a germanium silicon epitaxial layer 2015 is formed in the well region 2012, an LDD region 2018 is also formed in the substrate 210 on both sides of the second gate structure, and a pocket injection region 2016 is formed below the LDD region 2018.
[0038] Exemplarily, a photoresist may be covered on the second interlayer dielectric layer 282, and the photoresist in the first target area (the area corresponding to the first through hole 401) may be removed by exposure and development in sequence, and etching may be performed to a predetermined depth in the first gate structure (the first gate structure is not etched to the bottom) to form the first through hole 401. The first through hole 401 has an overlapping area with the first gate structure, and occupies a predetermined area on one side of the first gate structure and a predetermined area of the active area on the side in the lateral direction, and its bottom is higher than the bottom of the first gate structure.
[0039] Step S3, etching is performed by photolithography to form a second through hole below the first through hole and connected thereto, the heavily doped region at the bottom of the second through hole is exposed, and the second through hole has no overlapping area with the first gate structure in the lateral direction.
[0040] refer to Figure 5 , which shows a cross-sectional schematic diagram after the second through hole is formed. Figure 5 As shown, a photoresist may be covered on the second interlayer dielectric layer 282, and the photoresist in the second target area (the area corresponding to the second through hole 402) may be removed by exposure and development in sequence, and etching may be performed until the heavily doped area 2014 is exposed, thereby forming the second through hole 402. The second through hole 402 is formed in the first through hole 401 and communicates therewith, and the heavily doped area at the bottom of the second through hole 402 is exposed, and the second through hole 402 does not have an overlapping area with the first gate structure in the lateral direction.
[0041] Step S4, filling the first through hole and the second through hole with a metal layer to form a shared contact hole. When the first MOS device is working, the shared contact hole electrically connects the exposed heavily doped region to the gate structure.
[0042] To sum up, in the embodiment of the present application, during the process of manufacturing the shared contact hole, a first through hole is first formed by etching and a portion of the gate structure is removed to expose it, and then a second through hole with a width smaller than the first through hole is formed below the first through hole by etching for the second time and the heavily doped region at the bottom of the second through hole is exposed. Since the through hole formed in the second etching does not have an overlapping area with the gate structure, the height of the gate structure etched is reduced during the entire etching process, thereby reducing the exposed area of the gate structure and further reducing etching by-products, thereby solving the problem of insufficient etching due to a large number of by-products caused by etching the gate structure, and improving the product yield to a certain extent.
[0043] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for forming a contact hole, characterized in that: include: A substrate is provided, wherein an STI structure is formed in the substrate, wherein the region surrounded by the STI structure includes a first region and a second region when viewed from a top view, wherein a first MOS device is formed in the first region, wherein a second MOS device is formed in the second region, wherein the first MOS device includes a first gate structure and heavily doped regions formed in the substrate on both sides thereof, wherein the second MOS device includes a second gate structure and germanium silicon epitaxial layers formed in the substrate on both sides thereof, wherein an interlayer dielectric layer is covered on the substrate, wherein the first MOS device and the second MOS device are covered in the interlayer dielectric layer, wherein the first gate structure includes a first metal gate and work function layers on the surrounding side and the bottom thereof; Performing etching by a photolithography process to remove a predetermined area of the first gate structure, and forming a first through hole in the interlayer dielectric layer, wherein the first through hole occupies a predetermined area on one side of the first gate structure and a predetermined area of the active area on the side in a lateral direction, and the bottom of the first through hole is higher than the bottom of the first gate structure; Etching is performed by a photolithography process to form a second through hole below the first through hole and in communication with the first through hole, wherein the heavily doped region at the bottom of the second through hole is exposed, and the second through hole and the first gate structure do not have an overlapping region in a lateral direction; A metal layer is filled in the first through hole and the second through hole to form a shared contact hole. When the first MOS device is working, the shared contact hole electrically connects the exposed heavily doped region to the gate structure.
2. The method according to claim 1, characterized in that: The second gate structure includes a second metal gate and work function layers on the periphery and bottom of the second metal gate.
3. The method according to claim 2, characterized in that The first metal gate and the second metal gate include aluminum metal layers.
4. The method according to claim 3, characterized in that An etch stop layer is formed on the substrate surface and around the first gate structure and the second gate structure.
5. The method according to claim 4, characterized in that The etch stop layer includes a nitride layer.
6. The method according to any one of claims 1 to 5, characterized in that: An interface layer, a high dielectric constant layer and a cap layer are sequentially formed between the first gate structure and the substrate from bottom to top, and an interface layer, a high dielectric constant layer and a cap layer are sequentially formed between the second gate structure and the substrate from bottom to top.
7. The method according to claim 6, characterized in that The high dielectric constant layer includes at least one of hafnium oxide, tantalum oxide, strontium titanium oxide, hafnium silicon oxide, and zirconium oxide.
8. The method according to claim 7, characterized in that The interface layer includes an oxide layer.
9. The method according to claim 8, characterized in that The cap layer includes a nitride layer.