Wafer structure and chip

Abstract

The invention relates to the technical field of wafer manufacturing, and discloses a wafer structure and a chip. The wafer structure comprises a wafer body, the wafer body comprises a cutting channel and crystal grains, and the cutting channel is located between two adjacent crystal grains; wherein the crystal grains comprise functional crystal grains and test crystal grains, and the test crystal grains are used for process testing of the wafer structure; wherein the test crystal grain comprises a test crystal grain main body and a plurality of wafer test pins, and the plurality of wafer test pins are distributed on two sides of the test crystal grain main body and are used for being connected with a circuit layer of a wafer main body. According to the wafer structure disclosed by the invention, the test crystal grains are arranged, so that the Testkey arranged in the cutting channel in the related technology is eliminated, the width of the cutting groove can be reduced, the available area of the wafer body is increased, the number of single functional crystal grains is increased, the utilization rate of the wafer body is increased, and the production cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of wafer manufacturing technology, for example, to a wafer structure and a chip. Background Art

[0002] In chip manufacturing, the wafer is divided into multiple dies by cutting along the cutting path, and the individual dies are cut along the cutting path to obtain independent dies, and the individual dies are packaged to obtain chips. Figure 1 and Figure 2 , which is a schematic diagram of the distribution of crystal grains 13 and cutting lanes 12 in a single exposure area 11 of a wafer structure in the related art.

[0003] In the related technology, combined Figure 1 and Figure 2 As shown, according to the requirements of the wafer process, a test unit (Test-key 14) for testing the wafer process needs to be arranged inside the cutting path 12 to meet the setting of the test pins required in the cutting path. In order to be able to set the test unit, the width of the cutting path needs to be designed to be 50um to 60um to meet the arrangement requirements of the Test-key 14.

[0004] In addition, the insulating layer of the wafer in the related technology uses Low-K (low dielectric constant material). Since Low-K material has low mechanical strength and thermal stability, Low-K scribing technology is limited to laser grooving + blade scribing. In order to ensure that the chip is not damaged during the scribing process, the width of the cutting path needs to be further increased. The larger the width of the cutting path, the smaller the effective area available on the wafer, thereby reducing the utilization rate of the wafer. If the cutting path is too small, the risk of damaging the grain will increase. Summary of the invention

[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0006] The embodiments of the present disclosure provide a wafer structure and a chip to solve the risk problem of excessive width of the cutting lanes, which reduces the utilization rate of the wafer.

[0007] In some embodiments, a wafer structure is provided, including: a wafer body, the wafer body including cutting paths and grains, the cutting paths being located between two adjacent grains; wherein the grains include functional grains and test grains, the test grains being used for process testing of the wafer structure; wherein the test grains include: a test grain body and a plurality of wafer test pins, the plurality of wafer test pins being distributed on both sides of the test grain body for connecting to the circuit layer of the wafer body.

[0008] Optionally, the test die further includes: a test die body; a plurality of functional test pins, which are arranged on the test die body and are used to connect with the functional die; wherein the wafer test pins are distributed on both sides of the functional test pins.

[0009] Optionally, the functional die includes: a functional die body; a die pin, which is arranged on the functional die body, and the die pin is used to connect with an external circuit; wherein the wafer pin and the die test pin have the same size.

[0010] Optionally, the width of the cutting road ranges from 15 um to 30 um.

[0011] Optionally, the sum of the areas of the test dies is less than or equal to 10% of the area of ​​the wafer body.

[0012] Optionally, the size of a single test die is the same as the size of a single functional die.

[0013] Optionally, the sum of areas of all test dies included in the wafer body is less than or equal to 10% of the area of ​​the wafer body.

[0014] Optionally, the wafer structure further includes: a reinforcement track, which is arranged on the peripheral side wall of the grain and is located within the cutting track.

[0015] Optionally, the width of the reinforcement path has a value range of: D×20%≤d≤D×50%, wherein d is the width of the reinforcement path, and D is the width of the cutting path.

[0016] Optionally, the wafer structure further includes: a protection ring, which is arranged on the peripheral side of the crystal grain, and the protection ring is located between the reinforcement channel and the side wall of the crystal grain.

[0017] Optionally, the wafer structure further includes: an isolation layer, which is arranged on the peripheral side wall of the grain, and the reinforcement path is located between the isolation layer and the cutting path.

[0018] Optionally, along the depth direction of the cutting street, the height of the isolation layer is greater than or equal to the height of the grain.

[0019] Optionally, the thickness of the isolation layer ranges from 1 um to 2 um.

[0020] Optionally, the wafer body includes multiple shots, each shot includes multiple functional grains; wherein a single shot is provided with one or more test grains; or multiple shots share one or more test grains for process testing.

[0021] In some embodiments, a crystal grain is provided, wherein the crystal grain is obtained by cutting along a cutting groove of a wafer structure as described in any of the above embodiments by means of laser stealth cutting.

[0022] The wafer structure and chip provided by the embodiments of the present disclosure can achieve the following technical effects:

[0023] The wafer structure provided by the embodiment of the present disclosure can reduce the width of the cutting groove by setting the test grains, thereby eliminating the test-key set in the cutting path in the related art. In this way, the process test of the wafer structure can be realized by using the test grains, and by reducing the width of the cutting grooves, the area of ​​the grain body occupied by the cutting grooves is reduced, thereby increasing the available area of ​​the wafer body, increasing the number of single functional grains, improving the utilization rate of the wafer body, and reducing the production cost.

[0024] By controlling the proportion of the area occupied by the test grains, the utilization rate of the wafer body can be improved. In this way, the test requirements of the wafer structure can be met, the utilization rate of the wafer body can be improved, and the production cost can be reduced. By setting the sum of the areas of all the test grains included in the wafer body to be less than or equal to 10% of the area of ​​the wafer body, the area saved by reducing the width of the cutting groove is much larger than the area of ​​the test grain position, thereby effectively increasing the number of functional grains and reducing production costs.

[0025] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0027] Figure 1 It is a structural schematic diagram of a single shot in a wafer structure in the related art;

[0028] Figure 2 yes Figure 1 Schematic diagram of the distribution of some grains and cutting paths;

[0029] Figure 3 is a structural schematic diagram of a wafer structure provided by an embodiment of the present disclosure;

[0030] Figure 4 is a structural schematic diagram of a single shot in a wafer structure provided by an embodiment of the present disclosure;

[0031] Figure 5 yes Figure 4 A schematic diagram showing the distribution of some grains and cutting paths in one embodiment is shown;

[0032] Figure 6 yes Figure 4A schematic diagram showing the distribution of some crystal grains and dicing lanes in another embodiment shown;

[0033] Figure 7 yes Figure 4 An enlarged schematic diagram of A in the illustrated embodiment;

[0034] Figure 8 yes Figure 4 A schematic diagram of the structure of a test grain in one embodiment is shown;

[0035] Fig. 9 yes Figure 4 A schematic diagram of the structure of a functional grain in one embodiment is shown;

[0036] Fig.10 is a cross-sectional schematic diagram of a cutting path in one embodiment of the present disclosure;

[0037] Fig.11 is a cross-sectional schematic diagram of a cutting path in yet another embodiment of the present disclosure;

[0038] Fig.12 It is a schematic diagram of multiple shots sharing multiple test dies in one embodiment of the present disclosure.

[0039] Reference numerals in the related art:

[0040] 11 exposure area; 12 cutting road; 13 grain; 14 test-key;

[0041] Reference numerals in the embodiments of the present disclosure:

[0042] 1 Wafer structure;

[0043] 100 wafer body; 102 exposure area; 110 cutting road; 120 grain; 130 functional grain; 132 functional grain body; 134 grain pin; 140 test grain; 150 test grain body; 160 functional test pin; 161 first pin; 162 second pin; 170 wafer test pin; 171 first PAD; 172 second PAD; 173 third PAD; 174 fourth PAD; 175 fifth PAD; 180 circuit layer;

[0044] 200 reinforcement road; 300 protection ring; 400 isolation layer; 410 protrusion. DETAILED DESCRIPTION

[0045] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and wafer structures can be simplified for display.

[0046] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0047] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated wafer structures, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation. Moreover, in addition to being used to indicate orientations or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0048] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two wafer structures, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0049] Unless otherwise stated, the term "plurality" means two or more.

[0050] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0051] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0052] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0053] In some embodiments, in combination Figures 3 to 11 As shown, a wafer structure 1 is provided, including: a wafer body 100 and a reinforcement road 200. The wafer body 100 includes a cutting road 110 and a grain 120, and the cutting road 110 is located between two adjacent grains 120. Among them, the grain 120 includes a functional grain 130 and a test grain 140, and the test grain 140 is used for process testing of the wafer structure 1. The test grain 140 includes: a test grain body 150; a plurality of wafer test pins 170, which are arranged on the test grain body 150 and are used to connect with the circuit layer 180 of the wafer body. Among them, the plurality of wafer test pins 170 are distributed on both sides of the test grain body 150.

[0054] The wafer structure 1 provided in the embodiment of the present disclosure, by setting a test grain 140, thereby canceling the test-key set in the cutting road 110 in the related art, thereby reducing the width of the cutting groove. In this way, the process test of the wafer structure 1 can be realized by using the test grain 140, and by reducing the width of the cutting groove, the area of ​​the grain 120 body occupied by the cutting groove is reduced, thereby increasing the available area of ​​the wafer body 100, increasing the number of single functional grains 130, improving the utilization rate of the wafer body 100, and reducing the production cost. Furthermore, the wafer test pin 170 of the test grain 140 is used to test the wafer process. By respectively setting a plurality of wafer test pins 170 on both sides of the test grain body 150, it is convenient to connect the circuit layer to be tested and realize reasonable wiring.

[0055] Optionally, combined Figure 8 As shown, the test die 140 further includes: a plurality of functional test pins 160 , which are disposed on the test die body 150 and are used to connect with the functional die 130 ; wherein the wafer test pins 170 are distributed on both sides of the functional test pins 160 .

[0056] In this embodiment, the test chip includes a functional test pin 160 and a wafer test pin 170. The functional test pin 160 is used to test the function of a single die 120. In this way, by providing the functional test pin 160 and the wafer test pin 170, the performance of the functional die 130 and the connection reliability of the wafer main body circuit layer 180 can be fully evaluated.

[0057] Optionally, combined Figure 8The test die body 150 shown includes a first end and a second end, and the first end and the second end are opposite sides of the test die body 150. Part of the plurality of wafer test pins 170 are located in a region of the test die body 150 close to the first end. Part of the plurality of wafer test pins 170 are located in a region of the test die body 150 close to the second end. A plurality of functional test pins 160 are located in the middle region. By respectively arranging different types of test pins at the two ends and the middle region, comprehensive testing of different functional regions on the wafer structure 1 can be achieved, thereby improving test coverage.

[0058] Optionally, combined Figure 8 The functional test pin 160 includes a first pin 161 and a second pin 162, which are arranged at intervals. The first pin 161 and the second pin 162 are respectively connected to the pins of the functional die 130 to test the performance of the functional die 130.

[0059] Optionally, combined Figure 8 As shown, the wafer test pin 170 includes a first PAD171 (pad), a second PAD172, a third PAD173, a fourth PAD174 and a fifth PAD175. The number of the first PAD171, the second PAD172, the third PAD173, the fourth PAD174 and the fifth PAD175 is two respectively, and they are symmetrically distributed at the first end and the second end of the test die body 150. The first PAD171 is connected to the first circuit layer 180 of the wafer test, the second PAD172 is connected to the second circuit layer 180 of the wafer test, the third PAD173 is connected to the third circuit layer 180 of the wafer test, the fourth PAD174 is connected to the fourth circuit layer 180 of the wafer test, and the fifth PAD175 is connected to the fifth circuit layer 180 of the wafer test. By setting multiple PADs, with each PAD connected to a different circuit layer 180 , multiple circuit layers 180 of the wafer structure 1 can be tested independently to more comprehensively evaluate the performance of the wafer structure 1 and ensure the quality and functionality of each circuit layer 180 .

[0060] Optionally, combined Fig. 9 As shown, the functional die 130 includes: a functional die body 132 and a die pin 134 disposed on the functional die body 132. The die pin 134 of the functional die body 132 is used to connect the internal circuit of the die 120 with the external circuit.

[0061] Optionally, the wafer pins 134 and the die test pins 170 are the same size.

[0062] In this embodiment, by setting the wafer pins 134 and the die test pins 170 to be consistent in size, on the one hand, the manufacturing and production of the wafer structure is facilitated; on the other hand, the pins are set consistently, which facilitates the test operation.

[0063] It should be noted that, in the case where the die test pin 170 includes a plurality of PADs, the same size referred to here means that the size of the wafer pin 134 is the same as that of a single PAD.

[0064] Optionally, the sizes of the wafer pins 134 and the die test pins 170 may be different, and may be specifically designed according to the specific application scenario of the wafer structure.

[0065] Optionally, the sum of the areas of the test dies 140 is less than or equal to 10% of the area of ​​the wafer body 100 .

[0066] In this embodiment, the sum of the areas of all the test grains 140 included in the wafer body 100 is less than or equal to 10% of the area of ​​the wafer body 100. The utilization rate of the wafer body is improved by controlling the proportion of the area occupied by the test grains 140. In this way, it is possible to meet the test requirements of the wafer structure 1, improve the utilization rate of the wafer body, and reduce production costs. By setting the sum of the areas of all the test grains 140 included in the wafer body 100 to be less than or equal to 10% of the area of ​​the wafer body 100, the area saved by reducing the width of the cutting groove is much larger than the area of ​​the test grains 140, thereby effectively increasing the number of functional grains 130 and reducing production costs.

[0067] Optionally, the width D of the cutting street 110 ranges from 15 um to 30 um.

[0068] In this embodiment, the test die 140 is provided to replace the test-key in the related art, so that the width of the cutting groove can be in the range of 15um to 30um. In this way, the available area of ​​the die 120 body can be provided, so as to reduce the production cost.

[0069] Optionally, the width of the cutting road 110 includes but is not limited to: 15um, 16um, 17um, 18um, 19um, 20um, 21um, 22um, 23um, 24um, 25um, 26um, 27um, 28um, 29um or 30um.

[0070] Optionally, combined Figure 4 As shown, the size of a single test die 140 is the same as the size of a single functional die 130 .

[0071] In this embodiment, by setting the size of a single test die 140 to be the same as the size of a single functional die 130 , it is convenient to divide the die 120 on the main body of the die 120 , and to facilitate subsequent cutting and manufacturing, thereby reducing production costs.

[0072] Optionally, the fewer the number of test dies 140, the better, to reduce the occupancy rate of the wafer body. The specific number of settings can meet the wafer process safety test, and the number is not specifically limited here.

[0073] Optionally, combined Figure 6 , Figure 7 and Fig. 9 As shown, by providing a reinforcement path 200 on the side wall of the crystal grain 120 and in the cutting groove, the structural strength of the crystal grain 120 is enhanced by providing the reinforcement path 200, the stress resistance of the wafer after cutting is ensured, and the stress to which the chip is subjected during cutting and subsequent operations is reduced, thereby reducing the risk of cracks and damage. In addition, during the process of cutting the wafer, the reinforcement path 200 can prevent the cutting cracks from spreading from the cutting path 110 to the functional area, thereby protecting the integrity of the chip. This helps to reduce short circuit or open circuit problems caused by cracks and improve the electrical performance of the chip. In addition, it prevents the circuit layer 180 of the crystal grain 120 from being cut during the cutting process, thereby enhancing the protection of the crystal grain 120.

[0074] Optionally, combined Fig.10 As shown, the value range of the width of the reinforcement channel 200 is: D×20%≤d≤D×50%, where d is the width of the reinforcement channel 200 and D is the width of the cutting groove.

[0075] In this embodiment, by reasonably setting the width of the reinforcement channel 200, sufficient mechanical strength is provided to support the sidewalls of the grains 120 on the wafer, especially during deep trench isolation or cutting, which helps to prevent sidewall collapse or cracks. In addition, it helps to evenly disperse the stress generated during processing or use, reduce local stress concentration, and thus reduce the risk of damage to the grains 120. The wider reinforcement channel 200 can prevent over-etching during deep trench etching and protect the sidewalls of the grains 120 from excessive erosion.

[0076] Optionally, specific values ​​of the width of the reinforcement channel 200 include but are not limited to: D×20%, D×25%, D×30%, D×35%, D×40%, D×45% or D×50%.

[0077] Optionally, a Poly dummy (polycrystalline silicon structure) is used to set a reinforcement path 200 on the side wall of the grain 120. Polydummy is a virtual polycrystalline silicon structure that is unrelated to actual electronic components and is inserted into different areas of the wafer to fill empty spaces or adjust process steps. The use of Poly dummy as the reinforcement path 200 reduces defects caused by mechanical stress during the manufacturing process, thereby improving the overall yield. And under long-term use or environmental stress (such as temperature changes, vibrations, etc.), the reinforcement path 200 helps to maintain the stability of the chip structure, thereby improving the reliability of the product. In different areas of the wafer, uneven stress may be generated due to process deviations or design reasons. The polysilicon reinforcement path 200 can help balance these stresses and reduce defects caused by stress concentration.

[0078] Optionally, the width of the reinforcement channel 200 may be reasonably set according to the size of the die 120 and process requirements.

[0079] Optionally, combined Figure 7 and Fig. 9 As shown, the wafer structure 1 further includes: a protection ring 300 , which is disposed on the peripheral side of the die 120 , and the protection ring 300 is located between the reinforcement channel 200 and the side wall of the die 120 .

[0080] In this embodiment, the protection ring 300 is used to protect the edge of the die 120, and is located between the die 120 and the cutting groove to prevent the die 120 from being mechanically damaged during the cutting process, thereby improving the protection effect on the die 120. In addition, the protection ring 300 can prevent moisture from invading the inside of the die 120 from the cutting side, thereby protecting the die 120 from being affected by the environmental humidity.

[0081] Optionally, the guard ring 300 (Sealring) includes an annular diffusion region (Diff) and an annular metal contact hole (Metal Contact Via). The annular diffusion region is usually composed of a doped silicon layer, which surrounds the edge of the grain 120 to form a continuous annular structure. The annular metal contact hole (Metal Contact Via) is a through hole formed on the silicon wafer for connecting different levels of metal. The annular metal contact hole connects the annular diffusion region with the upper metal layer to form a closed electrical connection ring, thereby enhancing the mechanical and electrical integrity of the guard ring 300.

[0082] Optionally, combined Figure 6 , Figure 7 and Fig.11 As shown, the wafer structure 1 further includes: an isolation layer 400 disposed on the peripheral sidewall of the die 120 , and the reinforcement road 200 is located between the isolation layer 400 and the cutting road 110 .

[0083] In this embodiment, an isolation layer 400 is disposed around the peripheral sidewall of each die 120 , and the isolation layer 400 is in contact with the sidewall of the cutting groove.

[0084] Optionally, combined Figure 7 and Fig. 9 As shown, the protection ring 300 is arranged on the peripheral side of the die 120 , the reinforcement channel 200 is located between the protection ring 300 and the isolation layer 400 , and a three-layer protection structure is arranged to enhance the protection of the die 120 and improve the reliability of the die 120 .

[0085] Combination Figure 7 and Fig.11 As shown, by adopting the wafer structure 1 provided by the present disclosure, an isolation layer 400 is provided on the peripheral side of the grain 120 and is located on the side wall of the cutting groove. The isolation layer 400 can be used to isolate the grain 120 to prevent short circuits that may occur during cutting or subsequent use, thereby protecting the circuit layer 180 of the grain 120, improving the reliability and safety of removing the PI material from the cutting groove part, and protecting the reliability of the circuit layer 180. And through the protective effect of the isolation layer 400 on the grain 120, the stability of the wafer reduction process and the safety of the grain 120 can be improved.

[0086] Optionally, the isolation layer 400 is a PI (Polyimide) isolation layer 400. The PI isolation layer 400 has good mechanical strength and flexibility, and can withstand high temperature processing during the wafer manufacturing process. In this way, it can prevent external moisture from entering the circuit layer 180 of the die 120, and can also protect the circuit layer 180 from being damaged during the reduction process.

[0087] Optionally, combined Fig.11 As shown, along the depth direction of the scribe line 110 , the height of the isolation layer 400 is greater than or equal to the height of the die 120 .

[0088] In this embodiment, by setting the height of the isolation layer 400 to be greater than or equal to the height of the grain 120, the isolation layer 400 can extend from the bottom of the grain 120 to or beyond the top of the grain 120, thereby improving the coverage effect of the entire side wall of the grain 120, so as to prevent debris, dust or other contaminants generated during the cutting process from contacting the side wall of the grain 120, thereby avoiding potential electrical short circuits or functional damage, and improving the protection of the grain 120.

[0089] Optionally, the thickness of the isolation layer 400 ranges from 1 um to 2 um.

[0090] In this embodiment, the isolation layer 400 with a thickness of 1 um to 2 um can ensure good electrical insulation performance and maintain structural stability.

[0091] During the specific implementation process, the thickness of the isolation layer 400 can be reasonably set according to different application environments to meet the isolation requirements, which will not be elaborated here.

[0092] Optionally, specific values ​​of the thickness of the isolation layer 400 include but are not limited to: 1um, 1.2um, 1.5um, 1.6um or 2um.

[0093] In some embodiments, in combination Fig.11 As shown, the isolation layer 400 includes a protrusion 410, and the protrusion 410 is located on one side of the opening of the cutting groove.

[0094] In this embodiment, a protrusion 410 extending toward the inside of the cutting groove is provided on the side wall of the isolation layer 400 at one end of the opening of the cutting groove. In this way, there are protrusions 410 extending along the length direction of the cutting groove on both sides of the opening of the cutting groove. By providing the protrusions 410, the protrusions 410 play a role in protecting the grains 120 during the decrementing process.

[0095] Optionally, the shape of the protrusion 410 includes but is not limited to: circular, elliptical, square or triangular, etc., which is selected according to the material properties and manufacturing process of the isolation layer 400.

[0096] Optionally, the protrusions 410 are evenly distributed along the extending direction of the cutting groove or arranged in a specific pattern, for example, the density of the protrusions 410 is increased in the stress concentrated area to improve the local strength.

[0097] In some embodiments, along the width direction of the opening of the cutting groove, the height of the protrusion 410 ranges from 1 um to 3 um.

[0098] In this embodiment, the height of the protrusion 410 is set to 1um to 3um. On the one hand, by setting the protrusion 410 of a suitable height, the strength and stability of the structure are improved. On the other hand, the space at the opening of the cutting groove minus the height of the protrusion 410 can meet the cutting process requirements, so that the grain 120 can be cut smoothly.

[0099] The height of the protrusion 410 can be adjusted according to different cutting process requirements to meet different production needs.

[0100] Optionally, specific values ​​of the height of the protrusion 410 include but are not limited to: 1um, 1.5um, 2um, 2.5um or 3um.

[0101] In some embodiments, the width of the opening of the cutting groove ranges from 8 um to 14 um.

[0102] In this embodiment, the width of the opening of the cutting groove is set to 8um to 14um to meet the implementation of the cutting process.

[0103] Specifically, the width of the opening of the cutting groove can be adjusted according to the accuracy of the cutting equipment and the size of the die 120 .

[0104] Optionally, specific values ​​of the width L of the opening of the cutting groove include but are not limited to: 8um, 9um, 10um, 11um, 12um, 13um or 14um.

[0105] Optionally, the wafer body 100 includes a plurality of shots, and each shot includes a plurality of functional dies 130 .

[0106] Optionally, a single shot is provided with one or more test dies 140 .

[0107] In this embodiment, combined with Figure 3 As shown, the wafer body 100 includes a plurality of exposure areas 102 (shot), combined with Figure 3 and Figure 4 As shown, each shot includes a plurality of functional dies 130 and a test die 140. The number of the test die 140 is one or more test die 140. The test die 140 is used to implement wafer process testing within a single shot.

[0108] Optionally, when a single shot includes multiple test grains 140, the multiple test grains 140 are distributed at the vertex corners of the single shot. For example, when a single shot includes two test grains 140, the two test grains 140 are distributed at two vertex corners of the diagonal line of the single shot. When a single shot includes four test grains 140, a test grain 140 is set at each vertex corner of the single shot.

[0109] Optionally, multiple shots share one or more test dies 140 for process testing.

[0110] In this embodiment, combined with Figure 1 As shown, the wafer body 100 includes multiple exposure areas 102 (shots), and each shot includes multiple functional grains 130. Multiple shots share one or more test grains 140 for process testing. In this way, the position and number of the test grains 140 can be set according to the test requirements to improve the wafer utilization. In the wafer structure 1, multiple shots share one or more test chips for process testing, which can reduce the occupied area of ​​the test chips and improve the wafer utilization.

[0111] Combination Fig.12As shown, when multiple shots share one or more test dies 140 , the test dies 140 are disposed at the vertices where the multiple shots are connected.

[0112] In some embodiments, a chip is provided, wherein the grains 120 are obtained by cutting along the cutting grooves of the wafer structure 1 described in any of the above embodiments by laser stealth cutting, and the single grains 120 are independently packaged to obtain a chip.

[0113] In this embodiment, a laser hidden cutting method is used to cut along the cutting groove of the wafer structure 1 to obtain multiple grains, and then a single grain is independently packaged to obtain a chip. Since a too small cutting groove cannot achieve a safe cutting method, by cutting using a laser hidden cutting method, it is possible to achieve packaging process cutting in the case of a narrow cutting groove. In this way, by reducing the width of the cutting groove, the utilization rate of the wafer structure is improved. In addition, the effect of packaging process cutting can be improved.

[0114] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A wafer structure, characterized in that: include: A wafer body, the wafer body comprising a dicing path and a plurality of dies, wherein the dicing path is located between two adjacent dies; The multiple dies include functional dies and test dies, and the test dies are used for process testing of wafer structures; The test crystal grain comprises: a test crystal grain body and a plurality of wafer test pins, wherein the plurality of wafer test pins are distributed on both sides of the test crystal grain body and are used for connecting with the circuit layer of the wafer body.

2. The wafer structure according to claim 1, characterized in that: The test die also includes: A plurality of functional test pins are arranged on the test die body and are used to connect with the functional die; Among them, the wafer test pins are distributed on both sides of the functional test pins.

3. The wafer structure according to claim 2, characterized in that: Functional chips include: Functional grain body; A die pin is provided on the functional die body, and the die pin is used to connect with an external circuit; Among them, the wafer pins and the die test pins have the same size.

4. The wafer structure according to any one of claims 1 to 3, characterized in that: The sum of the areas of the test dies is less than or equal to 10% of the area of ​​the wafer body; and / or The size of a single test die is the same as the size of a single functional die; and / or The width of the cutting path ranges from 15um to 30um.

5. The wafer structure according to any one of claims 1 to 3, characterized in that: Also includes: The reinforcement path is arranged on the peripheral side wall of the crystal grain and is located inside the cutting path.

6. The wafer structure according to claim 5, characterized in that: Also includes: The protection ring is arranged on the peripheral side of the crystal grain, and the protection ring is located between the reinforcement channel and the side wall of the crystal grain.

7. The wafer structure according to claim 5, characterized in that: The isolation layer is arranged on the peripheral side wall of the crystal grain, and the reinforcement path is located between the isolation layer and the cutting path.

8. The wafer structure according to claim 7, characterized in that: The width of the reinforcement path is in the range of: D×20%≤d≤D×50%, where d is the width of the reinforcement path and D is the width of the cutting path; and / or Along the depth direction of the cutting path, the height of the isolation layer is greater than or equal to the height of the grain; and / or The thickness of the isolation layer ranges from 1um to 2um.

9. The wafer structure according to any one of claims 1 to 3, characterized in that: The wafer body includes multiple shots, each shot includes multiple functional grains; Wherein, a single shot is provided with one or more test grains; or Multiple shots share one or more test dies for process testing.

10. A chip, characterized in that: A laser hidden cutting method is adopted to cut along the cutting groove of the wafer structure according to any one of claims 1 to 9 to obtain grains, and the obtained single grains are packaged to obtain chips.

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