Semiconductor structure and manufacturing method thereof, semiconductor device and storage system

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a semiconductor device and a storage system. The method for manufacturing the semiconductor structure comprises the steps that first dielectric layers and second dielectric layers are stacked alternately, a laminated structure is formed, and the laminated structure comprises a plurality of storage areas and non-storage areas located between the adjacent storage areas; forming a first conductive column penetrating through the storage area and a supporting structure penetrating through the non-storage area and close to the storage area; removing the second dielectric layer of the storage region to form a gap; and forming a dielectric layer covering the first conductive column and a second conductive column covering the dielectric layer in the gap.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for manufacturing the semiconductor structure, a semiconductor device, and a storage system. Background Art

[0002] In the field of integrated circuit design and manufacturing, as the semiconductor manufacturing process level continues to improve, the process feature size is getting smaller and smaller, and the integration of integrated circuits is getting higher and higher. At the same time, as the process feature size of the semiconductor structure in the integrated circuit is shrinking, the difficulty of the formation process of the semiconductor structure is increasing.

[0003] For example, in the field of semiconductor structures such as three-dimensional semiconductor memory devices, capacitors used as charge storage elements play an important role in the performance of semiconductor structures. However, in the process of forming capacitors, other parts of the semiconductor structure are often affected to a certain extent. Summary of the invention

[0004] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0005] The present application provides a method for manufacturing a semiconductor structure. The method includes: alternately stacking a first dielectric layer and a second dielectric layer to form a stacked structure, wherein the stacked structure includes a plurality of storage areas and a non-storage area located between adjacent storage areas; forming a first conductive column penetrating the storage area and a supporting structure penetrating the non-storage area and close to the storage area; removing the second dielectric layer of the storage area to form a gap; and forming a dielectric layer covering the first conductive column and a second conductive column covering the dielectric layer in the gap.

[0006] In one embodiment, a first conductive pillar penetrating a storage area and a supporting structure penetrating a non-storage area and a portion close to the storage area are formed, comprising: forming a first mask layer having a first conductive pillar pattern on a surface of a stacked structure, wherein the first mask layer comprises a first sub-mask layer located in an edge region of the stacked structure and a second sub-mask layer located in the storage area and the non-storage area; forming a first protective layer covering the first sub-mask layer; forming a second mask layer on the first protective layer and the second sub-mask layer, covering the sidewalls of the first protective layer and exposing the first conductive pillar pattern in the second sub-mask layer; etching the stacked structure using the second sub-mask layer and the second mask layer as masks to form a first conductive hole penetrating the storage area and a supporting hole penetrating the non-storage area and a portion close to the storage area; and filling the first conductive hole and the supporting hole with conductive material to form a first conductive pillar and a supporting structure, respectively.

[0007] In one embodiment, the second dielectric layer of the storage area is removed to form a gap, including: forming a second protective layer covering the edge area of ​​the stacked structure; forming a patterned third mask layer on the surface of the second protective layer, the storage area and the non-storage area; and removing the second dielectric layer of the storage area using the patterned third mask layer as a mask to form a gap.

[0008] In one embodiment, the method further includes: forming a transistor connected to the first conductive pillar on one side of the stacked structure.

[0009] On the other hand, the present application provides a semiconductor device, which includes: a plurality of die regions and cutting paths between adjacent die regions; a storage structure located in the die region, including: a first conductive column, a dielectric layer covering the first conductive column, and a second conductive column covering the dielectric layer; and a support structure located in the cutting paths.

[0010] In one embodiment, the width of the scribe line is greater than or equal to 1.6 μm.

[0011] On the other hand, the present application provides a semiconductor structure, which includes: a stacked structure; a storage structure that runs through the stacked structure and includes a first conductive column, a dielectric layer covering the first conductive column, and a second conductive column covering the dielectric layer; and a support structure that runs through the stacked structure and is located at an edge region of the stacked structure.

[0012] In one embodiment, the width of the support structure in a first direction is less than or equal to 1.6 μm, wherein the first direction is perpendicular to the stacking direction of the stacked structure.

[0013] In one embodiment, the semiconductor structure further includes: a transistor located at one side of the stacked structure and connected to the first conductive pillar.

[0014] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0015] In one or more embodiments of the present application, in the process of forming the first conductive pillar (which can be used as an electrode plate of a capacitor formed subsequently) in the storage area, a support structure can also be formed in the portion of the non-storage area close to the storage area. This is conducive to reducing the risk of bending of the portion of the storage area close to the non-storage area in the subsequent process, thereby facilitating improving the molding yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0017] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0018] Figure 2 is a process step diagram for forming a stacked structure according to an exemplary embodiment of the present application;

[0019] Figure 3A and Figure 3B is a schematic structural diagram of forming a mask dielectric layer and etching a mask layer according to an exemplary embodiment of the present application;

[0020] Figure 4A and Figure 4B is a schematic structural diagram of forming a first conductive column and a support structure according to an exemplary embodiment of the present application;

[0021] Figure 5A and Figure 5B is a schematic structural diagram of forming a second protective layer and a third mask layer according to an exemplary embodiment of the present application;

[0022] Fig. 6A and Figure 6B is a schematic diagram of a structure for forming a gap according to an exemplary embodiment of the present application;

[0023] Figure 7 is a process step diagram for forming a dielectric layer, a second conductive column and a conductive structure according to an exemplary embodiment of the present application;

[0024] Figure 8 is a process step diagram for forming a semiconductor structure according to an exemplary embodiment of the present application;

[0025] Fig. 9A and Fig. 9B is a schematic structural diagram of a semiconductor device provided according to an exemplary embodiment of the present application;

[0026] Fig.10 is a schematic structural diagram of a semiconductor structure provided according to an exemplary embodiment of the present application;

[0027] Fig.11 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0028] Fig. 12A and Fig. 12B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0030] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first dielectric layer discussed in this application may also be referred to as the second dielectric layer, the first conductive column may also be referred to as the second conductive column, and vice versa.

[0031] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0032] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0033] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0034] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0036] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0037] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0038] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0040] like Figure 1As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, alternately stacking a first dielectric layer and a second dielectric layer to form a stacked structure, wherein the stacked structure includes a plurality of storage areas and a non-storage area located between adjacent storage areas; S1200, forming a first conductive pillar penetrating the storage area and a supporting structure penetrating the non-storage area and a portion close to the storage area; S1300, removing the second dielectric layer of the storage area to form a gap; and S1400, forming a dielectric layer covering the first conductive pillar and a second conductive pillar covering the dielectric layer in the gap. Steps S1100 to S1400 will be described in detail below.

[0041] In the exemplary embodiment of the present application, Figure 2 As shown, the first dielectric layer 1110 and the second dielectric layer 1120 may be alternately stacked to form a stacked structure 1100 , wherein the stacked structure 1100 may include a plurality of storage areas A and non-storage areas B located between adjacent storage areas A.

[0042] For example, the stacked structure 1100 may be formed by sequentially stacking the first dielectric layer 1110 and the second dielectric layer 1120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0043] It should be understood that the number and thickness of the first dielectric layer 1110 and the second dielectric layer 1120 are not limited to Figure 2 The number and thickness shown in , without departing from the concept of the present application, those skilled in the art can set any number and thickness of the first dielectric layer 1110 and the second dielectric layer 1120 as needed. In addition, the materials of the first dielectric layer 1110 and the second dielectric layer 1120 can be selected from suitable materials known in the art, for example, the material of the first dielectric layer 1110 may include nitride such as silicon nitride, and the material of the second dielectric layer 1120 may include oxide such as silicon oxide.

[0044] Exemplarily, the stacked structure 1100 may be formed on a substrate 1200. The material of the substrate 1200 includes at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 1200 may be a single-layer structure such as a silicon substrate, a germanium substrate, or a silicon germanium substrate, or a multi-layer structure such as a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. Exemplarily, a plurality of layers prepared from different materials may be sequentially arranged by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the substrate 1200.

[0045] Figure 4A and Figure 4B 1 is a schematic diagram of a structure for forming a first conductive column 1310 and a support structure 1400 according to an exemplary embodiment of the present application, wherein: Figure 4A FIG. 1 is a partial top view of the semiconductor structure after forming the first conductive pillar 1310 and the support structure 1400. Figure 4B for Figure 4A Cross-sectional view along DD direction.

[0046] In the exemplary embodiment of the present application, Figure 4A or Figure 4B As shown, a first conductive pillar 1310 penetrating the storage region A and a support structure 1400 penetrating a portion of the non-storage region B close to the storage region A may be formed.

[0047] Figure 3A and Figure 3B is a schematic diagram of a structure for forming a mask dielectric layer 1500 and etching a mask layer 1600 according to an exemplary embodiment of the present application, wherein: Figure 3A FIG. 1 is a partial top view of a semiconductor structure after forming a mask dielectric layer 1500 and etching the mask layer 1600. Figure 3B for Figure 3A Cross-sectional view along DD direction.

[0048] For example, forming the first conductive pillar 1310 and the support structure 1400 may include: Figure 3A and Figure 3B As shown, a mask dielectric layer 1500 and a patterned etching mask layer 1600 are sequentially formed on the surface of the stacked structure 1100. The mask dielectric layer 1500 may be a multilayer structure, such as an anti-reflection layer and an amorphous carbon layer. Specifically, a patterned etching mask layer 1600 may be formed on the mask dielectric layer 1500, and the mask dielectric layer 1500 may be etched using the patterned etching mask layer 1600 as a mask to transfer the pattern in the etching mask layer 1600 to the mask dielectric layer 1500, and then the patterned mask dielectric layer 1500 may be used as an etching mask to etch the stacked structure 1100 to form the first conductive pillar 1310 and the support structure 1400. The present application uses the patterned mask dielectric layer 1500 as an etching mask to improve the etching selectivity when etching the stacked structure 1100, thereby reducing the situation where the photoresist is not enough when etching the stacked structure 1100.

[0049] For example, Figure 3BAs shown, the patterned etching mask layer 1600 may include a first mask layer 1610, a first protective layer 1620, and a second mask layer 1630. For example, a first mask layer 1610 having a first conductive pillar pattern may be formed on the mask dielectric layer 1500. The first mask layer 1610 may include a first sub-mask layer 1611 located in an edge region C of the stacked structure 1100 and a second sub-mask layer 1612 located in the storage region A and the non-storage region B. The first mask layer 1610 may be used to determine a specific position for subsequently forming the first conductive pillar 1310.

[0050] Exemplarily, a first protective layer 1620 covering the first sub-mask layer 1611 may be formed. In actual processes, the morphology of the edge region C of the stacked structure 1100 is relatively poor, such as defects such as bending and depression. Therefore, in order to improve the overall performance of the semiconductor structure, a more complex structure such as a capacitor may not be formed in the edge region C to protect the morphology of the edge region C. In the present application, in order to protect the edge region C, a first protective layer 1620 covering the first sub-mask layer 1611 may be formed on the first sub-mask layer 1611 located in the edge region C. Exemplarily, the first protective layer 1620 may be a photoresist layer. Specifically, a photoresist layer may be spin-coated on the first sub-mask layer 1611 so that the photoresist layer covers the first sub-mask layer 1611 having a pattern.

[0051] For example, a second mask layer 1630 covering the sidewall of the first protective layer 1620 and exposing the first conductive pillar pattern in the second sub-mask layer 1612 may be formed on the first protective layer 1620 and the second sub-mask layer 1612. In the present application, by providing the second mask layer 1630 to cover the sidewall of the first protective layer 1620, the shape stability of the first protective layer 1620 is enhanced, and the risk of the first protective layer 1620 covering other parts due to factors such as temperature and time is reduced.

[0052] For example, the mask dielectric layer 1500 and the stacked structure 1100 may be sequentially etched with the second sub-mask layer 1612 and the second mask layer 1630 as masks to form a first conductive hole 100 penetrating the storage area A and a supporting hole 200 penetrating the non-storage area B and close to the storage area A ( Figure 4B ); and filling the first conductive hole 100 and the support hole 200 with a conductive material to form a first conductive column 1310 and a support structure 1400, respectively.

[0053] The first conductive pillar 1310 and the support structure 1400 may be made of any suitable conductive material, for example, a metal or metal alloy such as tungsten, cobalt, nickel, copper or aluminum, and / or a combination thereof. In some embodiments, the first conductive pillar 1310 and the support structure 1400 may also include a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc. The first conductive pillar 1310 and the support structure 1400 may be formed by any suitable deposition process, for example, sputtering, thermal evaporation, electron beam evaporation, ALD, PVD, and / or a combination thereof. Exemplarily, after forming the first conductive pillar 1310 and the support structure 1400, a planarization process such as a mechanical grinding process may be used to remove excess conductive material outside the first conductive hole 100 and the support hole 200.

[0054] For example, the first conductive pillar 1310 and the support structure 1400 may have a cylindrical or columnar shape extending along the stacking direction in the stacked structure 1100. The first conductive pillar 1310 may serve as a first electrode plate of a capacitor formed subsequently. It should be understood that the support structure 1400 may have a structure that is the same as or similar to the first conductive pillar 1310, and may play a supporting role to prevent the portion of the storage area A close to the non-storage area B from structural bending, thereby improving the structural stability of the semiconductor structure.

[0055] For example, after forming the first conductive pillars 1310 and the support structure 1400 , the mask dielectric layer 1500 and the etching mask layer 1600 may be removed by, for example, a dry etching process or a combination of dry and wet etching processes.

[0056] Fig. 6A and Figure 6B is a schematic diagram of a structure for forming a gap 300 according to an exemplary embodiment of the present application, wherein: Fig. 6A FIG. 3 is a partial top view of the semiconductor structure after the gap 300 is formed. Figure 6B for Fig. 6A Cross-sectional view along DD direction.

[0057] In the exemplary embodiment of the present application, Figure 6B As shown, the second dielectric layer 1120 of the storage area A can be removed to form a gap 300. Subsequently, a dielectric layer 1320 and a second conductive pillar 1330 ( Figure 7 ). The first conductive pillar 1310, the dielectric layer 1320 and the second conductive pillar 1330 may constitute a capacitor, wherein the first conductive pillar 1310 and the second conductive pillar 1330 may be two electrode plates of the capacitor respectively.

[0058] It should be understood that Figure 6BAs shown, in the actual process, in the process of removing the second dielectric layer 1120 of the storage area A, the second dielectric layer 1120 of the non-storage area B close to the storage area A will inevitably be removed. The present application provides a support structure 1400 in the non-storage area B close to the storage area A, so that the support structure 1400 can play a supporting role, prevent the part of the storage area A close to the non-storage area B from structural bending, and thus help to improve the structural stability of the finally formed semiconductor structure.

[0059] Figure 5A and Figure 5B 1 is a schematic diagram of a structure for forming a second protective layer 1640 and a third mask layer 1650 according to an exemplary embodiment of the present application, wherein: Figure 5A A partial top view of the semiconductor structure after forming the second protection layer 1640 and the third mask layer 1650. Figure 5B for Figure 5A Cross-sectional view along DD direction.

[0060] Exemplarily, forming the gap 300 may include: Figure 5A and Figure 5B As shown, a second protective layer 1640 covering the edge region C of the stacked structure 1100 may be formed; a patterned third mask layer 1650 may be formed on the surfaces of the second protective layer 1640, the storage region A, and the non-storage region B; and the second dielectric layer 1120 of the storage region A is removed using the patterned third mask layer 1650 as a mask to form a gap 300. For example, the gap 300 ( Figure 6B ).

[0061] For example, after the gap 300 is formed, the second protection layer 1640 and the third mask layer 1650 may be removed by, for example, a dry etching process or a combination of dry and wet etching processes.

[0062] In the exemplary embodiment of the present application, Figure 7 As shown, a dielectric layer 1320 covering the first conductive pillar 1310 and a second conductive pillar 1330 covering the dielectric layer 1320 may be formed in the gap 300. The first conductive pillar 1310, the dielectric layer 1320, and the second conductive pillar 1330 may constitute a capacitor for storing charges.

[0063] It should be understood that the structure and construction of the capacitor is not limited to Figure 7 The examples may also include any suitable structure and construction, such as cylindrical capacitors, trench capacitors, stacked capacitors, cup capacitors, and any other capacitors that conform to actual processes, and this application does not make any specific limitations on this.

[0064] For example, Figure 7As shown, during the process of forming the dielectric layer 1320 in the gap 300 , the dielectric layer 1320 may also be formed on the surface of the stacked structure 1100 . The dielectric layer 1320 on the surface of the stacked structure 1100 may serve as an isolation layer between the subsequently formed conductive structure 1700 and the first conductive pillar 1310 .

[0065] The dielectric layer 1320 may cover the sidewalls of the first conductive pillars 1310 exposed through the gap 300 and the surface of the substrate 1200. The dielectric layer 1320 may be any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride and / or a high-k dielectric film (such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide or lanthanum oxide film, and / or a combination thereof). The dielectric layer 1320 may be formed by any suitable method, such as a thin film deposition process of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0066] The second conductive pillar 1330 may cover the sidewalls of the dielectric layer 1320 within the gap 300. The second conductive pillar 1330 may be made of any suitable conductive material, for example, a metal or metal alloy such as tungsten, cobalt, nickel, copper or aluminum, and / or a combination thereof. In some embodiments, the second conductive pillar 1330 may also include a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc. The second conductive pillar 1330 may be formed by any suitable deposition process, for example, sputtering, thermal evaporation, electron beam evaporation, ALD, PVD, and / or a combination thereof. Exemplarily, after forming the second conductive pillar 1330, a planarization process such as a mechanical grinding process may be used to remove excess conductive material outside the gap 300.

[0067] In the exemplary embodiment of the present application, Figure 7 As shown, a conductive structure 1700 connected to a plurality of second conductive pillars 1330 may be formed. The second conductive pillars 1330 may be connected to other control circuits via the conductive structure 1700.

[0068] The conductive structure 1700 may be made of any suitable conductive material such as a metal or a metal alloy, for example, tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicide (WSi x 、CoSi x 、NiSi x 、AlSi x The conductive material may be deposited by one or more thin film deposition processes, such as CVD, PECVD, PVD, ALD, electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

[0069] In an exemplary embodiment of the present application, a transistor (not shown) connected to the first conductive pillar 1310 may be formed on one side of the stacked structure 1100. For example, a plurality of transistors may be formed in the substrate 1200 located on one side of the stacked structure 1100. The transistor and the capacitor may form a memory cell, wherein the transistor may be used as a switch or selection device in the memory cell. One end of the transistor may be connected to the capacitor, and the other end may be connected to the bit line. Each memory cell may include a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (also referred to as a transfer transistor) for controlling (e.g., switching and selecting) access to the memory cell.

[0070] In the exemplary embodiment of the present application, the stacked structure 1100 may be cut in the non-storage area B along the stacking direction to form a plurality of semiconductor structures ( Figure 8 ), wherein each semiconductor structure may include at least one storage area A. The present application provides a support structure 1400 in a portion of the non-storage area B close to the storage area A, so that the support structure 1400 can play a supporting role to reduce defects such as bending of the portion of the storage area A close to the non-storage area B.

[0071] Fig. 9A and Fig. 9B is a schematic structural diagram of a semiconductor device provided according to an exemplary embodiment of the present application, wherein: Fig. 9A A partial top view of a semiconductor device. Fig. 9B for Fig. 9A Cross-sectional view along DD direction.

[0072] The semiconductor device may include a plurality of die regions A1, scribe lines B1 (including first scribe lines B11 and second scribe lines B12), a storage structure and a support structure 1400. For example, the semiconductor device may be cut in the scribe lines B1 to form a plurality of die regions A1, a plurality of scribe lines B12, a plurality of storage structures and a support structure 1400. Figure 8 The semiconductor structure shown.

[0073] like Fig. 9A and Fig. 9B As shown, the semiconductor device may include a stacked structure 1100 having a plurality of die areas A1 and scribe lines B1. The semiconductor device may extend along a first direction X and a second direction Y, wherein the first direction X may be perpendicular to the second direction Y. The semiconductor device may be in any shape that meets the actual process, such as a circle or a rectangle.

[0074] like Fig. 9AAs shown, a plurality of die regions A1 may be distributed in an array in the first direction X and the second direction Y. A cutting lane B1 may be located between adjacent die regions A1. The die regions A1 may be used to form a semiconductor structure later, and the cutting lane B1 may be used as a cutting line for dividing the die regions A1 in the packaging stage when the semiconductor structure is manufactured. Therefore, the cutting lane B1 is not used for device storage.

[0075] The cutting lanes B1 may include a first cutting lane B11 extending along a first direction X and a second cutting lane B12 extending along a second direction Y. The first cutting lanes B11 and the second cutting lanes B12 intersect and are perpendicular to each other. The first cutting lanes B11 and the second cutting lanes B12 are crisscrossed and distributed to divide a plurality of array-arranged die areas A1.

[0076] The storage structure may be located in the die area A1. The storage structure may be, for example, a capacitor, and may include a first conductive pillar 1310, a dielectric layer 1320, and a second conductive pillar 1330, wherein the dielectric layer 1320 may cover at least a portion of the first conductive pillar 1310, and the second conductive pillar 1330 may cover at least a portion of the dielectric layer 1310. In other words, the first conductive pillar 1310, the dielectric layer 1320, and the second conductive pillar 1330 may constitute a capacitor, wherein the dielectric layer 1320 may be located between the first conductive pillar 1310 and the second conductive pillar 1330, and the first conductive pillar 1310 and the second conductive pillar 1330 may be two electrode plates of the capacitor, respectively.

[0077] It should be understood that the structure and construction of the capacitor is not limited to Fig. 9B The examples may also include any suitable structure and construction, such as cylindrical capacitors, trench capacitors, stacked capacitors, cup capacitors, and any other capacitors that conform to actual processes, and this application does not make any specific limitations on this.

[0078] The support structure 1400 may be located on the cutting path B1. For example, the support structure 1400 may be located on the portion of the cutting path B1 close to the die area A1. By providing the support structure 1400 on the portion of the cutting path B1 close to the die area A1, the present application can enable the support structure 1400 to play a supporting role, thereby preventing the portion of the die area A1 close to the cutting path B1 from experiencing structural bending and the like in the actual process, thereby facilitating improving the structural stability of the semiconductor structure finally formed. For example, the width of the cutting path B1 may be greater than or equal to 1.6 μm, that is, the width H1 of the first cutting path B11 and the width H2 of the second cutting path B12 may both be greater than or equal to 1.6 μm, so as to form the support structure 1400 in the cutting path.

[0079] Fig.10 is a schematic structural diagram of a semiconductor structure provided according to an exemplary embodiment of the present application.

[0080] The semiconductor structure may include a stacked structure 1100 , a storage structure, and a support structure 1400 .

[0081] The storage structure may penetrate the stacked structure 1100. The storage structure may be, for example, a capacitor, and may include a first conductive pillar 1310, a dielectric layer 1320, and a second conductive pillar 1330, wherein the dielectric layer 1320 may cover at least a portion of the first conductive pillar 1310, and the second conductive pillar 1330 may cover at least a portion of the dielectric layer 1310. In other words, the first conductive pillar 1310, the dielectric layer 1320, and the second conductive pillar 1330 may constitute a capacitor, wherein the dielectric layer 1320 may be located between the first conductive pillar 1310 and the second conductive pillar 1330, and the first conductive pillar 1310 and the second conductive pillar 1330 may be two electrode plates of the capacitor, respectively.

[0082] It should be understood that the structure and construction of the capacitor is not limited to Fig.10 The examples may also include any suitable structure and construction, such as cylindrical capacitors, trench capacitors, stacked capacitors, cup capacitors, and any other capacitors that conform to actual processes, and this application does not make any specific limitations on this.

[0083] The dielectric layer 1320 may be any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride and / or a high-k dielectric film (such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide or lanthanum oxide film, and / or a combination thereof). The first conductive pillar 1310 and the second conductive pillar 1330 may also include a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc.

[0084] The support structure 1400 may penetrate the stacked structure 1100 and may be located at an edge region of the stacked structure 1100. The width of the support structure 1400 in the first direction X may be less than or equal to 1.6 μm, wherein the first direction X may be perpendicular to the stacking direction Z of the stacked structure 1100. The support structure 1400 may have the same material as the first conductive pillar 1310. The present application provides the support structure 1400 at the edge region of the stacked structure 1100, so that the support structure 1400 can play a supporting role, so as to reduce defects such as bending in the edge region of the stacked structure 1100.

[0085] The semiconductor structure may further include a conductive structure 1700 connected to the plurality of second conductive pillars 1330. The second conductive pillars 1330 may be connected to other control circuits via the conductive structure 1700. The conductive structure 1700 may be made of any suitable conductive material such as a metal or a metal alloy, for example, tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicide (WSi x 、CoSi x 、NiSix 、AlSi x etc.), or any combination thereof.

[0086] The semiconductor structure may further include a substrate 1200 located on one side of the stacked structure 1100 and a plurality of transistors (not shown) located in the substrate 1200. The transistor and the capacitor may form a memory cell, wherein the transistor may be used as a switch or selection device in the memory cell. One end of the transistor may be connected to the capacitor and the other end may be connected to the bit line. Each memory cell may include a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (also referred to as a transfer transistor) for controlling (e.g., switching and selecting) access to the memory cell.

[0087] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0088] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0089] Fig.11 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0090] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.11 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0091] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0092] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig. 12AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig.11 The host 18 in the memory card connector 24 is coupled. Fig. 12B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig.11 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0093] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Alternately stacking a first dielectric layer and a second dielectric layer to form a stacked structure, wherein the stacked structure includes a plurality of storage areas and a non-storage area located between adjacent storage areas; forming a first conductive column penetrating the storage area and a supporting structure penetrating the non-storage area and close to the storage area; removing the second dielectric layer of the storage area to form a gap; as well as A dielectric layer covering the first conductive pillar and a second conductive pillar covering the dielectric layer are formed in the gap.

2. The method according to claim 1, characterized in that Forming a first conductive pillar penetrating the storage area and a supporting structure penetrating the non-storage area and close to the storage area, comprising: Forming a first mask layer having a first conductive pillar pattern on the stacked structure, wherein the first mask layer comprises a first sub-mask layer located in an edge region of the stacked structure and a second sub-mask layer located in the storage region and the non-storage region; forming a first protective layer covering the first sub-mask layer; forming a second mask layer on the first protection layer and the second sub-mask layer, covering the sidewall of the first protection layer and exposing the first conductive pillar pattern in the second sub-mask layer; Using the second sub-mask layer and the second mask layer as masks, etching the stacked structure to form a first conductive hole penetrating the storage area and a supporting hole penetrating the non-storage area and close to the storage area; and Conductive material is filled in the first conductive hole and the support hole to form a first conductive column and a support structure respectively.

3. The method according to claim 1, characterized in that Removing the second dielectric layer of the storage area to form a gap comprises: forming a second protective layer covering the edge area of ​​the stacked structure; forming a patterned third mask layer on surfaces of the second protective layer, the storage area, and the non-storage area; and The second dielectric layer of the storage area is removed by using the patterned third mask layer as a mask to form a gap.

4. The method according to claim 1, characterized in that The method further comprises: A transistor connected to the first conductive pillar is formed on one side of the stacked structure.

5. A semiconductor device, characterized in that: include: a plurality of die regions and scribe lines between adjacent die regions; A storage structure, located in the die area, comprising: a first conductive column, a dielectric layer covering the first conductive column, and a second conductive column covering the dielectric layer; as well as A supporting structure is located on the cutting path.

6. The semiconductor device according to claim 5, characterized in that The width of the cutting line is greater than or equal to 1.6 μm.

7. A semiconductor structure, characterized in that: include: Laminated structure; A storage structure, which runs through the stacked structure, includes a first conductive column, a dielectric layer covering the first conductive column, and a second conductive column covering the dielectric layer; as well as The supporting structure penetrates through the stacked structure and is located at an edge region of the stacked structure.

8. The semiconductor structure according to claim 7, characterized in that: The width of the support structure in a first direction is less than or equal to 1.6 μm, wherein the first direction is perpendicular to the stacking direction of the stacked structure.

9. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further comprises: The transistor is located at one side of the stacked structure and connected to the first conductive column.

10. A storage system, characterized in that: include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 7 to 9; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

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