Process method for forming high-temperature-resistant 4H-SiC P-type ohmic contact
By using SiC wafer ion implantation, high-temperature activation annealing and Si3N4 side wall formation in 4H-SiC P-type ohmic contact, combined with Pd/Al/Pd metal stacking and rapid thermal annealing, the 4H- in the prior art was solved. The problem of poor reliability of SiC P-type ohmic contact high temperature has achieved efficient improvement in ohmic contact quality.
Patent Information
- Application Number
- CN202411545149.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-18
AI Technical Summary
It is difficult for the prior art to form 4H-SiC P-type ohmic contacts with low specific contact resistance, especially under high temperature conditions, the high-temperature reliability of the ohmic contact of the Ti/Al metal system is poor.
SiC wafers are used for N and Al ion implantation. After high-temperature activation and annealing, SiO2/Si3N4/SiO2 is deposited successively as interlayer medium. Si3N4 side walls are formed by chemical vapor deposition and dry etching, and finally deposition by magnetron sputtering. Pd/Al/Pd metal stacks and undergoes rapid thermal annealing to form ohmic contacts.
Through the formation of Si3N4 side walls, the Al metal is prevented from penetrating transversely, and the high temperature reliability of ohmic contact is improved; the high metal work function and good high temperature reliability of Pd metal are combined with the reaction of Al and SiC to generate an intermediate phase product, reducing the barrier height , promote the emergence of ohmic characteristics and improve the quality of ohmic contact.
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Figure CN119486174A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of wide bandgap semiconductor manufacturing process, and more specifically, to a process method for forming a high temperature resistant 4H-SiC P-type ohmic contact. Background Art
[0002] As a representative material of the third-generation semiconductors, SiC power devices can operate at higher voltages and higher frequencies than traditional Si-based power devices due to its wide bandgap and high critical breakdown field strength. At the same time, due to the high thermal conductivity of SiC, SiC chips have a higher operating temperature.
[0003] However, since P-type 4H-SiC has a very high work function, the metal work function required to form a P-type ohmic contact with low specific contact resistance should be higher than 7eV, while the work function of the commonly used metals is usually between 4eV and 5eV, so most metals cannot form a P-type ohmic contact with low specific contact resistance. Currently, the Ti / Al metal system has a wide influence, but due to the inherent characteristics of Al metal, the high-temperature reliability of the ohmic contact formed by it is poor. Summary of the invention
[0004] The purpose of the present invention is to address the deficiencies of the prior art and to propose a process for forming a high temperature resistant 4H-SiC P-type ohmic contact.
[0005] In a first aspect, a process for forming a high temperature resistant 4H-SiC P-type ohmic contact is provided, comprising:
[0006] Step 1, providing a SiC wafer, wherein the SiC wafer comprises a SiC N+ substrate and a SiC N- epitaxial layer from bottom to top;
[0007] Step 2: implanting N ions into the SiC N-epitaxial to form a body region N+; implanting Al ions into the SiC N-epitaxial to form a source region and a drain region P+;
[0008] Step 3: After the carbon film is covered, the implanted ions are subjected to high temperature activation annealing;
[0009] Step 4: deposit gate oxide and polysilicon in the gate region, and deposit SiO2 / Si3N4 / SiO2 in other regions in sequence as interlayer dielectrics;
[0010] Step 5, performing photolithography to open holes in the ohmic contact area, where the openings are located on the source region, the drain region P+ and the body region N+;
[0011] Step 6, depositing Si3N4 by chemical vapor deposition, and then removing Si3N4 by dry etching to form Si3N4 sidewalls in the ohmic contact hole;
[0012] Step 7: Deposit a Pd / Al / Pd metal stack as a metal for forming an ohmic contact by a magnetron sputtering process, and form the ohmic contact by rapid thermal annealing.
[0013] Preferably, in step 4, the gate oxide is SiO2.
[0014] Preferably, in step 4, after the gate oxide deposition is completed, post-oxidation annealing is performed in a NO atmosphere.
[0015] Preferably, in step 6, CF4 is used as the etching gas.
[0016] Preferably, in step 7, the rapid thermal annealing is performed in an Ar atmosphere or an Ar+H2 mixed atmosphere.
[0017] In a second aspect, a high temperature resistant 4H-SiC P-type ohmic contact prepared by any method described in the first aspect is provided.
[0018] The beneficial effects of the present invention are:
[0019] 1. In the present invention, SiO2 / Si3N4 / SiO2 are sequentially deposited as interlayer dielectrics after ion activation annealing, and the middle layer of Si3N4 can prevent Al from reacting with and penetrating SiO2 in subsequent processing.
[0020] 2. The present invention uses chemical vapor deposition of Si3N4 and dry etching to form a layer of Si3N4 on the side wall of the ohmic contact opening, which can prevent the lateral penetration of metal Al at high temperatures, thereby improving the high-temperature reliability of the ohmic contact.
[0021] 3. The present invention uses palladium (Pd) metal, which is a chemically inactive noble metal with a metal work function of 4.9 eV. For forming ohmic contact, Pd metal has the following advantages: 1. The metal work function of Pd metal is higher, and it is easier to form a P-type ohmic contact; 2. Studies have shown that the intermediate phase product Pd2Si formed after high-temperature annealing of Pd and silicon carbide can reduce the barrier height and promote the emergence of ohmic characteristics; 3. Pd metal has good high-temperature reliability and oxidation resistance.
[0022] 4. The metal Al in the middle of the metal stack of the present invention can react with free C, remove free carbon, improve the ohmic contact quality, and enhance high temperature reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is a key process flow chart for improving the quality of silicon carbide P-type ohmic contact in the present invention;
[0024] Figure 2It is a cross-sectional schematic diagram of the present invention applied in SiC PMOS process;
[0025] Figure 3 It is a schematic cross-sectional diagram of the process flow of the present invention applied in SiC PMOS process. DETAILED DESCRIPTION
[0026] The present invention is further described below in conjunction with embodiments. The description of the following embodiments is only used to help understand the present invention. It should be noted that for ordinary persons in the art, without departing from the principle of the present invention, the present invention can also be modified in some ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
[0027] Embodiment 1:
[0028] To solve the problems of the prior art, Example 1 of the present application provides a process method for forming a high-temperature resistant 4H-SiC P-type ohmic contact, which includes ion implantation in the active area, high-temperature activation annealing, and sequential deposition of SiO2 / Si3N4 / SiO2 as an interlayer dielectric, wherein this layer of Si3N4 can prevent Al from reacting with and penetrating SiO2; photolithography is performed to open a hole in the ohmic contact area, and a layer of Si3N4 is chemically vapor deposited and then dry-etched away so that a layer of Si3N4 is attached to the sidewall of the ohmic contact opening, wherein this layer of Si3N4 can prevent Al metal from laterally penetrating at high temperatures; then a metal sputtering process is used to sputter a Pd / Al / Pd metal stack, and high-temperature annealing is performed, wherein the Pd metal at the bottom and the Al metal in the middle layer react with SiC to generate intermediate phase products Pd2Si, Pd3Si and Al4C3, wherein both Pd2Si and Al4C3 can reduce the barrier height, making the ohmic characteristics more likely to appear, and Al4C3 can also improve the carrier characteristics of the gold-semiconductor interface, thereby reducing the specific contact resistance.
[0029] Specifically, Figure 1 As shown, the process method for forming a high temperature resistant 4H-SiC P-type ohmic contact comprises:
[0030] Step 1: Provide a SiC wafer, wherein the SiC wafer comprises a SiC N+ substrate and a SiC N- epitaxial layer from bottom to top.
[0031] Step 2: Perform N ion implantation on the SiC N-epitaxial to form a body region N+; perform Al ion implantation on the SiC N-epitaxial to form a source region and a drain region P+.
[0032] Specifically, the P+ region is formed by multiple Al ion implantations at 500° C., with an implantation angle of 7°, and a junction depth of 0.2 μm-0.3 μm.
[0033] Step 3: After carbon film coverage, high temperature activation annealing is performed on the implanted ions.
[0034] Step 4: deposit gate oxide and polysilicon in the gate region, and deposit SiO2 / Si3N4 / SiO2 in other regions in sequence as interlayer dielectrics.
[0035] Step 5: Photolithography is performed to open holes in the ohmic contact area, and the opening positions are located above the source region, the drain region P+ and the body region N+.
[0036] Step 6: deposit Si3N4 by chemical vapor deposition, and then remove Si3N4 by dry etching to form Si3N4 sidewalls in the ohmic contact hole.
[0037] In step 6, CF4 is used as etching gas.
[0038] Step 7: Deposit a Pd / Al / Pd metal stack as a metal for forming an ohmic contact by a magnetron sputtering process, and form the ohmic contact by rapid thermal annealing.
[0039] Specifically, the metal of the ohmic contact is selected as a Pd / Al / Pd metal stack, and the Pd / Al / Pd metal stack is deposited by magnetron sputtering. After peeling, rapid thermal annealing is performed in a certain atmosphere, and the annealing temperature is 800°C-1050°C, and the annealing time is 60s. In the high-temperature annealing, an Ar atmosphere, an N2 atmosphere, or an Ar+H2 mixed atmosphere is used. For example, an Ar+1% H2 atmosphere can be used.
[0040] Embodiment 2:
[0041] On the basis of Example 1, Figure 2 As shown, Embodiment 2 of the present application provides a 4H-SiCP type ohmic contact for forming a high temperature resistant structure. In this embodiment, from bottom to top, it includes SiC N+ substrate, SiC N-epitaxial, source region, drain region P+ region, body region N+ region, gate oxide SiO2, polysilicon gate in-situ doped with P element, ohmic contact region, and metal interconnect layer.
[0042] To achieve Figure 2 The structure shown, see Figure 3 The manufacturing process technology of the present invention is further illustrated with a cross-sectional schematic diagram of the process flow.
[0043] In this embodiment, see Figure 3 (a), preferably, the SiC N+ substrate doping concentration used is 1.0×10 19 atom / cm 3 , thickness is 350μm.
[0044] In this embodiment, see Figure 3(a), preferably, the SiC N-epitaxial doping concentration used is 8.0×10 15 atom / cm 3 , thickness is 10μm.
[0045] In this embodiment, see Figure 3 (a) Preferably, the SiC N-epitaxial growth is subjected to RCA cleaning before the process to remove organic and inorganic contaminants on the epitaxial surface.
[0046] In this embodiment, see Figure 3 (b) N ion implantation is performed on the SiC N-epitaxial to form a body region N+ as the body region of the PMOS, which is located adjacent to the source region of the PMOS. Preferably, the body region N+ has a depth of 0.3 μm and an N ion concentration of 1.0×10 20 atom / cm 3 , uniform doping in the region.
[0047] Furthermore, the body region N+ is intended to be formed by multiple N ion implantations with different doses and energies. The implantation temperature is 500° C., the implantation angle is 7°, and the implantation dose and energy are shown in Table 1.
[0048] Table 1 N+ region ion implantation process
[0049] Injecting Elements Injection energy (keV) <![CDATA[Injection dose (atom / cm 2 )]]> N 10 <![CDATA[3×10 14 ]]> N 40 <![CDATA[5.8×10 14 ]]> N 100 <![CDATA[9.5×10 14 ]]> N 170 <![CDATA[1.1×10 15 ]]>
[0050] In this embodiment, see Figure 3 (c) Al ion implantation is performed on the SiC N-epitaxial to form source and drain P+ regions. Preferably, the source and drain P+ regions have a depth of 0.3 μm and an Al ion concentration of 1.0×10 20 atom / cm 3 , uniform doping in the region.
[0051] Furthermore, the body region P+ is planned to be formed by multiple Al ion implantations of different doses and energies. The implantation temperature is 500°C, the implantation angle is 7°, and the implantation dose and energy are shown in Table 2.
[0052] Table 2 P+ area ion implantation process
[0053] Injecting Elements Injection energy (keV) <![CDATA[Injection dose (atom / cm 2 )]]> Al 10 <![CDATA[1.6×10 14 ]]> Al 50 <![CDATA[5.8×10 14 ]]> Al 100 <![CDATA[9.6×10 14 ]]> Al 200 <![CDATA[1.5×10 15 ]]>
[0054] Furthermore, after the source region, drain region P+ and body region N+ implantation are completed, the implantation needs to be activated by annealing, the annealing temperature is 1700° C., and the annealing time is 30 minutes.
[0055] In this embodiment, see Figure 3(d) Etching the SiC N-epitaxial to remove the SiC thin layer on the epitaxial surface. Preferably, the SiC epitaxial is etched by H2 at 1600°C, the etching time is 20 minutes, and the etching thickness is 10 nm.
[0056] In this embodiment, see Figure 3 (e) After removing the SiC thin layer on the epitaxial surface, a gate oxide is grown on the SiC N-epitaxially. Preferably, the gate oxide is grown by a dry oxygen oxidation process, and the grown material is SiO2.
[0057] Furthermore, the gate oxide is generated by a dry oxygen oxidation process, where N2 and a small amount of O2 are first introduced. Preferably, the heating rate is 25°C / min, and a large amount of O2 is introduced. Under this reaction condition, 40nm thick SiO2 is formed.
[0058] Furthermore, after the gate oxide deposition is completed, post-oxidation annealing is required in a NO atmosphere, with an annealing temperature of 1250° C. and an annealing time of 60 min.
[0059] In this embodiment, see Figure 3 (f) On the surface of the gate oxide, polysilicon in-situ doped with P element is deposited by low pressure chemical vapor deposition process. Preferably, the low pressure chemical vapor deposition temperature is 600° C. and the thickness of the deposited polysilicon is 400 nm.
[0060] Furthermore, after the polysilicon is in-situ doped, the polysilicon is etched to form a polysilicon gate in-situ doped with the P element.
[0061] In this embodiment, see Figure 3 (g) SiO2 / Si3N4 / SiO2 are sequentially deposited as interlayer dielectrics, preferably, the deposition thickness is 100nm / 300nm / 100nm respectively. The ohmic contact holes are opened, and the opening positions are located above the source region, the drain region P+ and the body region N+. Preferably, after the holes are opened, 100nm Si3N4 is deposited by chemical vapor deposition, and then 100nm Si3N4 is removed by dry etching. After this operation, Si3N4 sidewalls will be formed in the ohmic contact holes.
[0062] In this embodiment, see Figure 3 (h) A 10nm / 50nm / 140nm Pd / Al / Pd metal stack is deposited as the metal to form the ohmic contact by magnetron sputtering process.
[0063] In this embodiment, see Figure 3 (i) The ohmic contact metal was rapidly annealed in an Ar atmosphere at a temperature of 900 °C for 60 s.
[0064] In the technical solution proposed by the present invention, SiO2 / Si3N4 / SiO2 are deposited in sequence as an interlayer dielectric after ion activation annealing, and the middle layer of Si3N4 can prevent Al from reacting with and penetrating SiO2 in subsequent processing; after Si3N4 is deposited by chemical vapor deposition and dry etching, a layer of Si3N4 is attached to the side wall of the ohmic contact opening, and this layer of Si3N4 can prevent metal Al from penetrating laterally at high temperatures, thereby improving the high-temperature reliability of the ohmic contact; secondly, the metal work function of Pd metal is relatively high, and it is easy to form a P-type ohmic contact. At the same time, the intermediate phase product Pd2Si formed after high-temperature annealing of Pd and silicon carbide can reduce the barrier height and promote the emergence of ohmic characteristics; at the same time, the metal Al in the middle of the metal stack can react with free C, remove free carbon, improve the quality of the ohmic contact, and also improve the high-temperature reliability.
[0065] It should be noted that the parts in this embodiment that are the same or similar to those in Embodiment 1 can be referenced to each other and will not be described in detail in this application.
Claims
1. A process for forming a high temperature resistant 4H-SiC P-type ohmic contact, characterized in that: include: Step 1, providing a SiC wafer, wherein the SiC wafer comprises a SiC N+ substrate and a SiC N- epitaxial layer from bottom to top; Step 2: implanting N ions into the SiC N-epitaxial to form a body region N+; implanting Al ions into the SiC N-epitaxial to form a source region and a drain region P+; Step 3: After the carbon film is covered, the implanted ions are subjected to high temperature activation annealing; Step 4: deposit gate oxide and polysilicon in the gate region, and deposit SiO2 / Si3N4 / SiO2 in other regions in sequence as interlayer dielectrics; Step 5, performing photolithography to open holes in the ohmic contact area, where the openings are located on the source region, the drain region P+ and the body region N+; Step 6, depositing Si3N4 by chemical vapor deposition, and then removing Si3N4 by dry etching to form Si3N4 sidewalls in the ohmic contact hole; Step 7: Deposit a Pd / Al / Pd metal stack as a metal for forming an ohmic contact by a magnetron sputtering process, and form the ohmic contact by rapid thermal annealing.
2. The process for forming a high temperature resistant 4H-SiC P-type ohmic contact according to claim 1, characterized in that: In step 4, the gate oxide is SiO2.
3. The process for forming a high temperature resistant 4H-SiC P-type ohmic contact according to claim 2, characterized in that: In step 4, after the gate oxide deposition is completed, post-oxidation annealing is performed in a NO atmosphere.
4. The process for forming a high temperature resistant 4H-SiC P-type ohmic contact according to claim 3, characterized in that: In step 6, CF4 is used as etching gas.
5. The process for forming a high temperature resistant 4H-SiC P-type ohmic contact according to claim 4, characterized in that: In step 7, the rapid thermal annealing is performed in an Ar atmosphere or an Ar+H2 mixed atmosphere.
6. A high temperature resistant 4H-SiC P-type ohmic contact prepared by the method according to any one of claims 1 to 5.