Semiconductor device and manufacturing method

Abstract

The invention provides a semiconductor device and a manufacturing method, and the method comprises the following steps: providing a substrate, and forming a grid electrode on the substrate; forming a dielectric layer covering the grid electrode on the substrate; a dielectric layer is formed on the grid electrode, a plurality of conductive nano-columns arranged in an array are formed in the dielectric layer, a connecting conductive layer is formed on the dielectric layer, the connecting conductive layer is connected with the top ends of the conductive nano-columns, the conductive nano-columns are located on the same side of the grid electrode, and the bottom ends of the conductive nano-columns are not completely located on the same plane. According to the invention, the end face of each conductive nano-column is equivalent to a micro-field plate, the improvement capability of the electric field is stronger, a channel electric field with a single peak is changed into a channel electric field with a plurality of small peaks, and the distribution of the channel electric fields is more uniform; and moreover, the smaller end surface area in the conductive nanorod can bring smaller parasitic capacitance, and the reliability of the device is enhanced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] When semiconductor devices operate under high frequency and high voltage conditions, they need to withstand extremely high drain voltages, and the electric field is unevenly distributed in the channel. The electric field lines will gather on the side of the device gate close to the drain, which can easily cause device breakdown and fail to maximize the material's voltage resistance advantages.

[0003] In order to improve the breakdown characteristics of the device, a common method is to use a field plate structure. The field plate structure is usually a metal plate, which is isolated from the device surface by a dielectric layer. It can modulate the electric field and reduce the electric field strength at the gate edge. Increasing the field plate structure can alleviate the electric field concentration at the gate edge to a certain extent and improve the voltage resistance of the device, but at the same time, the electric field lines will gather at the edge of the field plate close to the drain side, that is, there will still be a high electric field peak at the edge of the field plate, which will still affect the device performance. The current mainstream practice in the industry is to alleviate this problem by increasing the number of field plates. Some researchers have also proposed using inclined field plates, floating field plates and other structures to alleviate this problem, but in the final analysis, they are all achieved by forming a layer of metal plate on the surface of the device. Ultimately, the problem of electric field lines concentrating at the edge of the metal plate cannot be avoided; in addition, the metal plate field plate will introduce parasitic capacitance into the device, which is not conducive to the frequency characteristics of the device.

[0004] Therefore, how to provide a semiconductor device and a manufacturing method to improve the channel electric field distribution and enhance the reliability of the device has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to solve the problems in the prior art of electric field lines being concentrated at the edge of the metal field plate and low device reliability.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0007] providing a substrate, wherein a gate is formed on the substrate;

[0008] forming a dielectric layer covering the gate on the substrate;

[0009] A plurality of conductive nanopillars arranged in an array are formed in the dielectric layer, and a connecting conductive layer is formed on the dielectric layer, wherein the connecting conductive layer is connected to the top ends of the conductive nanopillars, wherein the conductive nanopillars are located on the same side of the gate, and the bottom ends of the plurality of conductive nanopillars are not completely in the same plane, and in the horizontal direction and away from the gate, the plurality of conductive nanopillars are arranged from the first column of conductive nanopillars to the Nth column of conductive nanopillars, where N is an integer not less than 2, and the distance between the bottom end of the Nth column of conductive nanopillars and the substrate is not less than the distance between the bottom end of the N-1th column of conductive nanopillars and the substrate.

[0010] Optionally, the base includes a substrate, a transition layer and a barrier layer stacked from bottom to top.

[0011] Optionally, the step of forming the conductive nanocolumns and the connecting conductive layer includes:

[0012] forming a groove at a predetermined position of the dielectric layer, wherein the groove extends from the upper surface of the dielectric layer to the interior of the dielectric layer;

[0013] forming a patterned mask layer on the dielectric layer after the grooves are formed, wherein the patterned mask layer defines positions of the conductive nanorods;

[0014] Etching the dielectric layer based on the mask layer to form a nanohole array in the dielectric layer, wherein the nanohole array includes at least two parts, a first part of the nanohole array extending from the bottom of the groove to the interior of the dielectric layer, and a second part of the nanohole array extending from the upper surface of the dielectric layer to the interior of the dielectric layer, and in a horizontal direction, a distance between the first part of the nanohole array and the gate is smaller than a distance between the second part of the nanohole array and the gate;

[0015] A conductive layer is formed on the dielectric layer, and the conductive layer extends into the nanohole array, wherein the conductive layer extending into the nanohole array constitutes the conductive nanocolumns, and the conductive layer located on the dielectric layer constitutes the connecting conductive layer.

[0016] Optionally, the dielectric layer is a passivation layer, and the material of the dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3.

[0017] Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked from bottom to top, and the conductive nanopillars include a first conductive nanopillar and a second conductive nanopillar stacked from bottom to top, and the steps of forming the conductive nanopillars and the connecting conductive layer include:

[0018] forming the first dielectric layer covering the gate on the substrate;

[0019] forming a groove at a predetermined position of the first dielectric layer, wherein the groove extends from the upper surface of the first dielectric layer to the interior of the first dielectric layer;

[0020] forming a first conductive layer on the first dielectric layer, wherein the first conductive layer extends into the groove;

[0021] forming a second conductive nanocolumn on the first conductive layer based on an anodic aluminum oxide template, wherein the second conductive nanocolumn is electrically connected to the first conductive layer;

[0022] etching the first conductive layer using the first conductive nanorods as a mask to form the first conductive nanorods;

[0023] forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the sidewalls of the conductive nanorods;

[0024] The connecting conductive layer is formed on the second dielectric layer, and the connecting conductive layer is electrically connected to the top of the second conductive nanocolumn.

[0025] Optionally, the first dielectric layer adopts a passivation layer, the material of the first dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3, and the material of the second dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3; the material of the first conductive layer includes one or more of Al, Ti, W and TiN, and the material of the second conductive nanocolumn includes one or more of Au, Ag and Cu.

[0026] The present invention also provides a semiconductor device, comprising:

[0027] a substrate, wherein a gate is provided on the substrate;

[0028] a dielectric layer, located on the substrate and covering the gate;

[0029] a plurality of conductive nanopillars located in the dielectric layer, the plurality of conductive nanopillars being arranged in an array, the conductive nanopillars being located on the same side of the gate, the bottom ends of the plurality of conductive nanopillars being not completely in the same plane, and the plurality of conductive nanopillars being arranged horizontally and away from the gate into a first column of conductive nanopillars to an Nth column of conductive nanopillars, where N is an integer not less than 2, and the distance between the bottom ends of the conductive nanopillars in the Nth column and the substrate being not less than the distance between the bottom ends of the conductive nanopillars in the N-1th column and the substrate;

[0030] The connecting conductive layer is located above the dielectric layer, and the connecting conductive layer is connected to the top of the conductive nanocolumn.

[0031] Optionally, the base includes a substrate, a transition layer and a barrier layer stacked from bottom to top.

[0032] Optionally, a groove is provided at a preset position of the dielectric layer, and the groove extends from the upper surface of the dielectric layer to the interior of the dielectric layer; the conductive nanocolumn includes at least two parts, the first part of the conductive nanocolumn extends from the bottom of the groove to the interior of the dielectric layer, and the second part of the conductive nanocolumn extends from the upper surface of the dielectric layer to the interior of the dielectric layer. In the horizontal direction, the distance between the conductive nanocolumn in the first part and the gate is greater than the distance between the conductive nanocolumn in the second part and the gate.

[0033] Optionally, the dielectric layer is a passivation layer, and the material of the dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3.

[0034] Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked from bottom to top, and the conductive nanocolumns include a first conductive nanocolumn and a second conductive nanocolumn stacked from bottom to top, wherein a groove is provided at a preset position of the first dielectric layer, and the groove extends from the upper surface of the first dielectric layer to the interior of the first dielectric layer. The conductive nanocolumn includes at least two parts, the first part of the conductive nanocolumn extends upward from the bottom of the groove and penetrates the second dielectric layer, and the second part of the conductive nanocolumn extends upward from the upper surface of the first dielectric layer and penetrates the second dielectric layer. In the horizontal direction, the distance between the conductive nanocolumn in the first part and the gate is smaller than the distance between the conductive nanocolumn in the second part and the gate. The connecting conductive layer is located above the second dielectric layer and is electrically connected to the conductive nanocolumn.

[0035] Optionally, the first dielectric layer adopts a passivation layer, the material of the first dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3, and the material of the second dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3; the material of the first conductive layer includes one or more of Al, Ti, W and TiN, and the material of the second conductive nanocolumn includes one or more of Au, Ag and Cu.

[0036] As described above, in the semiconductor device and manufacturing method of the present invention, the end face of each conductive nanocolumn is equivalent to a "micro-field plate", which has a stronger ability to improve the electric field, and can transform a single-peak channel electric field into a channel electric field with multiple small peaks, making the channel electric field distribution more uniform; and, the smaller end face area of ​​the conductive nanocolumn can bring smaller parasitic capacitance, thereby enhancing the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Shown is a process flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0038] Figure 2 It is a schematic diagram showing a substrate provided and a gate formed on the substrate in the first embodiment of the present invention.

[0039] Figure 3 It is a schematic diagram showing the formation of a dielectric layer in the first embodiment of the present invention.

[0040] Figure 4 It is a schematic diagram showing the formation of grooves in the first embodiment of the present invention.

[0041] Figure 5 Shown is a schematic diagram of forming a nanopore array in Example 1 of the present invention.

[0042] Figure 6 Shown is an enlarged schematic diagram of the nanopore in Example 1 of the present invention.

[0043] Figure 7 Shown is a schematic diagram of an exposure array in Example 1 of the present invention.

[0044] Figure 8 It is a schematic diagram showing the formation of a conductive material layer in the first embodiment of the present invention.

[0045] Figure 9 It shows a schematic diagram of etching the conductive material layer in the first embodiment of the present invention.

[0046] Figure 10 It is a schematic diagram showing the formation of the first dielectric layer in the second embodiment of the present invention.

[0047] Figure 11 It is a schematic diagram showing the formation of grooves in the second embodiment of the present invention.

[0048] Figure 12 It is a schematic diagram showing the formation of the first conductive layer in the second embodiment of the present invention.

[0049] Figure 13 It shows a schematic diagram of forming an anodized aluminum template in the second embodiment of the present invention.

[0050] Figure 14 It is a schematic diagram showing the formation of the second conductive nanorod in the second embodiment of the present invention.

[0051] Figure 15 It is a schematic diagram showing the formation of a photoresist layer in the second embodiment of the present invention.

[0052] Figure 16 It shows a schematic diagram of etching the second conductive nanorod in the second embodiment of the present invention.

[0053] Figure 17 It shows a schematic diagram of etching the first conductive layer in the second embodiment of the present invention.

[0054] Figure 18 It is a schematic diagram showing the formation of the second dielectric layer in the second embodiment of the present invention.

[0055] Figure 19 It is a schematic diagram showing the formation of a connecting conductive material layer in the second embodiment of the present invention.

[0056] Figure 20 It is a schematic diagram showing etching the connecting conductive material layer in the second embodiment of the present invention.

[0057] Component number description

[0058] 1 base

[0059] 100 substrate

[0060] 101 Transition Layer

[0061] 102 Barrier layer

[0062] 2 Gate

[0063] 3 Dielectric layer

[0064] 300 First dielectric layer

[0065] 301 Second dielectric layer

[0066] 4 grooves

[0067] 5 Nanopore Array

[0068] 6 Conductive material layer

[0069] 600 conductive nanopillars

[0070] 601 Connecting conductive layer

[0071] 602 first conductive layer

[0072] 603 Second Conductive Nanopillar

[0073] 604 First Conductive Nanopillar

[0074] 605 Connecting conductive material layer

[0075] 7 Anodized aluminum template

[0076] 8 Photoresist layer

[0077] Steps S1 to S3 DETAILED DESCRIPTION

[0078] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0079] See also Figures 1 to 20 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0080] Example 1

[0081] This embodiment provides a method for manufacturing a semiconductor device. Figure 1 , including the following steps:

[0082] S1: providing a substrate, wherein a gate is formed on the substrate;

[0083] S2: forming a dielectric layer covering the gate on the substrate;

[0084] S3: A plurality of conductive nanopillars arranged in an array are formed in the dielectric layer, and a connecting conductive layer is formed on the dielectric layer, wherein the connecting conductive layer is connected to the top ends of the conductive nanopillars, wherein the conductive nanopillars are located on the same side of the gate, and the bottom ends of the plurality of conductive nanopillars are not completely in the same plane, and in the horizontal direction and away from the gate, the plurality of conductive nanopillars are arranged into a first column of conductive nanopillars to an Nth column of conductive nanopillars, N is an integer not less than 2, and the distance between the bottom end of the Nth column of conductive nanopillars and the substrate is not less than the distance between the bottom end of the N-1th column of conductive nanopillars and the substrate.

[0085] The method for manufacturing the semiconductor device of this embodiment will be described in detail below with reference to the specific drawings.

[0086] First, see Figure 2 , performing step S1: providing a substrate 1 , on which a gate 2 is formed.

[0087] As an example, the Z direction is the device stacking direction, the X direction is the source and drain direction, and the Y direction is the gate direction.

[0088] As an example, the semiconductor device formed in this embodiment is a GaN-based HEMT device, and the substrate 1 includes a substrate 100, a transition layer 101, and a barrier layer 102 stacked from bottom to top, wherein the substrate 1 includes but is not limited to a GaN epitaxial substrate such as a Si substrate, a SiC substrate, a sapphire substrate, etc., the transition layer 101 includes but is not limited to an AlN nucleation layer, a multi-quantum well (MQW) buffer layer, an Al composition gradient buffer layer, a GaN buffer layer, etc., the barrier layer 102 includes but is not limited to an AlN epitaxial transition layer. x Ga 1-x N(0≤x≤1),In x Al 1-x Specifically, in this embodiment, the substrate 100 is a Si substrate, the transition layer 101 is a GaN epitaxial layer, and the barrier layer 102 is an Al substrate with a thickness of 15 nm. 0.2 Ga 0.8 N layers.

[0089] As an example, the gate 2 includes but is not limited to P-type GaN, P-type Al x Ga 1-x N (0≤x≤1) or other P-type gallium nitride-based wide bandgap semiconductor materials; or metal gate, metal / insulator / semiconductor gate structure (MIS / MOS), etc. Specifically, in this embodiment, the gate 2 is a P-type GaN gate with a thickness of 100nm.

[0090] Next, see Figure 3 , executing step S2: forming a dielectric layer 3 covering the gate 2 on the substrate 1.

[0091] As an example, the dielectric layer 3 is a passivation layer. The material of the dielectric layer 3 includes, but is not limited to, one or more of SiN, SiO2, SiON, AlN, and Al2O3. The method for forming the dielectric layer 3 includes, but is not limited to, common thin film deposition methods such as PECVD, SACVD, PVD, and ALD. Specifically, in this embodiment, the dielectric layer 3 is a SiN layer with a thickness of 200 nm, and is formed by PECVD.

[0092] Next, see Figures 4 to 9, executing step S3: forming a plurality of conductive nanopillars 600 arranged in an array in the dielectric layer 3, forming a connecting conductive layer 601 on the dielectric layer 3, and connecting the conductive layer 601 to the top of the conductive nanopillars 600, wherein the conductive nanopillars 600 are located on the same side of the gate 102, and the bottom ends of the plurality of conductive nanopillars 600 are not completely in the same plane, and in the horizontal direction and away from the gate 102, the plurality of conductive nanopillars 600 are arranged into a first column of conductive nanopillars to an Nth column of conductive nanopillars, N is an integer not less than 2, and the distance between the bottom end of the Nth column of conductive nanopillars and the substrate 1 is not less than the distance between the bottom end of the N-1th column of conductive nanopillars and the substrate 1.

[0093] As an example, Figure 4 As shown, an etching process is used to form a groove 4 at a preset position of the dielectric layer 3, and the groove 4 extends from the upper surface of the dielectric layer 3 to the interior of the dielectric layer 3, wherein the depth of the groove 4 ranges from 50 to 150 nm to ensure that the dielectric layer 3 is not etched through, and the width of the groove 4 ranges from 50 to 1000 nm to ensure that the width of the groove 4 is less than the distance between the device gate and the device drain; specifically, in this embodiment, the depth of the groove 4 is 100 nm and the width of the groove 4 is 800 nm.

[0094] As an example, Figure 5 As shown, a nanohole array 5 is formed in the dielectric layer 3, wherein the nanohole array 5 includes at least two parts, a first part of the nanohole array 5 extends from the bottom of the groove 4 to the inside of the dielectric layer 3, and a second part of the nanohole array 5 extends from the upper surface of the dielectric layer 3 to the inside of the dielectric layer 3. In the horizontal direction, the distance between the nanohole array in the first part and the gate 2 is smaller than the distance between the nanohole array in the second part and the gate 2.

[0095] As an example, since the first portion of the nanopore array 5 extends from the bottom of the groove 4 to the interior of the dielectric layer 3, and the second portion of the nanopore array 5 extends from the upper surface of the dielectric layer 3 to the interior of the dielectric layer 3, the distance between the bottom end of the first portion of the nanopore array 5 and the substrate 1 is smaller than the distance between the bottom end of the second portion of the nanopore array 5 and the substrate 1. In other examples, the groove 4 may not be formed, and a step-by-step etching process may be used to form the nanopore array extending from the upper surface of the dielectric layer 3 to the interior of the dielectric layer 3, with the step-by-step etching being performed to achieve different nanopore depths in different regions.

[0096] As an example, see Figure 6 The pore size L1 of a single nanopore is 20 nm to 50 nm, and the distance L2 between adjacent nanopores is 20 nm to 50 nm.

[0097] Specifically, a mask layer is formed on the dielectric layer 3 after the groove 4 is formed. The mask layer is a photoresist layer. The mask layer is patterned by deep submicron exposure to define the position of the conductive nanorods 600. Then, the dielectric layer 3 is etched based on the patterned mask layer to form the nanorod array 5. The etching depth is 20nm to 80nm. In this embodiment, the etching depth is 50nm. Figure 7 , which is a schematic diagram of the exposure array, wherein the number of nanopore arrays in the direction perpendicular to the grid bars (X direction) is 1 to 20 columns, and the number of nanopore arrays in the direction parallel to the grid bars (Y direction) is 1,000 to 30,000 rows.

[0098] Specifically, in this embodiment, the pore diameter L1 of a single nanopore is 30 nm, the distance L2 between adjacent nanopores is 30 nm, the number of nanopore arrays in the direction perpendicular to the grid bars is 10 rows, and the number of nanopore arrays in the direction parallel to the grid bars is 25,000 rows.

[0099] As an example, Figure 8 As shown, a conductive material layer 6 is formed on the dielectric layer 3, and the conductive material layer 6 extends into the nanohole array 5. The conductive material layer extending into the nanopillar array 5 constitutes the conductive nanopillars 600, and the conductive nanopillars 600 are located between the device gate and the device drain. The conductive material layer 6 is made of one or more of Au, Ag, Ti, and Cu, and is formed by methods such as ALD and CVD. Specifically, in this embodiment, the conductive material layer 6 is made of Ti and is formed by ALD, wherein the Ti deposition temperature is 400°C and the precursor is titanium tetrachloride (TiCl4).

[0100] As an example, since ALD deposition is full-surface, Figure 9 As shown, the conductive material layer in the non-field plate region is removed by etching, and the remaining conductive material layer constitutes the connecting conductive layer 601 , which is used to electrically connect the conductive nanorod 600 and the device source.

[0101] As an example, in another example, before forming the conductive material layer 6, a barrier layer is formed in the non-field plate area of ​​the surface of the dielectric layer 3, and then the conductive material layer 6 is formed, and then the barrier layer is removed to remove the conductive material layer 6 in the non-field plate area, which also falls within the scope of protection of the present invention.

[0102] As an example, the bottom ends of the conductive nanopillars 600 in this embodiment are arranged in two steps. In other examples, the bottom ends of the conductive nanopillars 600 can be arranged in a more stepped arrangement, depending on actual needs. In the extreme case, the distance between the bottom end of each column of conductive nanopillars 600 and the substrate 1 is different in the direction perpendicular to the extension of the gate bars, forming a structure similar to a tilted field plate.

[0103] As an example, the farther away from the gate, the higher the step of the conductive nanorod 600 . At a position farther from the gate and closer to the drain, the electric field strength is greater, so a thicker dielectric layer is required to prevent the device from being broken down.

[0104] At this point, a semiconductor device is manufactured. Figure 9 The semiconductor device includes a substrate 1, a gate 2, a dielectric layer 3, a plurality of conductive nanopillars 600 and a connecting conductive layer 601, wherein the gate 2 is located on the substrate 1; the dielectric layer 3 is located on the substrate 1 and covers the gate 2; the conductive nanopillars 600 are located in the dielectric layer 3, and the plurality of conductive nanopillars 600 are arranged in an array, the conductive nanopillars 600 are located on the same side of the gate 2, and the bottom ends of the plurality of conductive nanopillars 600 are not completely in the same plane. In the horizontal direction and in the direction away from the gate 2, the plurality of conductive nanopillars 600 are arranged into a first column of conductive nanopillars to an Nth column of conductive nanopillars, where N is an integer not less than 2, and the distance between the bottom end of the Nth column of conductive nanopillars and the substrate 1 is not less than the distance between the bottom end of the N-1th column of conductive nanopillars and the substrate 1; the connecting conductive layer 601 is located above the dielectric layer 3, and the connecting conductive layer 601 is connected to the top of the conductive nanopillars 600.

[0105] As an example, the base 1 includes a substrate 100, a transition layer 101 and a barrier layer 102 stacked from bottom to top, wherein the substrate 1 includes but is not limited to a commonly used gallium nitride epitaxial substrate such as a Si substrate, a SiC substrate, a sapphire substrate, the transition layer 101 includes but is not limited to a commonly used gallium nitride epitaxial transition layer such as an AlN nucleation layer, a multi-quantum well (MQW) buffer layer, an Al composition gradient buffer layer, a GaN buffer layer, and the like. The barrier layer 102 includes but is not limited to an Al x Ga 1-x N(0≤x≤1),In x Al 1-x N (0≤x≤1) and other commonly used barrier materials. Specifically, in this embodiment, the substrate 100 is a Si substrate, the transition layer 101 is a GaN epitaxial layer, and the barrier layer 102 is an Al substrate with a thickness of 15 nm. 0.2 Ga 0.8 N layers.

[0106] As an example, the gate 2 includes but is not limited to P-type GaN, P-type Al x Ga 1-x N (0≤x≤1) or other P-type gallium nitride-based wide bandgap semiconductor materials; or metal gate, metal / insulator / semiconductor gate structure (MIS / MOS), etc. Specifically, in this embodiment, the gate 2 is a P-type GaN gate with a thickness of 100nm.

[0107] As an example, the dielectric layer 3 is a passivation layer, and the material of the dielectric layer 3 includes but is not limited to one or more of SiN, SiO2, SiON, AlN and Al2O3. In this embodiment, the dielectric layer 3 is a SiN layer with a thickness of 200 nm.

[0108] As an example, the conductive nanorod 600 is located between the device gate and the device drain, and the material of the conductive nanorod 600 includes one or more of Au, Ag, Ti and Cu.

[0109] As an example, the connecting conductive layer 601 is used to electrically connect the conductive nanorod 600 and the source of the device.

[0110] As an example, the bottom ends of the conductive nanopillars 600 in this embodiment are arranged in two steps. In other examples, the bottom ends of the conductive nanopillars 600 can be arranged in a more stepped arrangement, depending on actual needs. In the extreme case, the distance between the bottom end of each column of conductive nanopillars 600 and the substrate 1 is different in the direction perpendicular to the extension of the gate bars, forming a structure similar to a tilted field plate.

[0111] As described above, in the semiconductor device and manufacturing method of this embodiment, the end face of each conductive nanocolumn is equivalent to a "micro-field plate", which has a stronger ability to improve the electric field, and can transform a single-peak channel electric field into a channel electric field with multiple small peaks, making the channel electric field distribution more uniform; and, the smaller end face area of ​​the conductive nanocolumn can bring smaller parasitic capacitance, thereby enhancing the reliability of the device.

[0112] Example 2

[0113] This embodiment provides a method for manufacturing a semiconductor device, which differs from the first embodiment in that: the dielectric layer includes a first dielectric layer and a second dielectric layer stacked from bottom to top, and the conductive nanopillars include a first conductive nanopillar and a second conductive nanopillar stacked from bottom to top.

[0114] The method for manufacturing the semiconductor device of this embodiment will be described in detail below with reference to the specific drawings.

[0115] As an example, the materials and thicknesses of the substrate 1 and the gate 2 refer to the first embodiment, which will not be described in detail here.

[0116] As an example, Figure 10 As shown, a first dielectric layer 300 is formed on the substrate 1, covering the gate 2. The first dielectric layer 300 serves as a passivation layer. The material of the first dielectric layer 300 includes, but is not limited to, one or more of SiN, SiO2, SiON, AlN, and Al2O3. The method for forming the first dielectric layer 300 includes, but is not limited to, common thin film deposition methods such as PECVD, SACVD, PVD, and ALD. Specifically, in this embodiment, the first dielectric layer 300 is a SiN layer with a thickness of 200 nm, formed using PECVD.

[0117] As an example, Figure 11 As shown, an etching process is used to form a groove 4 at a preset position of the first dielectric layer 300, and the groove 4 extends from the upper surface of the first dielectric layer 300 to the interior of the first dielectric layer 300, wherein the depth of the groove 4 ranges from 50 to 150 nm to ensure that the first dielectric layer 300 is not etched through, and the width of the groove 4 ranges from 50 to 1000 nm to ensure that the width of the groove 4 is smaller than the distance between the device gate and the device drain; specifically, in this embodiment, the depth of the groove 4 is 100 nm, and the width of the groove 4 is 800 nm.

[0118] As an example, Figure 12 As shown, a first conductive layer 602 with a thickness of 100 nm is formed on the first dielectric layer 300 by a deposition process, and the first conductive layer 602 is filled into the groove 4. The material of the first conductive layer 602 is conductive or a conductive compound that is easy to dry etch. The material of the first conductive layer 602 includes one or more of Al, Ti, W and TiN.

[0119] As an example, Figure 13 As shown, an anodized aluminum oxide template 7 (AAO) is formed on the first conductive layer 602 ; specifically, a two-step anodizing process is used to prepare the anodized aluminum oxide template 7 in oxalic acid and sulfuric acid, and then the anodized aluminum oxide template 7 is transferred to the first conductive layer 602 .

[0120] As an example, the anodized aluminum template 7 features stable chemical properties, simple processing, parallel pores that are strictly perpendicular to the substrate, and controllable and uniform pore size distribution, facilitating the subsequent formation of an array of conductive nanopillars. In this embodiment, the pore size within the anodized aluminum template 7 is 30 nm, and the spacing between adjacent pores is 30 nm.

[0121] As an example, see Figure 14, using the anodized aluminum template 7 as a mask, forming the second conductive nanocolumns 603 in the holes in the anodized aluminum template 7, the second conductive nanocolumns 603 are electrically connected to the first conductive layer 602, and then removing the anodized aluminum template 7; wherein, the method for forming the second conductive nanocolumns 603 includes but is not limited to metal evaporation, metal sputtering, vapor deposition, atomic layer deposition, etc., the thickness range of the second conductive nanocolumns 603 is 5nm to 10nm, the material of the second conductive nanocolumns 603 is a metal or metal compound with a high etching selectivity with the first conductive layer 602, and the material of the second conductive nanocolumns 603 includes one or more of Au, Ag and Cu; specifically, in this embodiment, the second conductive nanocolumns 603 are formed by metal evaporation, the thickness of the second conductive nanocolumns 603 is 10nm, and the material of the second conductive nanocolumns 603 is Au.

[0122] As an example, the anodized aluminum template 7 is prepared as a whole surface through hole, so the second conductive nanorods 603 prepared are also arranged in a whole surface periodic array. Figures 15 and 16 A photoresist layer is formed and patterned on the first conductive layer 602. The patterned photoresist layer 8 covers the second conductive nanopillars 603 in the field plate region, while exposing the second conductive nanopillars 603 in the non-field plate region. The second conductive nanopillars 603 in the non-field plate region are then removed by wet cleaning, dry etching, or other suitable processes. Specifically, in this embodiment, the second conductive nanopillars 603 are made of Au, and the second conductive nanopillars 603 in the non-field plate region are removed by immersing the nanopillars in a gold etching solution.

[0123] As an example, in another example, the holes in the anodized aluminum template 7 corresponding to the non-field plate area can also be blocked by a mask plate, and the second conductive nanocolumns 603 are formed only in the holes corresponding to the field plate area, which also falls within the scope of protection of the present invention.

[0124] As an example, Figure 17 As shown, the first conductive layer 602 is etched using the second conductive nanopillars 603 arranged in a periodic array as a mask to form the first conductive nanopillars 604. The first conductive nanopillars 604 and the second conductive nanopillars 603 together constitute the conductive nanopillars 600. Since the second conductive nanopillars 604 have a high etching selectivity with the first conductive layer 602, the second conductive nanopillars 604 will not be damaged during the etching process of the first conductive layer 602, thereby forming the conductive nanopillars 600 arranged in a whole row.

[0125] As an example, Figure 18As shown, the second dielectric layer 301 is formed by a deposition process until the conductive nanocolumns 600 are completely covered, and the tops of the conductive nanocolumns 600 are exposed by photolithography, etching, etc., wherein the material of the second dielectric layer 301 includes but is not limited to one or more of SiN, SiO2, SiON, AlN and Al2O3.

[0126] Specifically, the positions, columns, and rows of the conductive nanorods 600 are as described in the first embodiment, and are not described in detail here.

[0127] As an example, see Figures 19 to 20 A connecting conductive material layer 605 is formed on the second dielectric layer 301 by a deposition process, and the connecting conductive material layer 605 is etched to form the connecting conductive layer 601 . The connecting conductive layer 601 is electrically connected to the conductive nanorods 600 .

[0128] As an example, compared with the deep submicron exposure of the first embodiment, the anodized aluminum template of this embodiment has the advantages of simple preparation and low cost.

[0129] At this point, a semiconductor device is manufactured. Figure 20 The main difference between the semiconductor device of this embodiment and the first embodiment is that the dielectric layer 3 includes a first dielectric layer 300 and a second dielectric layer 301 stacked from bottom to top, and the conductive nanopillar 600 includes a first conductive nanopillar 604 and a second conductive nanopillar 603 stacked from bottom to top.

[0130] As an example, the first dielectric layer 300 is a passivation layer, and the material of the first dielectric layer 300 includes but is not limited to one or more of SiN, SiO 2 , SiON, AlN and Al 2 O 3 .

[0131] As an example, the material of the second dielectric layer 301 includes but is not limited to one or more of SiN, SiO 2 , SiON, AlN and Al 2 O 3 .

[0132] As an example, the material of the first conductive nanorods 604 includes one or more of Al, Ti, W, and TiN.

[0133] As an example, the material of the second conductive nanorods 603 includes one or more of Au, Ag and Cu.

[0134] As an example, the bottom ends of the conductive nanopillars 600 in this embodiment are arranged in two steps. In other examples, the bottom ends of the conductive nanopillars 600 can be arranged in a more stepped arrangement, depending on actual needs. In the extreme case, the distance between the bottom end of each column of conductive nanopillars 600 and the substrate 1 is different in the direction perpendicular to the extension of the gate bars, forming a structure similar to a tilted field plate.

[0135] As an example, in other examples, conductive nanocolumns can also be formed by nanoimprinting, steam transport, gas-liquid-solid, hydrothermal and other methods. The method of forming conductive nanocolumns is not limited to the method of Example 1 or Example 2, and can be selected according to actual needs.

[0136] In summary, in the semiconductor device and fabrication method of the present invention, the end face of each conductive nanopillar acts as a "micro-field plate," significantly improving the electric field. This transforms a single peak in the channel electric field into multiple smaller peaks, resulting in a more uniform channel electric field distribution. Furthermore, the smaller end face area of ​​the conductive nanopillars results in lower parasitic capacitance, enhancing device reliability. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial applicability.

[0137] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, on which a gate is formed; forming a dielectric layer covering the gate on the substrate; A plurality of conductive nanocolumns arranged in an array are formed in the dielectric layer, and a connecting conductive layer is formed on the dielectric layer, wherein the connecting conductive layer is connected to the top ends of the conductive nanocolumns, wherein the conductive nanocolumns are located on the same side of the gate, and the bottom ends of the plurality of conductive nanocolumns are not completely in the same plane, and in the horizontal direction and in the direction away from the gate, the plurality of conductive nanocolumns are arranged from the first column of conductive nanocolumns to the Nth column of conductive nanocolumns, N being an integer not less than 2, and the distance between the bottom end of the Nth column of conductive nanocolumns and the substrate is not less than the distance between the bottom end of the N-1th column of conductive nanocolumns and the substrate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The base comprises a substrate, a transition layer and a barrier layer which are stacked from bottom to top.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the conductive nanorods and the connecting conductive layer include: forming a groove at a preset position of the dielectric layer, wherein the groove extends from the upper surface of the dielectric layer to the interior of the dielectric layer; forming a patterned mask layer on the dielectric layer after the grooves are formed, wherein the patterned mask layer defines the positions of the conductive nanocolumns; Etching the dielectric layer based on the mask layer to form a nanohole array in the dielectric layer, wherein the nanohole array includes at least two parts, a first part of the nanohole array extends from the bottom of the groove to the inside of the dielectric layer, and a second part of the nanohole array extends from the upper surface of the dielectric layer to the inside of the dielectric layer, and in the horizontal direction, the distance between the first part of the nanohole array and the gate is smaller than the distance between the second part of the nanohole array and the gate; A conductive layer is formed on the dielectric layer, and the conductive layer extends into the nanohole array, wherein the conductive layer extending into the nanohole array constitutes the conductive nanocolumn, and the conductive layer on the dielectric layer constitutes the connecting conductive layer.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The dielectric layer is a passivation layer, and the material of the dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric layer includes a first dielectric layer and a second dielectric layer stacked from bottom to top, the conductive nanocolumns include a first conductive nanocolumn and a second conductive nanocolumn stacked from bottom to top, and the steps of forming the conductive nanocolumns and the connecting conductive layer include: forming the first dielectric layer covering the gate on the substrate; forming a groove at a preset position of the first dielectric layer, wherein the groove extends from the upper surface of the first dielectric layer to the interior of the first dielectric layer; forming a first conductive layer on the first dielectric layer, wherein the first conductive layer extends into the groove; forming the second conductive nanocolumn on the first conductive layer based on an anodic aluminum oxide template, wherein the second conductive nanocolumn is electrically connected to the first conductive layer; Using the first conductive nanorods as a mask, etching the first conductive layer to form the first conductive nanorods; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the sidewalls of the conductive nanorods; The connecting conductive layer is formed on the second dielectric layer, and the connecting conductive layer is electrically connected to the top of the second conductive nanocolumn.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The first dielectric layer adopts a passivation layer, the material of the first dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3, the material of the second dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3; the material of the first conductive layer includes one or more of Al, Ti, W and TiN, and the material of the second conductive nanocolumn includes one or more of Au, Ag and Cu.

7. A semiconductor device, characterized in that: include: A substrate, wherein a gate is disposed on the substrate; A dielectric layer, located on the substrate and covering the gate; A plurality of conductive nanopillars are located in the dielectric layer, the plurality of conductive nanopillars are arranged in an array, the conductive nanopillars are located on the same side of the gate, and the bottom ends of the plurality of conductive nanopillars are not completely in the same plane, and in the horizontal direction and in the direction away from the gate, the plurality of conductive nanopillars are arranged from the first column of conductive nanopillars to the Nth column of conductive nanopillars, N is an integer not less than 2, and the distance between the bottom end of the Nth column of conductive nanopillars and the substrate is not less than the distance between the bottom end of the N-1th column of conductive nanopillars and the substrate; The connecting conductive layer is located above the dielectric layer, and the connecting conductive layer is connected to the top of the conductive nanocolumn.

8. The semiconductor device according to claim 7, wherein: The base comprises a substrate, a transition layer and a barrier layer which are stacked from bottom to top.

9. The semiconductor device according to claim 7, wherein: A groove is provided at a preset position of the dielectric layer, and the groove extends from the upper surface of the dielectric layer to the interior of the dielectric layer; the conductive nanocolumn includes at least two parts, the first part of the conductive nanocolumn extends from the bottom of the groove to the interior of the dielectric layer, and the second part of the conductive nanocolumn extends from the upper surface of the dielectric layer to the interior of the dielectric layer. In the horizontal direction, the distance between the conductive nanocolumn in the first part and the gate is smaller than the distance between the conductive nanocolumn in the second part and the gate.

10. The semiconductor device according to claim 9, wherein: The dielectric layer is a passivation layer, and the material of the dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3.

11. The semiconductor device according to claim 7, wherein: The dielectric layer includes a first dielectric layer and a second dielectric layer stacked from bottom to top, and the conductive nanocolumn includes a first conductive nanocolumn and a second conductive nanocolumn stacked from bottom to top, wherein a groove is provided at a preset position of the first dielectric layer, and the groove extends from the upper surface of the first dielectric layer to the interior of the first dielectric layer. The conductive nanocolumn includes at least two parts, the first part of the conductive nanocolumn extends upward from the bottom of the groove and penetrates the second dielectric layer, and the second part of the conductive nanocolumn extends upward from the upper surface of the first dielectric layer and penetrates the second dielectric layer. In the horizontal direction, the distance between the conductive nanocolumn in the first part and the gate is smaller than the distance between the conductive nanocolumn in the second part and the gate. The connecting conductive layer is located above the second dielectric layer and is electrically connected to the conductive nanocolumn.

12. The semiconductor device according to claim 11, characterized in that: The first dielectric layer adopts a passivation layer, the material of the first dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3, the material of the second dielectric layer includes one or more of SiN, SiO2, SiON, AlN and Al2O3; the material of the first conductive layer includes one or more of Al, Ti, W and TiN, and the material of the second conductive nanocolumn includes one or more of Au, Ag and Cu.

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