Novel method for improving double-sided rate of Topcon solar cell

Abstract

The invention discloses a novel Topcon solar cell double-sided rate improvement method, which belongs to the field of Topcon cells, and comprises the following steps: selecting an N-type silicon substrate and carrying out double-sided texturing to obtain a textured silicon wafer; performing boron diffusion on the front surface of the textured silicon wafer to form a P + doping layer and a borosilicate glass layer; removing the borosilicate glass layer on the front surface of the silicon wafer after boron diffusion and the doped layer expanded on the back surface and the edge of the silicon wafer; a first tunneling oxide layer is formed on the surface of the silicon wafer substrate, and three doped polycrystalline silicon layers with different densities are deposited and formed without deposition pressure; performing low-pressure oxidation to form a silicon dioxide masking film, and then performing phosphorus diffusion segmented propulsion to obtain an initial battery piece; removing the wound-plated polycrystalline silicon on the front surface and the edge of the primary battery piece; printing silver aluminum paste, printing silver paste on the back surface, drying and sintering, and then carrying out light injection treatment. The double-sided rate of the Topcon battery is improved through the cooperation of the steps of controlling the alkali polishing process time, reducing the size of a back tower footing after alkali polishing, reducing the number of silk-screen printing grid lines, reducing the width of the grid lines and the like.

Description

Technical Field

[0001] The invention relates to the field of Topcon cells, and in particular to a novel method for improving the bifaciality of Topcon solar cells. Background Art

[0002] The Topcon cell is a tunneling oxide passivated contact solar cell that uses N-type silicon as a substrate. By preparing an ultra-thin layer of silicon oxide on the back of the cell and depositing a thin layer of doped silicon, a passivated contact structure is formed, which effectively reduces surface recombination and metal contact recombination, thereby improving energy conversion efficiency. Bifaciality is an important indicator of a cell. Photovoltaic modules produced by high bifaciality cells have better power generation performance. Generally, photovoltaic modules produced by high bifaciality cells have better power generation performance. Improving the efficiency of the back of the cell can increase the bifaciality of solar energy. The solar bifaciality refers to the ratio of the power generation of the double side of the solar panel to the power generation of the single side, and is usually used to evaluate the power generation efficiency of solar panels. The higher the bifaciality, the more effective it means that the panel can use light on both sides, thereby improving the overall power generation efficiency.

[0003] In order to improve the double-sidedness of solar energy, a double-sided cell structure is used, that is, both sides have P-type and N-type silicon layers, and the two sides are connected to each other through the P-N junction. When sunlight shines on the front of the solar double-sided panel, it will stimulate the P-N junction on the front to cause electron movement, causing the electrons to gather in the P area to generate current. The back side is also exposed to sunlight, and the reflected light will also be absorbed and converted into electrical energy, realizing double-sided power generation. Due to its high efficiency, strong reliability, energy saving and environmental protection, it has been widely used in the field of solar power generation. At the same time, in cloudy weather or when direct sunlight is insufficient, the solar double-sidedness can also improve the overall power generation efficiency by absorbing reflected light on the back side to generate electricity.

[0004] At present, domestic and foreign solar panel manufacturers have begun to launch bifacial products, and their applications are expanding. The bifaciality of mass-produced Topcon bifacial cells in the industry is generally 80% to 83%, which makes the bifaciality of bifacial modules made using these bifacial cells in conventional cell circuit arrangement methods also stay in the range of 70% to 84% and cannot be improved.

[0005] In view of this, the inventor conducted in-depth research on this demand, and thus the present case was produced. Summary of the invention

[0006] In order to solve the problems that the bifaciality of mass-produced Topcon bifacial cells in the prior art is generally 80% to 84%, and the bifaciality of bifacial modules made using these bifacial cells in a conventional cell circuit arrangement method also remains in the range of 70% to 85% and cannot be improved, the present invention provides a novel Topcon solar cell bifaciality improvement method, comprising the following steps:

[0007] Step 1, selecting an N-type silicon substrate and performing double-sided texturing to form a pyramid structure to obtain a textured silicon wafer;

[0008] Step 2: Diffusing boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer;

[0009] Step 3, removing the borosilicate glass layer on the front side of the silicon wafer after the boron diffusion in Step 2 and the doped layer on the back side and edge of the silicon wafer by alkali polishing;

[0010] Step 4, using LPCVD equipment to form a first tunneling oxide layer on the surface of the silicon wafer substrate, and then depositing a first doped polysilicon layer, a second doped polysilicon layer and a third doped polysilicon layer on the surface of the first tunneling oxide layer using different deposition pressures;

[0011] Step 5: low-pressure oxidation to form a silicon dioxide masking film, followed by phosphorus diffusion in stages, forming a PN junction on the back of the silicon wafer to obtain a preliminary cell;

[0012] Step 6, removing the polysilicon on the front and edge of the primary cell;

[0013] Step seven, printing silver-aluminum paste on the front side of the silicon wafer obtained in step six and printing silver paste on the back side, and performing light injection treatment after drying and sintering.

[0014] Furthermore, in the step three, a tank-type alkali polishing machine is used, the polishing tank process time is 170 to 190 seconds, and the tower base size after alkali polishing is 7.5 to 8.5 μm.

[0015] Furthermore, in the step four, LPCVD equipment is used, oxygen is introduced under normal pressure, and the reaction is carried out at a temperature of 600-620°C for 950-1200s to form a tunneling oxide layer on the surface of the silicon substrate. Subsequently, the tunneling oxide layer surface is reacted at a pressure of 300-350mtorr and a temperature of 590-640°C for 670-700s to generate a first doped polysilicon layer.

[0016] Furthermore, the thickness of the tunnel oxide layer is 1.5-2 nm, and the thickness of the first doped polysilicon layer is 20-40 nm.

[0017] Furthermore, the reaction is carried out for 280 to 300 seconds at a pressure of 200 to 250 mtorr and a temperature of 590 to 640° C. to form a second doped polysilicon layer on the first doped polysilicon layer.

[0018] Furthermore, the reaction is carried out for 200 to 220 seconds at a pressure of 100 to 150 mtorr and a temperature of 590 to 640° C. to form a third doped polysilicon layer on the second doped polysilicon layer.

[0019] Furthermore, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 100-130 nm.

[0020] Furthermore, in the step five, a low-pressure diffusion deposition device is used to oxidize and form a silicon dioxide masking film under the conditions of a pressure of 100-200 mtorr, an oxygen flow rate of 900-1200 sccm, and a reaction time of 200-300 s, and POCl3 is used for phosphorus diffusion. Low-temperature deposition is first performed at a deposition temperature of 750-830°C, and then the process is carried out in stages: first, the temperature is increased at a temperature of 860-930°C for 10-20 min, and then the temperature is reduced at 860-900°C for 10-20 min. Finally, a post-oxidation process is performed and the temperature is reduced to 720-750°C to complete the process, thereby forming a back PN junction.

[0021] Furthermore, in step seven, the width of the back side gate lines is 11.5-13.5 μm, and the number of the back side gate lines is 154-174.

[0022] The present invention also provides a Topcon solar cell, which is prepared by the above-mentioned preparation method, and comprises a silicon wafer, wherein a P+ diffusion layer, an aluminum oxide passivation layer, a front anti-reflection layer and a front metal electrode are sequentially arranged on the front side of the silicon wafer, and a tunneling oxide layer, a first doped polysilicon layer, a second doped polysilicon layer, a third doped polysilicon layer, a back anti-reflection layer and a back metal electrode are sequentially arranged on the back side of the silicon wafer;

[0023] The front metal electrode penetrates the front anti-reflection layer, the aluminum oxide passivation layer and the P+ diffusion layer to form an ohmic contact; the back metal electrode penetrates the back anti-reflection layer and the doped polysilicon layer to form an ohmic contact.

[0024] Beneficial effects:

[0025] The beneficial effects produced by the technical solution of the present invention are as follows:

[0026] (1) By controlling the alkali polishing process time, the amount of automatic chemical addition is further optimized, the size of the tower base on the back of the cell after alkali polishing is controlled and reduced, and then a high-thickness polysilicon layer is prepared by LPCVD, and the number and width of screen-printed grid lines are reduced. The combination of the above technical steps ultimately improves the bifaciality of the Topcon cell. The three layers of doped polysilicon layers prepared at the same time allow the doped polysilicon layers to be deposited at different densities under different pressures, and the generated doped polysilicon layers have better uniformity, thereby increasing the advancement temperature of phosphorus diffusion and improving the crystallization ability.

[0027] (2) Because the solubility of phosphorus atoms in SiO2 and Si is too different at high temperatures, the diffusion rate of phosphorus in silicon is much greater than that in silicon dioxide, resulting in P diffusion. By increasing the oxygen flow rate before phosphorus diffusion, a thicker silicon dioxide masking film is formed on the back of the battery, which can slow down the diffusion rate of phosphorus, thereby greatly increasing the advancement temperature of phosphorus diffusion and improving the crystallization ability. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Therefore, the following detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] This embodiment controls the alkali polishing process time, further optimizes the amount of automatic chemical addition, controls and reduces the size of the tower base on the back of the cell after alkali polishing, then prepares a high-thickness Poly silicon layer by LPCVD, and reduces the number and width of screen-printed grid lines. The combination of the above technical steps ultimately improves the bifaciality of the Topcon cell. The specific implementation is as follows:

[0030] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0031] Step 1, selecting an N-type silicon substrate and performing double-sided texturing to form a pyramid structure to obtain a textured silicon wafer;

[0032] Step 2: Diffusing boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer;

[0033] Step 3, removing the borosilicate glass layer on the front side of the silicon wafer after the boron diffusion in Step 2 and the doped layer on the back side and edge of the silicon wafer by alkali polishing;

[0034] Step 4: using LPCVD equipment to form a first tunnel oxide layer on the surface of the silicon wafer substrate, and then depositing a first doped polysilicon layer, a second doped polysilicon layer and a third doped polysilicon layer on the surface of the first tunnel oxide layer using different deposition pressures (gradient pressure reduction);

[0035] Step 5: low-pressure oxidation to form a silicon dioxide masking film, followed by phosphorus diffusion in stages, forming a PN junction on the back of the silicon wafer to obtain a preliminary cell;

[0036] Step 6, removing the polysilicon on the front and edge of the primary cell;

[0037] Step seven, printing silver-aluminum paste on the front side of the silicon wafer obtained in step six and printing silver paste on the back side, and performing light injection treatment after drying and sintering.

[0038] As a preferred embodiment, in the step three, a tank-type alkali polishing machine is used, the polishing tank process time is 170 to 190 seconds, and the tower base size after alkali polishing is 7.5 to 8.5 μm.

[0039] As a preferred embodiment, in the step four, LPCVD equipment is used, oxygen is introduced under normal pressure, and the reaction is carried out at a temperature of 600-620°C for 950-1200s to form a tunneling oxide layer on the surface of the silicon substrate. Subsequently, the tunneling oxide layer surface is reacted at a pressure of 300-350mtorr and a temperature of 590-640°C for 670-700s to generate a first doped polysilicon layer.

[0040] As a preferred implementation, the thickness of the tunnel oxide layer is 1.5-2 nm, and the thickness of the first doped polysilicon layer is 20-40 nm.

[0041] As a preferred implementation, the reaction is carried out for 280 to 300 seconds under the conditions of a pressure of 200 to 250 mtorr and a temperature of 590 to 640° C. to form a second doped polysilicon layer on the first doped polysilicon layer.

[0042] As a preferred implementation, the reaction is carried out for 200 to 230 seconds under the conditions of a pressure of 100 to 150 mtorr and a temperature of 590 to 640° C. to form a third doped polysilicon layer on the second doped polysilicon layer.

[0043] As a preferred implementation manner, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 100-130 nm.

[0044] As a preferred embodiment, in the step five, a low-pressure diffusion deposition equipment is used to oxidize and form a silicon dioxide masking film under the conditions of a pressure of 100-200 mtorr, an oxygen flow rate of 900-1200 sccm, and a reaction time of 200-300 s, and POCl3 is used for phosphorus diffusion. Low-temperature deposition is first performed at a deposition temperature of 750-830°C, and then the process is advanced in stages: first, the temperature is increased at a temperature of 860-930°C for 10-20 min, and then the temperature is reduced at 860-900°C for 10-20 min, and finally a post-oxidation process is performed and the temperature is reduced to 720-750°C to complete the process to form a back PN junction.

[0045] As a preferred implementation, in step seven, the width of the back side gate lines is 11.5-13.5 μm, and the number of the back side gate lines is 154-174.

[0046] The present invention also provides a Topcon solar cell, which is prepared by the above-mentioned preparation method, and comprises a silicon wafer, wherein a P+ diffusion layer, an aluminum oxide passivation layer, a front anti-reflection layer and a front metal electrode are sequentially arranged on the front side of the silicon wafer, and a tunneling oxide layer, a first doped polysilicon layer, a second doped polysilicon layer, a third doped polysilicon layer, a back anti-reflection layer and a back metal electrode are sequentially arranged on the back side of the silicon wafer;

[0047] The front metal electrode penetrates the front anti-reflection layer, the aluminum oxide passivation layer and the P+ diffusion layer to form an ohmic contact; the back metal electrode penetrates the back anti-reflection layer and the doped polysilicon layer to form an ohmic contact.

[0048] The beneficial effects of the preparation process of the N-type Topcon solar cell in the present invention are further reviewed through several groups of embodiments.

[0049] Embodiment 1:

[0050] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0051] Step 1: Select an N-type silicon substrate and perform double-sided texturing to form a pyramid structure to obtain a textured silicon wafer.

[0052] Step 2: Diffuse boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer, and then remove the borosilicate glass layer, the back side and the doped layer around the edge.

[0053] Step three, using a tank-type alkali polishing machine, shorten the polishing tank process time to 190s, and improve the size of the tower base after alkali polishing by shortening the time, and its size is 7.5μm.

[0054] Step 4, using LPCVD equipment, introducing oxygen at normal pressure, and reacting at 600°C for 1000s to form a 1.5nm tunneling oxide layer on the surface of the silicon substrate, and then reacting on the surface of the tunneling oxide layer at a pressure of 320mtorr and a temperature of 600°C for 690s to generate a first doped polysilicon layer with a thickness of 30nm; reacting at a pressure of 220mtorr and a temperature of 600°C for 290s to generate a second doped polysilicon layer; reacting at a pressure of 130mtorr and a temperature of 620°C for 200s to generate a third doped polysilicon layer, wherein the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm.

[0055] Step five, use low-pressure diffusion deposition equipment to oxidize to form a silicon dioxide masking film under the conditions of a pressure of 150mtorr, an oxygen flow rate of 1000sccm, and a reaction time of 250s, use POCl3 for phosphorus diffusion, first low-temperature deposition, the deposition temperature is 790°C, and then advance in stages: first heat up at 900°C for 15min, then cool down at 870°C for 15min, and finally perform a post-oxidation process and cool to 730°C to complete the process to form a back PN junction.

[0056] Step six, remove the coated polysilicon on the front and edge of the preliminary cell, use the ALD process to grow an aluminum oxide passivation layer on the front of the preliminary cell, and use the PECVD method to deposit a silicon nitride anti-reflection layer on the front and back of the preliminary cell.

[0057] Step seven, print silver aluminum paste on the front side of the silicon wafer, optimize the width and number of the back gate lines to 164 gate lines and 12.5 μm line width, and perform light injection treatment after drying and sintering.

[0058] Embodiment 2:

[0059] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0060] Step 1: Select an N-type silicon substrate and perform double-sided texturing to form a pyramid structure to obtain a textured silicon wafer.

[0061] Step 2: Diffuse boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer, and then remove the borosilicate glass layer, the back side and the doped layer around the edge.

[0062] Step three, using a tank-type alkali polishing machine, shorten the polishing tank process time to 170s, and improve the size of the tower base after alkali polishing by shortening the time, and its size is 8μm.

[0063] Step 4, using LPCVD equipment, introducing oxygen at normal pressure, and reacting at 620°C for 1200s to form a 2nm tunneling oxide layer on the surface of the silicon substrate, and then reacting on the surface of the tunneling oxide layer at a pressure of 350mtorr and a temperature of 640°C for 700s to generate a first doped polysilicon layer with a thickness of 40nm; reacting at a pressure of 250mtorr and a temperature of 640°C for 300s to generate a second doped polysilicon layer; reacting at a pressure of 150mtorr and a temperature of 640°C for 220s to generate a third doped polysilicon layer, wherein the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm.

[0064] Step five, use low-pressure diffusion deposition equipment to oxidize to form a silicon dioxide masking film under the conditions of a pressure of 200mtorr, an oxygen flow rate of 1200sccm, and a reaction time of 300s, use POCl3 for phosphorus diffusion, first low-temperature deposition, the deposition temperature is 830°C, and then advance in stages: first heat up at a temperature of 930°C for 20min, then cool down at 900°C for 20min, and finally perform a post-oxidation process and cool to 750°C to complete the process to form a back PN junction.

[0065] Step six, remove the coated polysilicon on the front and edge of the preliminary cell, use the ALD process to grow an aluminum oxide passivation layer on the front of the preliminary cell, and use the PECVD method to deposit a silicon nitride anti-reflection layer on the front and back of the preliminary cell.

[0066] Step seven, print silver aluminum paste on the front side of the silicon wafer, optimize the width and number of the back gate lines to 164 gate lines and 12.5 μm line width, and perform light injection treatment after drying and sintering.

[0067] Embodiment 3:

[0068] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0069] Step 1: Select an N-type silicon substrate and perform double-sided texturing to form a pyramid structure to obtain a textured silicon wafer.

[0070] Step 2: Diffuse boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer, and then remove the borosilicate glass layer, the back side and the doped layer around the edge.

[0071] Step three, using a tank-type alkali polishing machine, shorten the polishing tank process time to 190s, and improve the size of the tower base after alkali polishing by shortening the time, and its size is 7.7μm.

[0072] Step 4, using LPCVD equipment, introducing oxygen at normal pressure, and reacting at 620°C for 1100s to form a 1.5nm tunneling oxide layer on the surface of the silicon substrate, and then reacting on the surface of the tunneling oxide layer at a pressure of 300mtorr and a temperature of 640°C for 700s to generate a first doped polysilicon layer with a thickness of 20nm; reacting at a pressure of 250mtorr and a temperature of 590°C for 300s to generate a second doped polysilicon layer; reacting at a pressure of 150mtorr and a temperature of 590°C for 200s to generate a third doped polysilicon layer, wherein the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 100nm.

[0073] Step five, use low-pressure diffusion deposition equipment to oxidize to form a silicon dioxide masking film under the conditions of a pressure of 150mtorr, an oxygen flow rate of 1200sccm, and a reaction time of 200s, use POCl3 for phosphorus diffusion, first low-temperature deposition, the deposition temperature is 750℃, and then advance in stages: first heat up at 860℃ for 20min, then cool down at 900℃ for 20min, and finally perform a post-oxidation process and cool to 750℃ to complete the process to form a back PN junction.

[0074] Step six, remove the coated polysilicon on the front and edge of the preliminary cell, use the ALD process to grow an aluminum oxide passivation layer on the front of the preliminary cell, and use the PECVD method to deposit a silicon nitride anti-reflection layer on the front and back of the preliminary cell.

[0075] Step seven, print silver aluminum paste on the front side of the silicon wafer, optimize the width and number of the back gate lines to 155 gate lines and 13μm line width, and perform light injection treatment after drying and sintering.

[0076] Embodiment 4:

[0077] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0078] Step 1: Select an N-type silicon substrate and perform double-sided texturing to form a pyramid structure to obtain a textured silicon wafer.

[0079] Step 2: Diffuse boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer, and then remove the borosilicate glass layer, the back side and the doped layer around the edge.

[0080] Step three, using a tank-type alkali polishing machine, shorten the polishing tank process time to 190s, and improve the size of the tower base after alkali polishing by shortening the time, and its size is 8μm.

[0081] Step 4, using LPCVD equipment, introducing oxygen at normal pressure, and reacting at 600°C for 1000s to form a 2nm tunneling oxide layer on the surface of the silicon substrate, and then reacting on the surface of the tunneling oxide layer at a pressure of 300mtorr and a temperature of 590°C for 700s to generate a first doped polysilicon layer with a thickness of 30nm; reacting at a pressure of 250mtorr and a temperature of 590°C for 300s to generate a second doped polysilicon layer; reacting at a pressure of 150mtorr and a temperature of 640°C for 200s to generate a third doped polysilicon layer, wherein the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 115nm.

[0082] Step five, use low-pressure diffusion deposition equipment to oxidize to form a silicon dioxide masking film under the conditions of a pressure of 150mtorr, an oxygen flow rate of 1200sccm, and a reaction time of 200s, use POCl3 for phosphorus diffusion, first low-temperature deposition, the deposition temperature is 750℃, and then advance in stages: first heat up at 930℃ for 10min, then cool down at 900℃ for 20min, and finally perform a post-oxidation process and cool to 720℃ to complete the process to form a back PN junction.

[0083] Step six, remove the coated polysilicon on the front and edge of the preliminary cell, use the ALD process to grow an aluminum oxide passivation layer on the front of the preliminary cell, and use the PECVD method to deposit a silicon nitride anti-reflection layer on the front and back of the preliminary cell.

[0084] Step seven, print silver aluminum paste on the front side of the silicon wafer, optimize the width and number of the back gate lines to 174 gate lines and 11.5 μm line width, and perform light injection treatment after drying and sintering.

[0085] Embodiment 5:

[0086] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0087] Step 1: Select an N-type silicon substrate and perform double-sided texturing to form a pyramid structure to obtain a textured silicon wafer.

[0088] Step 2: Diffuse boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer, and then remove the borosilicate glass layer, the back side and the doped layer around the edge.

[0089] Step three, using a tank-type alkali polishing machine, shorten the polishing tank process time to 190s, and improve the size of the tower base after alkali polishing by shortening the time, and its size is 8.5μm.

[0090] Step 4: Using LPCVD equipment, oxygen is introduced under normal pressure, and the reaction is carried out at 600°C for 950s to form a 1.5nm tunneling oxide layer on the surface of the silicon substrate, and then the first doped polysilicon layer is formed at a pressure of 300mtorr and a temperature of 590°C for 700s on the surface of the tunneling oxide layer, and the thickness of the first doped polysilicon layer is 20nm; the second doped polysilicon layer is formed at a pressure of 200mtorr and a temperature of 640°C for 300s; the third doped polysilicon layer is formed at a pressure of 100mtorr and a temperature of 640°C for 200s. The total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm.

[0091] Step five, use low-pressure diffusion deposition equipment to oxidize to form a silicon dioxide masking film under the conditions of a pressure of 150mtorr, an oxygen flow rate of 1200sccm, and a reaction time of 300s, use POCl3 for phosphorus diffusion, first low-temperature deposition, the deposition temperature is 750℃, and then advance in stages: first heat up at 860℃ for 10min, then cool down at 900℃ for 15min, and finally perform a post-oxidation process and cool to 750℃ to complete the process to form a back PN junction.

[0092] Step six, remove the coated polysilicon on the front and edge of the preliminary cell, use the ALD process to grow an aluminum oxide passivation layer on the front of the preliminary cell, and use the PECVD method to deposit a silicon nitride anti-reflection layer on the front and back of the preliminary cell.

[0093] Step seven, print silver aluminum paste on the front side of the silicon wafer, optimize the width and number of the back gate lines to 154 gate lines and 13.5 μm line width, and perform light injection treatment after drying and sintering.

[0094] Embodiment 6:

[0095] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0096] Step 1: Select an N-type silicon substrate and perform double-sided texturing to form a pyramid structure to obtain a textured silicon wafer.

[0097] Step 2: Diffuse boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer, and then remove the borosilicate glass layer, the back side and the doped layer around the edge.

[0098] Step three, using a tank-type alkali polishing machine, shorten the polishing tank process time to 190s, and improve the size of the tower base after alkali polishing by shortening the time, and its size is 8.5μm.

[0099] Step 4, using LPCVD equipment, introducing oxygen at normal pressure, and reacting at 620°C for 1200s to form a 2nm tunneling oxide layer on the surface of the silicon substrate, and then reacting on the surface of the tunneling oxide layer at a pressure of 350mtorr and a temperature of 640°C for 700s to generate a first doped polysilicon layer with a thickness of 30nm; reacting at a pressure of 250mtorr and a temperature of 640°C for 300s to generate a second doped polysilicon layer; reacting at a pressure of 150mtorr and a temperature of 640°C for 200s to generate a third doped polysilicon layer, wherein the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 130nm.

[0100] Step five, use low-pressure diffusion deposition equipment to oxidize to form a silicon dioxide masking film under the conditions of a pressure of 200mtorr, an oxygen flow rate of 1200sccm, and a reaction time of 300s, use POCl3 for phosphorus diffusion, first low-temperature deposition, the deposition temperature is 830°C, and then advance in stages: first heat up at a temperature of 930°C for 20min, then cool down at 900°C for 20min, and finally perform a post-oxidation process and cool to 750°C to complete the process to form a back PN junction.

[0101] Step six, remove the coated polysilicon on the front and edge of the preliminary cell, use the ALD process to grow an aluminum oxide passivation layer on the front of the preliminary cell, and use the PECVD method to deposit a silicon nitride anti-reflection layer on the front and back of the preliminary cell.

[0102] Step seven, print silver aluminum paste on the front side of the silicon wafer, optimize the width and number of the back gate lines to 164 gate lines and 12.5 μm line width, and perform light injection treatment after drying and sintering.

[0103] Embodiment 7:

[0104] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0105] Step 1: Select an N-type silicon substrate and perform double-sided texturing to form a pyramid structure to obtain a textured silicon wafer.

[0106] Step 2: Diffuse boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer, and then remove the borosilicate glass layer, the back side and the doped layer around the edge.

[0107] Step three, using a tank-type alkali polishing machine, shorten the polishing tank process time to 190s, and improve the size of the tower base after alkali polishing by shortening the time, and its size is 8.1μm.

[0108] Step 4, using LPCVD equipment, introducing oxygen at normal pressure, and reacting at 600°C for 1000s to form a 1.5 tunneling oxide layer on the surface of the silicon substrate, and then reacting on the surface of the tunneling oxide layer at a pressure of 300mtorr and a temperature of 590°C for 700s to generate a first doped polysilicon layer with a thickness of 30nm; reacting at a pressure of 200mtorr and a temperature of 590°C for 300s to generate a second doped polysilicon layer; reacting at a pressure of 100mtorr and a temperature of 590°C for 200s to generate a third doped polysilicon layer, wherein the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm.

[0109] Step five, use low-pressure diffusion deposition equipment to oxidize to form a silicon dioxide masking film under the conditions of a pressure of 150mtorr, an oxygen flow rate of 1200sccm, and a reaction time of 300s, use POCl3 for phosphorus diffusion, first low-temperature deposition, the deposition temperature is 750℃, and then advance in stages: first heat up at 860℃ for 10min, then cool down at 860℃ for 10min, and finally perform a post-oxidation process and cool to 720℃ to complete the process to form a back PN junction.

[0110] Step six, remove the coated polysilicon on the front and edge of the preliminary cell, use the ALD process to grow an aluminum oxide passivation layer on the front of the preliminary cell, and use the PECVD method to deposit a silicon nitride anti-reflection layer on the front and back of the preliminary cell.

[0111] Step seven, print silver aluminum paste on the front side of the silicon wafer, optimize the width and number of the back gate lines to 164 gate lines and 12.5 μm line width, and perform light injection treatment after drying and sintering.

[0112] The N-type Topcon solar cells obtained in the above examples 1-7 were subjected to performance tests, and the results are as follows:

[0113] Table 1 Performance test results of N-type Topcon solar cells in each group of examples

[0114]

[0115]

[0116] Comparative Example 1:

[0117] A novel method for improving the bifaciality of Topcon solar cells comprises the following steps:

[0118] Step 1: Select an N-type silicon substrate and perform double-sided texturing to form a pyramid structure to obtain a textured silicon wafer.

[0119] Step 2: Diffuse boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer, and then remove the borosilicate glass layer, the back side and the doped layer around the edge.

[0120] Step three, using a tank-type alkali polishing machine, shorten the polishing tank process time to 190s, and improve the size of the tower base after alkali polishing by shortening the time, and its size is 9.5μm.

[0121] Step 4: Using LPCVD equipment, oxygen is introduced under normal pressure, and the reaction is carried out at 600°C for 1000s to form a 1.5nm tunneling oxide layer on the surface of the silicon substrate, and then the first doped polysilicon layer is formed at a pressure of 320mtorr and a temperature of 600°C for 690s on the surface of the tunneling oxide layer, and the thickness is 30nm; the second doped polysilicon layer is formed at a pressure of 220mtorr and a temperature of 600°C for 290s; the third doped polysilicon layer is formed at a pressure of 130mtorr and a temperature of 620°C for 200s. The total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 155nm.

[0122] Step five, use low-pressure diffusion deposition equipment to oxidize to form a silicon dioxide masking film under the conditions of a pressure of 150mtorr, an oxygen flow rate of 1000sccm, and a reaction time of 250s, use POCl3 for phosphorus diffusion, first low-temperature deposition, the deposition temperature is 790°C, and then advance in stages: first heat up at 900°C for 15 minutes, then cool down at 870°C for 15 minutes, and finally perform a post-oxidation process and cool to 730°C to complete the process to form a back PN junction.

[0123] Step six, remove the coated polysilicon on the front and edge of the preliminary cell, use the ALD process to grow an aluminum oxide passivation layer on the front of the preliminary cell, and use the PECVD method to deposit a silicon nitride anti-reflection layer on the front and back of the preliminary cell.

[0124] Step seven, print silver aluminum paste on the front side of the silicon wafer, optimize the width and number of the back gate lines to 220 gate lines and 16.5 μm line width, and perform light injection treatment after drying and sintering.

[0125] Comparative Example 2

[0126] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 140nm, the number of gate lines is 220, and the gate line width is 16.5, which are respectively limited differently.

[0127] Comparative Example 3

[0128] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 130nm, the number of gate lines is 220, and the gate line width is 16.5, which are different restrictions.

[0129] Comparative Example 4

[0130] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm, the number of gate lines is 220, and the gate line width is 16.5, which are different restrictions.

[0131] Comparative Example 5

[0132] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 110nm, the number of gate lines is 220, and the gate line width is 16.5, which are respectively limited differently.

[0133] Comparative Example 6

[0134] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 145nm, the number of gate lines is 220, and the gate line width is 16.5, which are different restrictions.

[0135] Comparative Example 7

[0136] The difference from Example 1 is that the size of the tower base is 9.5 μm, the doped polysilicon layer is a single layer with a thickness of 145 nm, the number of gate lines is 220, and the gate line width is 16.5, which makes different restrictions.

[0137] Comparative Example 8

[0138] What is different from Example 1 is that the size of the tower base is 7.5 μm, the doped polysilicon layer is a single layer with a thickness of 130 nm, the number of gate lines is 164, and the gate line width is 12.5, which are different limitations.

[0139] Comparative Example 9

[0140] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 140nm, the number of gate lines is 220, and the gate line width is 16.5, which are respectively limited differently.

[0141] Comparative Example 10

[0142] What is different from Example 1 is that the size of the tower base is 8.1μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 140nm, the number of gate lines is 220, and the gate line width is 16.5, which are respectively limited differently.

[0143] Comparative Example 11

[0144] What is different from Example 1 is that the size of the tower base is 7.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 140nm, the number of gate lines is 220, and the gate line width is 16.5, which are respectively limited differently.

[0145] Comparative Example 12

[0146] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm, the number of gate lines is 220, and the gate line width is 16.5, which are different restrictions.

[0147] Comparative Example 13

[0148] What is different from Example 1 is that the size of the tower base is 7.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm, the number of gate lines is 220, and the gate line width is 16.5, which are respectively limited differently.

[0149] Comparative Example 14

[0150] What is different from Example 1 is that the size of the tower base is 7.1μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm, the number of gate lines is 220, and the gate line width is 16.5, which are respectively limited differently.

[0151] Comparative Example 15

[0152] What is different from Example 1 is that the size of the tower base is 7.1μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 120nm, the number of gate lines is 164, and the gate line width is 16.5, which are respectively limited differently.

[0153] Comparative Example 16

[0154] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 145nm, the number of gate lines is 164, and the gate line width is 16.5, which are respectively limited differently.

[0155] Comparative Example 17

[0156] What is different from Example 1 is that the size of the tower base is 9.5μm, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 145nm, the number of gate lines is 164, and the gate line width is 12.5, which are respectively limited differently.

[0157] The N-type Topcon solar cells obtained in the above-mentioned comparative examples 1-16 were subjected to performance tests, and the results are as follows:

[0158] Table 2 Performance test results of N-type Topcon solar cells in each group of comparative examples

[0159]

[0160] Comparing Example 1 with Comparative Examples 1-5, the bifaciality of the cell gradually increases when the thickness of the polysilicon layer decreases, but the increase is very small. This is because the stacking process can differentiate the doping concentrations of the two adjacent layers of poly silicon through the blocking ability of the middle oxide layer, thereby achieving the vertical selectivity of the effects of different poly silicon. The high doping concentration of the poly silicon on the outside is mainly used for high contact ability, and the low doping concentration of the poly silicon on the inside can be superimposed to reduce the thickness of the first tunneling oxide layer, and finally reduce the inner layer recombination and reduce the inner expansion to enhance the tunneling effect. The above can maintain high contact and enhance filling, high tunneling and low recombination to enhance the opening voltage, and the thickening of poly silicon reduces the metal recombination to enhance the opening voltage, and finally improves the efficiency of the back of the battery.

[0161] Comparing Example 1 with Comparative Examples 6-8, where Comparative Example 6 is a multi-layer polysilicon layer and Comparative Example 7-8 is a single-layer polysilicon layer, only changing the number of polysilicon layers has little effect on the improvement of the bifaciality of the cell. Comparing Example 1 with Comparative Examples 9-11, as the size of the tower base increases, the bifaciality of the cell is improved, but only changing the size of the tower base has little effect on the improvement of the bifaciality of the cell; Comparing Example 1 with Comparative Examples 12-16, when reducing the thickness of the polysilicon layer or reducing the thickness of the polysilicon layer and the tower base or reducing the thickness of the Poly, the tower base and the number of gate lines, the number of gate lines The bifaciality of the corresponding battery cell increases when the number or the number of gate lines and the gate line width are increased. The increase in the bifaciality of the battery cell is very small and belongs to the conventional range. However, as in Examples 1-7, when the Poly thickness (100-130nm), the base size (7.5-8.5μm), the number of gate lines (154-174), and the gate line width (11.5-13.5μm) are simultaneously reduced, the bifaciality of the corresponding battery cell can reach 85.03%-85.67%, which has a larger range for improvement. Therefore, it is useful to improve the bifaciality when the above parameters are adjusted at the same time.

[0162] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A novel method for improving the bifaciality of Topcon solar cells, characterized in that: The steps include: Step 1, selecting an N-type silicon substrate and performing double-sided texturing to form a pyramid structure to obtain a textured silicon wafer; Step 2: Diffusing boron on the front side of the textured silicon wafer to form a P+ doped layer and a borosilicate glass layer; Step 3, removing the borosilicate glass layer on the front side of the silicon wafer after the boron diffusion in Step 2 and the doped layer on the back side and edge of the silicon wafer by alkali polishing; Step 4, using LPCVD equipment to form a first tunneling oxide layer on the surface of the silicon wafer substrate, and then depositing a first doped polysilicon layer, a second doped polysilicon layer and a third doped polysilicon layer on the surface of the first tunneling oxide layer using different deposition pressures; Step 5: low-pressure oxidation to form a silicon dioxide masking film, followed by phosphorus diffusion in stages, forming a PN junction on the back of the silicon wafer to obtain a preliminary cell; Step 6, removing the polysilicon on the front and edge of the primary cell; Step seven, printing silver-aluminum paste on the front side of the silicon wafer obtained in step six and printing silver paste on the back side, and performing light injection treatment after drying and sintering.

2. A novel Topcon solar cell bifaciality improvement method according to claim 1, characterized in that: In the step three, a tank-type alkali polishing machine is used, the polishing tank process time is 170 to 190 seconds, and the tower base size after alkali polishing is 7.5 to 8.5 μm.

3. A novel Topcon solar cell bifaciality improvement method according to claim 1, characterized in that: In the step four, LPCVD equipment is used, oxygen is introduced under normal pressure, and the reaction is carried out at a temperature of 600-620°C for 950-1200 seconds to form a tunneling oxide layer on the surface of the silicon substrate. Subsequently, the tunneling oxide layer surface is reacted at a pressure of 300-350 mtorr and a temperature of 590-640°C for 670-700 seconds to generate a first doped polysilicon layer.

4. A novel Topcon solar cell bifaciality improvement method according to claim 3, characterized in that: The thickness of the tunnel oxide layer is 1.5-2 nm, and the thickness of the first doped polysilicon layer is 20-40 nm.

5. A novel Topcon solar cell bifaciality improvement method according to claim 4, characterized in that: The reaction is carried out for 280 to 300 seconds under the conditions of a pressure of 200 to 250 mtorr and a temperature of 590 to 640° C., so as to form a second doped polysilicon layer on the first doped polysilicon layer.

6. A novel Topcon solar cell bifaciality improvement method according to claim 5, characterized in that: The reaction is carried out for 200 to 220 seconds under the conditions of a pressure of 100 to 150 mtorr and a temperature of 590 to 640° C., so as to form a third doped polysilicon layer on the second doped polysilicon layer.

7. A novel Topcon solar cell bifaciality improvement method according to claim 1, characterized in that: The total thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is 100-130 nm.

8. A novel Topcon solar cell bifaciality improvement method according to claim 1, characterized in that: In the step five, a low-pressure diffusion deposition device is used to oxidize and form a silicon dioxide masking film under the conditions of a pressure of 100 to 200 mtorr, an oxygen flow rate of 900 to 1200 sccm, and a reaction time of 200 to 300 seconds, and POCl3 is used for phosphorus diffusion. Low-temperature deposition is first performed at a deposition temperature of 750 to 830°C, and then the process is carried out in stages: first, the temperature is increased at a temperature of 860 to 930°C for 10 to 20 minutes, and then the temperature is reduced at 860 to 900°C for 10 to 20 minutes. Finally, a post-oxidation process is performed and the temperature is reduced to 720 to 750°C to complete the process, thereby forming a back PN junction.

9. A novel Topcon solar cell bifaciality improvement method according to claim 1, characterized in that: In the step seven, the width of the back gate lines is 11.5-13.5 μm, and the number of the back gate lines is 154-174.

10. A Topcon solar cell, characterized in that: The method is prepared by the method according to any one of claims 1 to 9, comprising a silicon wafer, wherein a P+ diffusion layer, an aluminum oxide passivation layer, a front anti-reflection layer and a front metal electrode are sequentially arranged on the front side of the silicon wafer, and a tunneling oxide layer, a first doped polysilicon layer, a second doped polysilicon layer, a third doped polysilicon layer, a back anti-reflection layer and a back metal electrode are sequentially arranged on the back side of the silicon wafer; The front metal electrode penetrates the front anti-reflection layer, the aluminum oxide passivation layer and the P+ diffusion layer to form an ohmic contact; the back metal electrode penetrates the back anti-reflection layer and the doped polysilicon layer to form an ohmic contact.

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