Light-emitting diode chip, preparation method thereof and LED

Abstract

The invention relates to the technical field of photoelectricity, in particular to a light-emitting diode chip, a preparation method thereof and an LED. In the preparation method of the light-emitting diode chip, second photoetching processing and second dry etching are carried out on an N-type semiconductor layer in a preset area; etching gases adopted in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset region is higher than that of the N-type semiconductor layer in the non-preset region, and preparing an N-type electrode on the N-type semiconductor layer in the preset region, in this way, better ohmic contact between the N-type electrode and the N-type semiconductor is achieved, the voltage of the chip is reduced, meanwhile, the overall Si doping concentration of the N-type semiconductor is not affected, the situation that the luminance of the chip is low due to the fact that the luminous efficiency of the epitaxial layer is low is avoided, and the luminance is not lost while voltage reduction is achieved.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technology, and in particular to a light emitting diode chip and a preparation method thereof, and an LED. Background Art

[0002] LED (Light Emitting Diode) is a semiconductor light-emitting device that can convert electrical energy into light energy. With the development and progress of LED chip manufacturing technology, it has gradually become a new mainstream lighting source after incandescent lamps and fluorescent lamps. It has the advantages of small size, fast response, long life, environmental protection and energy saving, and is widely used in lighting, display screens and other fields.

[0003] The LED chip is composed of an epitaxial layer and a chip layer. The epitaxial layer generally includes a substrate, an N-type semiconductor, a quantum well, and a P-type semiconductor; the chip layer is composed of a current blocking layer, a transparent conductive layer, an electrode, and a passivation layer from bottom to top. The electrodes are divided into P-type electrodes and N-type electrodes. The N-type electrode is located on the surface of the N-type semiconductor and is connected to the negative pole of the power supply to achieve electrical connection. Exposing the N-type semiconductor requires a chip process called Mesa. The principle is to etch the epitaxial layer to a certain depth through photolithography and dry etching, and etch away the P-type semiconductor, quantum well, and part of the N-type semiconductor, thereby exposing the N-type semiconductor that needs to be electrically connected.

[0004] In the traditional Mesa process, the exposed N-type semiconductor has the same Si doping concentration as the N-type semiconductor in other locations, which is the concentration of the N-type semiconductor itself in the epitaxial layer. If the chip voltage is reduced in order to make the N-type electrode have better ohmic contact with the N-type semiconductor, the Si concentration of the N-type semiconductor in the epitaxial layer can be increased, but this will lead to low luminous efficiency of the epitaxial layer and thus low brightness of the chip, so there is no way to reduce the voltage without losing brightness. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a light emitting diode chip and a preparation method thereof, which can reduce the chip voltage without affecting the brightness of the chip.

[0006] The technical problem to be solved by the present invention is also to provide an LED.

[0007] In order to solve the above technical problems, the present invention provides a method for preparing a light emitting diode chip, comprising the following steps:

[0008] Providing an epitaxial layer, the epitaxial layer comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer;

[0009] Performing a first photolithography process and a first dry etching on the epitaxial layer to expose a portion of the N-type semiconductor layer, wherein the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer of a first region, and an N-type electrode is disposed in the first region, wherein the first region includes a preset region and a non-preset region, and the preset region includes an orthographic projection region of the N-type electrode on the N-type semiconductor layer;

[0010] The N-type semiconductor layer in the preset area is subjected to a second photolithography process and a second dry etching process, wherein the etching gas used in the second dry etching process is SiCl 4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area;

[0011] Preparing an N-type electrode on the N-type semiconductor layer within the preset area, and making the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer within the preset area;

[0012] A P-type electrode is prepared on the P-type semiconductor layer.

[0013] In some embodiments, the preset area is an area formed by extending the edge of the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer outward by 0.5 μm to 2 μm.

[0014] In some embodiments, the Si doping concentration of the N-type semiconductor layer in the predetermined area is 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 ;

[0015] The Si doping concentration of the N-type semiconductor layer in the non-preset area is 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 .

[0016] In some embodiments, the etching gas used in the first dry etching is Cl 2 Gas, BCl 3 gas, Ar gas or one or more thereof.

[0017] In some embodiments, the process parameters of the first dry etching include: 2 The gas flow rate is 10 sccm to 250 sccm;

[0018] The BCl 3 The gas flow rate is 10 sccm to 250 sccm;

[0019] The flow rate of the Ar gas is 10 sccm to 250 sccm.

[0020] In some embodiments, the process parameters of the first dry etching further include: a pressure of 3mT to 5mT;

[0021] The upper electrode loading power is 300W~500W;

[0022] The lower electrode loading power is 100W~300W.

[0023] In some embodiments, the process parameters of the second dry etching include: 4 The gas flow rate is 10 sccm to 60 sccm;

[0024] The flow rate of the Ar gas is 5 sccm to 15 sccm.

[0025] In some embodiments, the process parameters of the second dry etching further include: a pressure of 3mT to 5mT;

[0026] The upper electrode loading power is 300W~500W;

[0027] The lower electrode loading power is 100W~300W.

[0028] Correspondingly, the present invention further provides a light emitting diode chip, the light emitting diode chip is manufactured by the light emitting diode chip manufacturing method as described above, and an LED, the LED comprising the light emitting diode chip.

[0029] The implementation of the present invention has the following beneficial effects:

[0030] In the method for preparing a light-emitting diode chip provided by the present invention, the N-type semiconductor layer in the preset area is subjected to a second photolithography process and a second dry etching process, and the etching gas used in the second dry etching process is SiCl 4 Gas and Ar gas are used to make the Si doping concentration of the N-type semiconductor layer in the preset area higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area, and an N-type electrode is prepared on the N-type semiconductor layer in the preset area, thereby achieving better ohmic contact between the N-type electrode and the N-type semiconductor, reducing the chip voltage without affecting the overall Si doping concentration of the N-type semiconductor, avoiding the low luminous efficiency of the epitaxial layer and thus the low brightness of the chip, and achieving voltage reduction without losing luminous brightness. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A schematic diagram of a semi-finished product in the process of performing a first photolithography process and a first dry etching process on the epitaxial layer in the method for preparing a light-emitting diode chip provided by the present invention;

[0032] Figure 2 A schematic diagram of a preset area in the method for preparing a light emitting diode chip provided by the present invention;

[0033] Figure 3 It is a schematic diagram of a semi-finished product in the process of performing a second photolithography process and a second dry etching on the epitaxial layer in the method for preparing a light emitting diode chip provided by the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0035] In the description of the present invention, it is necessary to understand that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0037] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0039] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0040] In the present invention, "preferred" and "better" are only used to describe implementation methods or embodiments with better effects, and it should be understood that they do not constitute a limitation on the scope of protection of the present invention. In the present invention, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features. In the present invention, when involving numerical ranges, unless otherwise specified, the two endpoints of the numerical range are included.

[0041] To solve the above problems, the present invention provides a method for preparing a light emitting diode chip, comprising the following steps:

[0042] (1) Providing an epitaxial layer, wherein the epitaxial layer includes a substrate, an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer;

[0043] (2) performing a first photolithography process and a first dry etching on the epitaxial layer to expose a portion of the N-type semiconductor layer, wherein the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer of a first region, and an N-type electrode is disposed in the first region, wherein the first region includes a preset region and a non-preset region, and the preset region includes an orthographic projection region of the N-type electrode on the N-type semiconductor layer;

[0044] like Figure 1As shown, the epitaxial layer is subjected to a first photolithography process and a first dry etching process to expose a portion of the N-type semiconductor layer, where the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer of the first region 100 . The blank area in the figure is the first region 100 , and the shaded area is the photoresist mask area.

[0045] In actual production, not all of the exposed N-type semiconductor layer in the first region 100 is used to prepare the N-type electrode. Some of the exposed N-type semiconductor layer in the first region 100 is not used to prepare the N-type electrode. 4 Gas etching will cause the Si doping concentration of the N-type semiconductor layer to be too high, which will affect the low luminous efficiency of the epitaxial layer and thus reduce the brightness of the chip. 4 Gas etching.

[0046] like Figure 2 As shown, in some embodiments, the preset area 110 is an area formed by the edge of the orthographic projection area of ​​the N-type electrode 120 on the N-type semiconductor layer extending outward by 0.5μm to 2μm; preferably, the preset area 110 is an area formed by the edge of the orthographic projection area of ​​the N-type electrode 120 on the N-type semiconductor layer extending outward by 1μm to 1.5μm. When the area of ​​the preset area 110 is smaller than the area of ​​the N-type electrode 120, it will cause a voltage increase. The area of ​​the preset area 110 is larger than the area of ​​the N-type electrode 120, so that the Si doping concentration of the N-type semiconductor layer in the preset area 110 can be ensured to be higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area 130, thereby ensuring a voltage reduction.

[0047] In some embodiments, the etching gas used in the first dry etching is Cl 2 Gas, BCl 3 The first dry etching process uses the above etching gas without affecting the Si doping concentration of the N-type semiconductor layer. In some embodiments, the first dry etching process uses Cl 2 When the Cl 2 The gas flow rate is 10 sccm to 250 sccm; the etching gas for the first dry etching is BCl 3 When the gas is 3 The flow rate of the gas is 10 sccm to 250 sccm; when Ar gas is selected as the etching gas for the first dry etching, the flow rate of the Ar gas is 10 sccm to 250 sccm.

[0048] Preferably, the etching gas used in the first dry etching is Cl 2gas and Ar gas, the Cl 2 The gas flow rate is 100 sccm to 200 sccm, and the Ar gas flow rate is 10 sccm to 30 sccm. This can increase the etching rate and achieve precise etching.

[0049] The process parameters of the first dry etching also include: pressure of 3mT to 5mT; upper electrode loading power of 300W to 500W; lower electrode loading power of 100W to 300W. Preferably, the pressure is 3.5mT to 4.5mT; upper electrode loading power of 350W to 450W; lower electrode loading power of 150W to 250W.

[0050] (3) performing a second photolithography process and a second dry etching on the N-type semiconductor layer in the preset area, wherein the etching gas used in the second dry etching is SiCl 4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area;

[0051] like Figure 3 As shown, the N-type semiconductor layer in the preset area is subjected to a second photolithography process and a second dry etching, wherein the blank area in the figure is the preset area 110 and the shaded area is the photoresist mask area.

[0052] The etching gas used in the second dry etching of the present invention is SiCl 4 gas and Ar gas, using SiCl 4 Gas etching will increase the Si doping concentration of the N-type semiconductor layer in the preset area, thereby achieving that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area, and an N-type electrode is prepared on the N-type semiconductor layer in the preset area, thereby achieving better ohmic contact between the N-type electrode and the N-type semiconductor, reducing the chip voltage without affecting the overall Si doping concentration of the N-type semiconductor, avoiding the low luminous efficiency of the epitaxial layer and thus the low brightness of the chip, and achieving voltage reduction without losing luminous brightness.

[0053] In some embodiments, the Si doping concentration of the N-type semiconductor layer in the predetermined area is 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 The Si doping concentration of the N-type semiconductor layer in the non-preset area is 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3.

[0054] In some embodiments, the process parameters of the second dry etching include: 4 The flow rate of the gas is 10 sccm to 60 sccm; the flow rate of the Ar gas is 5 sccm to 15 sccm. Preferably, the SiCl 4 The flow rate of the gas is 20 sccm to 50 sccm; the flow rate of the Ar gas is 7 sccm to 13 sccm.

[0055] In some embodiments, the process parameters of the second dry etching further include: pressure of 3mT to 5mT; upper electrode loading power of 300W to 500W; lower electrode loading power of 100W to 300W. Preferably, the pressure is 3.5mT to 4.5mT; upper electrode loading power of 350W to 450W; lower electrode loading power of 150W to 250W.

[0056] (4) preparing an N-type electrode on the N-type semiconductor layer within the preset area, and making the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer within the preset area;

[0057] (5) Preparing a P-type electrode on the P-type semiconductor layer.

[0058] Accordingly, the present invention also provides an LED chip, i.e., a light-emitting diode chip, which is the core part of the LED and determines the key characteristics of the LED, such as the luminous efficiency, wavelength, and chromaticity. Therefore, in the development of the LED industry, improving the quality and processing accuracy of the light-emitting diode chip and optimizing the chip manufacturing process are of great significance for improving the performance and application range of the LED. In addition, the present invention also provides an LED device, which includes the light-emitting diode chip.

[0059] The present invention is further described below with specific embodiments:

[0060] Example 1

[0061] This embodiment provides a method for preparing a light emitting diode chip, comprising the following steps:

[0062] Providing an epitaxial layer, the epitaxial layer comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer;

[0063] Performing a first photolithography process and a first dry etching on the epitaxial layer to expose a portion of the N-type semiconductor layer, wherein the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer of a first region, and an N-type electrode is disposed in the first region, wherein the first region includes a preset region and a non-preset region, and the preset region includes an orthographic projection region of the N-type electrode on the N-type semiconductor layer;

[0064] The N-type semiconductor layer in the preset area is subjected to a second photolithography process and a second dry etching process, wherein the etching gas used in the second dry etching process is SiCl 4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area;

[0065] Preparing an N-type electrode on the N-type semiconductor layer within the preset area, and making the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer within the preset area;

[0066] A P-type electrode is prepared on the P-type semiconductor layer.

[0067] The preset area is an area formed by extending 1 μm outward from the edge of the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer.

[0068] The process parameters used in the first dry etching are as follows:

[0069] parameter Pressure (mT) 4 Upper electrode loading power (W) 400 Lower electrode loading power (W) 200 Ar(sccm) 20 <![CDATA[Cl 2 (sccm)]]> 150

[0070] The process parameters used in the second dry etching are as follows:

[0071] parameter Pressure (mT) 4 Upper electrode loading power (W) 400 Lower electrode loading power (W) 200 Ar(sccm) 10 <![CDATA[SiCl 4 (sccm)]]> 40

[0072] Comparative Example 1

[0073] This comparative example provides a method for preparing a light emitting diode chip, comprising the following steps:

[0074] Providing an epitaxial layer, the epitaxial layer comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer;

[0075] The epitaxial layer is subjected to a first photolithography process and a first dry etching process to expose a portion of the N-type semiconductor layer, an N-type electrode is prepared on the exposed portion of the N-type semiconductor layer, and a P-type electrode is prepared on the P-type semiconductor layer.

[0076] The light emitting diode chips prepared in Example 1 and Comparative Example 1 were tested, and the specific test results are shown in Table 1.

[0077] Table 1 Performance test results of photodiode chips prepared in Example 1 and Comparative Example 1

[0078] Test current / mA Voltage / V Brightness / mW Wavelength / nm Comparative Example 1 120 3.08 186.2 453.5 Example 1 120 3.04 186.2 453.5

[0079] From the above data, it can be seen that the brightness of Example 1 is comparable to that of Comparative Example 1, but the voltage is 0.04V lower, which is rare for a light-emitting diode chip. Therefore, in the method for preparing a light-emitting diode chip provided by the present invention, the N-type semiconductor layer in the preset area is subjected to a second photolithography process and a second dry etching, and the etching gas used in the second dry etching is SiCl 4 Gas and Ar gas are used to make the Si doping concentration of the N-type semiconductor layer in the preset area higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area, and an N-type electrode is prepared on the N-type semiconductor layer in the preset area, thereby achieving better ohmic contact between the N-type electrode and the N-type semiconductor, reducing the chip voltage without affecting the overall Si doping concentration of the N-type semiconductor, avoiding the low luminous efficiency of the epitaxial layer and thus the low brightness of the chip, and achieving voltage reduction without losing luminous brightness.

[0080] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0081] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A method for preparing a light emitting diode chip, characterized in that: The following steps are involved: Providing an epitaxial layer, the epitaxial layer comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer; Performing a first photolithography process and a first dry etching on the epitaxial layer to expose a portion of the N-type semiconductor layer, wherein the exposed portion of the N-type semiconductor layer is the N-type semiconductor layer of a first region, and an N-type electrode is disposed in the first region, wherein the first region includes a preset region and a non-preset region, and the preset region includes an orthographic projection region of the N-type electrode on the N-type semiconductor layer; Performing a second photolithography process and a second dry etching on the N-type semiconductor layer in the preset area, wherein the etching gases used in the second dry etching are SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the preset area is higher than the Si doping concentration of the N-type semiconductor layer in the non-preset area; Preparing an N-type electrode on the N-type semiconductor layer within the preset area, and making the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer within the preset area; A P-type electrode is prepared on the P-type semiconductor layer.

2. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The preset area is an area formed by extending the edge of the orthographic projection area of ​​the N-type electrode on the N-type semiconductor layer outward by 0.5 μm to 2 μm.

3. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The Si doping concentration of the N-type semiconductor layer in the preset area is 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 ; The Si doping concentration of the N-type semiconductor layer in the non-preset area is 1×10 18 atoms / cm 3 ~1×10 19 atoms / cm 3 .

4. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The etching gas used in the first dry etching is selected from one or more of Cl2 gas, BCl3 gas, and Ar gas.

5. The method for preparing a light emitting diode chip according to claim 4, characterized in that: The process parameters of the first dry etching include: the flow rate of the Cl2 gas is 10 sccm to 250 sccm; The flow rate of the BCl3 gas is 10 sccm to 250 sccm; The flow rate of the Ar gas is 10 sccm to 250 sccm.

6. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The process parameters of the first dry etching also include: a pressure of 3mT to 5mT; The upper electrode loading power is 300W~500W; The lower electrode loading power is 100W~300W.

7. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The process parameters of the second dry etching include: the flow rate of the SiCl4 gas is 10 sccm to 60 sccm; The flow rate of the Ar gas is 5 sccm to 15 sccm.

8. The method for preparing a light emitting diode chip according to claim 1, characterized in that: The process parameters of the second dry etching also include: a pressure of 3mT to 5mT; The upper electrode loading power is 300W~500W; The lower electrode loading power is 100W~300W.

9. A light emitting diode chip, characterized in that: The light emitting diode chip is manufactured by the method for manufacturing a light emitting diode chip according to any one of claims 1 to 8.

10. An LED, characterized in that: The LED comprises the light emitting diode chip as claimed in claim 9.

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