Light-emitting chip epitaxial layer and light-emitting chip

Abstract

The invention relates to a light-emitting chip epitaxial layer and a light-emitting chip. The light-emitting chip epitaxial layer comprises an N-type layer, an active layer and a P-type layer which grow in sequence, the N-type layer comprises a first sub-layer and a current conducting layer, the first sub-layer is arranged on one surface, far away from the active layer, of the current conducting layer, and the first sub-layer at least comprises a plurality of first doping layers; si is doped in the current conducting layer and the first doping layer, the concentration of the doped Si in the current conducting layer is larger than or equal to the concentration of the doped Si in the first doping layer close to the current conducting layer, and in any two adjacent first doping layers, the concentration of the doped Si in the first doping layer close to the current conducting layer is larger than or equal to the concentration of the doped Si in the second doping layer close to the current conducting layer. The concentration of doped Si in the first doping layer far away from the current conducting layer is greater than that of doped Si. Point defects caused by Si doping can be effectively reduced, the crystallization quality of the current conducting layer is improved, and the quality of the light-emitting chip is improved.

Description

Technical Field

[0001] The present application relates to the technical field of LED chips, and in particular to a light-emitting chip epitaxial layer and a light-emitting chip. Background Art

[0002] LED light-emitting diodes are electronic components that convert electrical energy directly into light energy. Compared with traditional ones, they have the advantages of high efficiency, energy saving, environmental protection and long life. They play an important role in energy conservation and emission reduction and green development, and are now widely used in displays and lighting. The light-emitting chip is the light source part of the light-emitting diode. The light-emitting effect of the light-emitting chip will be affected by the quality of the epitaxial layer. At present, the epitaxial layer of the light-emitting chip is usually a nitride semiconductor layer grown on a substrate. The nitride semiconductor layer has a large number of defects due to the lattice mismatch problem, which reduces the quality of the epitaxial layer of the light-emitting chip and affects the quality of the light-emitting chip.

[0003] Therefore, how to improve the quality of the epitaxial layer of the light-emitting chip is an urgent problem to be solved. Summary of the invention

[0004] In view of the deficiencies of the above-mentioned related technologies, the purpose of the present application is to provide a light-emitting chip epitaxial layer and a light-emitting chip, aiming to solve the technical problems of a large number of defects in the epitaxial layer of the light-emitting chip and low quality of the epitaxial layer.

[0005] A light-emitting chip epitaxial layer, comprising:

[0006] The N-type layer, active layer and P-type layer are grown sequentially;

[0007] The N-type layer includes a first sublayer and a current conduction layer, the first sublayer is arranged on a side of the current conduction layer away from the active layer, and the first sublayer includes at least a plurality of first doped layers; Si is doped in the current conduction layer and the first doped layer, the concentration of Si doped in the current conduction layer is greater than or equal to the concentration of Si doped in the first doped layer close to the current conduction layer, and in any two adjacent first doped layers, the concentration of Si doped in the first doped layer close to the current conduction layer is greater than the concentration of Si doped in the first doped layer away from the current conduction layer.

[0008] The N-type layer of the epitaxial layer of the above-mentioned light-emitting chip includes a first sublayer and a current conduction layer. The current conduction layer is doped with Si, which can reduce the resistance value of the current conduction layer and improve the current conduction effect. The first sublayer includes multiple first doped layers, and the concentration of doped Si between each first doped layer gradually changes; and the closer the first doped layer is to the current conduction layer, the higher the concentration of doped Si. This is more conducive to the growth of the current conduction layer, effectively reducing the point defects introduced by Si doping, improving the crystallization quality of the current conduction layer, and the current conduction effect of the N-type layer is better, which ensures the quality of the epitaxial layer of the light-emitting chip and improves the quality of the light-emitting chip.

[0009] Optionally, the first sublayer further includes a plurality of first non-doped layers, and the first doped layers and the first non-doped layers are alternately stacked in sequence. The first doped layer is doped with Si, which can reduce the resistance value of the first doped layer. The first non-doped layer is not doped with Si, and the resistance of the first non-doped layer is relatively high. During the current transmission process, the first sublayer with high and low resistances staggeredly arranged has enhanced lateral expansion ability of electrons, which expands the current distribution area of ​​the N-type layer flowing into the active layer, and effectively reduces the current crowding phenomenon.

[0010] Optionally, the N-type layer further includes a second sublayer disposed between the current conducting layer and the active layer, the second sublayer at least including a plurality of second doped Si layers; the concentration of Si doped in the current conducting layer is greater than or equal to the concentration of Si doped in the second doped layer close to the current conducting layer, and in any two adjacent second doped layers, the concentration of Si doped in the second doped layer close to the active layer is less than the concentration of Si doped in the second doped layer far from the active layer. The second sublayer includes a plurality of second doped layers, the concentration of Si doped between each second doped layer gradually changes; and the closer the second doped layer is to the active layer, the lower the concentration of Si doped therein. This is more conducive to the growth of the active layer, so that the active layer has a lower defect density and high crystal quality.

[0011] Based on the same inventive concept, the present application also provides a light-emitting chip, including a positive electrode, a negative electrode, and the light-emitting chip epitaxial layer as described above, wherein the negative electrode is electrically connected to the N-type layer, and the positive electrode is electrically connected to the P-type layer.

[0012] The epitaxial layer of the above-mentioned light-emitting chip includes a first sublayer and a current conduction layer. The current conduction layer is doped with Si, which can reduce the resistance value of the current conduction layer and improve the current conduction effect. The first sublayer includes multiple first doped layers, and the concentration of doped Si between each first doped layer gradually changes; and the closer the first doped layer is to the current conduction layer, the higher the concentration of doped Si. This is more conducive to the growth of the current conduction layer, effectively reducing the point defects introduced by Si doping, improving the crystallization quality of the current conduction layer, and the current conduction effect of the N-type layer is better, which ensures the quality of the epitaxial layer of the light-emitting chip and improves the quality of the light-emitting chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the structure of an epitaxial layer of a light-emitting chip provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of the structure of the N-type layer provided in the embodiment of the present application including a first sub-layer and a current conducting layer;

[0015] Figure 3 A schematic diagram of a structure in which the first sub-layer provided in an embodiment of the present application includes a first doped layer and a first undoped layer;

[0016] Figure 4 A schematic diagram of a current conduction layer in which the concentration of Si doped in the current conduction layer provided in an embodiment of the present application is constant;

[0017] Figure 5 A schematic diagram showing that the concentration of Si doped between adjacent first doped layers provided in an embodiment of the present application increases in a gradient;

[0018] Figure 6 Another structural schematic diagram of a light-emitting chip epitaxial layer provided in another optional embodiment of the present application;

[0019] Figure 7 A schematic structural diagram of a second sub-layer including a second doped layer and a second non-doped layer provided in another optional embodiment of the present application;

[0020] Figure 8 A schematic diagram showing that the concentration of doped Si between adjacent second doped layers decreases in a gradient manner, provided in another optional embodiment of the present application;

[0021] Description of reference numerals:

[0022] 1-N-type layer; 101-first sublayer; 102-current conducting layer; 103-first doped layer; 104-first undoped layer; 105-second sublayer; 106-second doped layer; 107-second undoped layer; 2-active layer; 3-P-type layer. DETAILED DESCRIPTION

[0023] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0025] The light-emitting effect of the light-emitting chip will be affected by the quality of the epitaxial layer. The epitaxial layer of the light-emitting chip is usually a nitride semiconductor layer grown on a substrate. The nitride semiconductor layer has a large number of defects due to lattice mismatch problems, which reduces the quality of the epitaxial layer of the light-emitting chip and affects the quality of the light-emitting chip.

[0026] Based on this, the present application hopes to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in the subsequent embodiments.

[0027] The present embodiment provides an epitaxial layer of a light-emitting chip. The light-emitting chip in the present embodiment includes but is not limited to at least one of a high-brightness LED light-emitting chip, a Mini LED (Mini Light Emitting Diode), a Micro LED (Micro Light Emitting Diode), and a nanometer-level light-emitting diode. The light-emitting chip in the present embodiment can be a front-mounted LED chip or a flip-chip LED chip. The light-emitting chip in the present embodiment can be a red light LED chip that emits red light. Of course, it can also be set to an LED chip that emits light of other colors according to needs, which will not be described one by one here.

[0028] like Figure 1 As shown, the epitaxial layer of the light-emitting chip includes an N-type layer 1, an active layer 2, and a P-type layer 3 grown in sequence. It can be understood that the material of the N-type layer 1 in this embodiment may include at least one of GaN, InGaN, AlGaN, and AlInGaN; the active layer 2 in this embodiment may include a quantum well layer, or may include other structures; this embodiment does not impose any specific restrictions on the P-type layer 3, as long as the light-emitting chip can emit light.

[0029] like Figure 2 , Figure 3As shown, the N-type layer 1 in this embodiment includes a first sublayer 101 and a current conducting layer 102. The first sublayer 101 is disposed on a side of the current conducting layer 102 away from the active layer 2. The first sublayer 101 includes at least a plurality of first doped layers 103. The current conducting layer 102 and the first doped layer 103 are doped with Si. Doping with Si can reduce the resistance value. In some embodiments, Figure 4 As shown, the concentration of doped Si in the current conducting layer 102 can be a constant concentration. The current conducting layer 102 maintains a relatively high constant concentration, and the current conducting layer 102 can have a good conduction effect, which is also conducive to the growth of the current conducting layer 102. In this embodiment, the thickness of the first sublayer 101 and the current conducting layer 102 can be selected as needed. For example, the overall thickness of the first sublayer 101 can be 500-800nm, and the overall thickness of the current conducting layer 102 can be 800-1200nm.

[0030] The concentration of Si doped in the current conducting layer 102 of this embodiment is greater than or equal to the concentration of Si doped in the first doped layer 103 close to the current conducting layer 102. It can be understood that the first doped layer 103 close to the current conducting layer 102 is the first doped layer 103 in the first sublayer 101 that is adjacent to the current conducting layer 102. In this embodiment, in any two adjacent first doped layers 103, the concentration of Si doped in the first doped layer 103 close to the current conducting layer 102 is greater than the concentration of Si doped in the first doped layer 103 far from the current conducting layer 102. For example, the concentration of Si doped in the current conducting layer 102 is greater than 1×10 19 cm 3 The concentration range of Si doping in the first doping layer 103 is 1×10 18 cm 3 ~1×10 19 cm 3 , the concentration of Si doped in the first doping layer 103 closer to the current conducting layer 102 is closer to 1×10 19 cm 3 The concentration of Si doped in the second doping layer 106 which is farther away from the current conducting layer 102 is closer to 1×10 18 cm 3 .

[0031] In some embodiments, the concentration of Si doped in each first doping layer 103 in the first sublayer 101 is a constant concentration. That is, the first first doping layer 103 is grown while maintaining the concentration m of Si doping, and the m value is constant; the adjacent second first doping layer 103 is grown while maintaining the concentration n of Si doping, and the n value is constant; if the second first doping layer 103 is closer to the current conducting layer 102, then n is greater than m. Figure 5As shown, the concentration of doped Si in each first doped layer 103 thus grown shows a trend of increasing gradually in the direction close to the current conducting layer 102. In other embodiments, the concentration of doped Si in each first doped layer 103 in the first sublayer 101 is a gradient concentration. That is, the first first doped layer 103 grows while maintaining the concentration m of doped Si, and the m value changes gradually; the adjacent second first doped layer 103 grows while maintaining the concentration n of doped Si, and the n value changes gradually; if the second first doped layer 103 is closer to the current conducting layer 102, the minimum value of n is greater than the maximum value of m, and at the same time, the closer the first doped layer 103 is to the current conducting layer 102, the greater the m value and n value are.

[0032] In this embodiment, the first sublayer 101 may only include a plurality of stacked first doping layers 103. The closer the first doping layer 103 is to the current conducting layer 102, the higher the concentration of Si doping is. This is beneficial to the growth of the current conducting layer 102, can reduce point defects introduced by Si doping, and improve the crystal quality of the current conducting layer 102. In some embodiments, such as Figure 3 As shown, the first sublayer 101 may also include a plurality of first non-doped layers 104, and the first doped layers 103 and the first non-doped layers 104 are alternately stacked in sequence. The first doped layer 103 is doped with Si, which can reduce the resistance value of the first doped layer 103. The first non-doped layer 104 is not doped with Si, and the resistance value of the first non-doped layer 104 is relatively high. In the process of current transmission, the first sublayer 101 with high and low resistances staggeredly arranged has enhanced lateral expansion ability of electrons, expanded current distribution area of ​​the N-type layer 1 flowing into the active layer 2, and effectively reduced current crowding. In this embodiment, the current conducting layer 102 is in contact with the first doped layer 103 on one side close to the first sublayer 101, and the current conducting layer 102 is in direct contact with the first doped layer 103, which is conducive to the growth of the current conducting layer 102 and improves the crystal quality. In this embodiment, the thickness of the first doped layer 103 and the first non-doped layer 104 can be selected as needed. For example, the thickness of the first doped layer 103 can be 8-12 nm, and the thickness of the first non-doped layer 104 can be 3-5 nm.

[0033] In some embodiments, the epitaxial layer of the light-emitting chip may also include an intrinsic undoped semiconductor layer, such as a uGaN layer, which may be used as a buffer layer to reduce the lattice mismatch problem. Then, an N-type layer 1, an active layer 2, and a P-type layer 3 are sequentially grown on the intrinsic undoped semiconductor layer.

[0034] The N-type layer 1 of the epitaxial layer of the above-mentioned light-emitting chip includes a first sublayer 101 and a current conduction layer 102. The current conduction layer 102 is doped with Si, which can reduce the resistance value of the current conduction layer 102 and improve the current conduction effect. The first sublayer 101 includes multiple first doped layers 103, and the concentration of doped Si between each first doped layer 103 gradually changes; and the closer the first doped layer 103 is to the current conduction layer 102, the higher the concentration of doped Si. This is more conducive to the growth of the current conduction layer 102, effectively reducing the point defects introduced by Si doping, improving the crystal quality of the current conduction layer 102, and the current conduction effect of the N-type layer 1 is better, ensuring the quality of the epitaxial layer of the light-emitting chip and improving the quality of the light-emitting chip. When the first sublayer 101 includes multiple first non-doped layers 104, the first sublayer 101 has a stronger ability to expand electrons laterally during current transport, which expands the current distribution area of ​​the N-type layer 1 flowing into the active layer 2, and can effectively reduce the current crowding phenomenon.

[0035] Another optional embodiment of the present application:

[0036] This embodiment provides a light-emitting chip epitaxial layer. The remaining configurations of the light-emitting chip epitaxial layer are the same as those of the previous embodiment. The difference between the light-emitting chip epitaxial layer and the previous embodiment is that:

[0037] like Figure 6 , Figure 7 As shown, the N-type layer 1 in this embodiment further includes a second sublayer 105 disposed between the current conducting layer 102 and the active layer 2. The second sublayer 105 includes at least a plurality of second doped layers 106 doped with Si. The concentration of doped Si in the current conducting layer 102 is greater than or equal to the concentration of doped Si in the second doped layer 106 close to the current conducting layer 102. It can be understood that the second doped layer 106 close to the current conducting layer 102 is the second doped layer 106 disposed adjacent to the current conducting layer 102 in the first sublayer 101. And in any two adjacent second doped layers 106, the concentration of doped Si in the second doped layer 106 close to the active layer 2 is less than the concentration of doped Si in the second doped layer 106 away from the active layer 2. For example, the concentration range of doped Si in the second doped layer 106 is 1×10 18 cm 3 ~1×10 19 cm 3 The closer the second doping layer 106 is to the active layer 2, the closer the concentration of Si doping is to 1×10 18 cm 3 The concentration of Si doped in the second doping layer 106 closer to the current conducting layer 102 is closer to 1×10 19 cm 3The specific concentration of Si doped in the current conducting layer 102 and the first doping layer 103 in this embodiment is the same as that in the previous embodiment, and will not be described again.

[0038] In some embodiments, the concentration of Si doped in each second doping layer 106 in the second sublayer 105 is a constant concentration. That is, the first second doping layer 106 is grown while maintaining the concentration e of Si doping, and the value e is constant; the adjacent second second doping layer 106 is grown while maintaining the concentration f of Si doping, and the value f is constant; if the second second doping layer 106 is closer to the active layer 2, then f is less than e. Figure 8 As shown, the concentration of Si doped in each second doping layer 106 thus grown shows a trend of decreasing gradually toward the direction close to the active layer 2. In other embodiments, the concentration of Si doped in each second doping layer 106 in the second sublayer 105 is a gradient concentration. That is, the first second doping layer 106 grows while maintaining the concentration e value of Si doping, and the e value changes gradually; the adjacent second second doping layer 106 grows while maintaining the concentration f value of Si doping, and the f value changes gradually; if the second second doping layer 106 is closer to the active layer 2, the maximum value of f is less than the minimum value of e, and at the same time, the closer the e value and f value are to the active layer 2 in each second doping layer 106, the smaller the value.

[0039] In this embodiment, the second sublayer 105 may only include a plurality of stacked second doping layers 106. The closer the second doping layer 106 is to the active layer 2, the lower the concentration of Si doping is, which is more conducive to the growth of the active layer 2, so that the active layer 2 has a lower defect density and a high crystal quality. In some embodiments, Figure 7 As shown, the second sublayer 105 may also include a plurality of second non-doped layers 107, and the second doped layers 106 and the second non-doped layers 107 are alternately stacked in sequence. The second doped layer 106 is doped with Si, which can reduce the resistance value of the second doped layer 106. The second non-doped layer 107 is not doped with Si, and the resistance value of the second non-doped layer 107 is relatively high. In the process of current transmission, the second sublayer 105 with high and low resistances staggeredly arranged has enhanced lateral expansion ability of electrons, which can expand the current distribution area of ​​the N-type layer 1 flowing into the active layer 2, effectively reduce the current crowding phenomenon, and can also comprehensively reduce the formation of non-radiative recombination, thereby improving the luminous efficiency and antistatic performance of the light-emitting chip. In this embodiment, the thickness of the second sublayer 105, the second doped layer 106, and the second non-doped layer 107 can be selected as needed. For example, by way of example, the overall thickness of the second sublayer 105 is 300-500nm, the thickness of the second doped layer 106 is 8-12nm, and the thickness of the second non-doped layer 107 is 3-5nm.

[0040] The N-type layer 1 of the epitaxial layer of the light-emitting chip of this embodiment includes a first sublayer 101, a current conduction layer 102, and a second sublayer 105. The current conduction layer 102 is doped with Si, which can reduce the resistance value of the current conduction layer 102 and improve the current conduction effect. The first sublayer 101 includes a plurality of first doped layers 103, and the concentration of doped Si between each first doped layer 103 gradually changes; and the closer the first doped layer 103 is to the current conduction layer 102, the higher the concentration of doped Si. This is more conducive to the growth of the current conduction layer 102, effectively reducing the point defects introduced by Si doping, improving the crystal quality of the current conduction layer 102, and the current conduction effect of the N-type layer 1 is better, ensuring the quality of the epitaxial layer of the light-emitting chip and improving the quality of the light-emitting chip. And the second sublayer 105 includes a plurality of second doped layers 106, and the closer the second doped layer 106 is to the active layer 2, the lower the concentration of doped Si, which is more conducive to the growth of the active layer 2, so that the active layer 2 has a lower defect density and high crystal quality, and improves the luminous efficiency of the light-emitting chip.

[0041] Another optional embodiment of this embodiment:

[0042] This embodiment provides a light-emitting chip, including a positive electrode, a negative electrode, and the light-emitting chip epitaxial layer as described above, wherein the negative electrode is electrically connected to the N-type layer 1 , and the positive electrode is electrically connected to the P-type layer 3 .

[0043] The present embodiment does not specifically limit the material and shape of the positive electrode and the negative electrode. For example, the material of the electrode may include but is not limited to at least one of Cr, Ni, Al, Ti, Au, Pt, W, Pb, Rh, Sn, Cu, and Ag.

[0044] The epitaxial layer of the above-mentioned light-emitting chip includes a first sublayer 101 and a current conduction layer 102. The current conduction layer 102 is doped with Si, which can reduce the resistance value of the current conduction layer 102 and improve the current conduction effect. The first sublayer 101 includes a plurality of first doped layers 103, and the concentration of doped Si between each first doped layer 103 gradually changes; and the closer the first doped layer 103 is to the current conduction layer 102, the higher the concentration of doped Si. This is more conducive to the growth of the current conduction layer 102, effectively reduces the point defects introduced by Si doping, improves the crystal quality of the current conduction layer 102, and the current conduction effect of the N-type layer 1 is better, which ensures the quality of the epitaxial layer of the light-emitting chip and improves the quality of the light-emitting chip.

[0045] It should be understood that the application of the present application is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to this application.

Claims

1. A light-emitting chip epitaxial layer, characterized in that: include: The N-type layer, active layer and P-type layer are grown sequentially; The N-type layer includes a first sublayer and a current conduction layer, the first sublayer is arranged on a side of the current conduction layer away from the active layer, and the first sublayer includes at least a plurality of first doped layers; Si is doped in the current conduction layer and the first doped layer, the concentration of Si doped in the current conduction layer is greater than or equal to the concentration of Si doped in the first doped layer close to the current conduction layer, and in any two adjacent first doped layers, the concentration of Si doped in the first doped layer close to the current conduction layer is greater than the concentration of Si doped in the first doped layer away from the current conduction layer.

2. The light-emitting chip epitaxial layer according to claim 1, characterized in that: The first sublayer further includes a plurality of first non-doped layers, and the first doped layers and the first non-doped layers are alternately stacked in sequence.

3. The light-emitting chip epitaxial layer according to claim 2, characterized in that: A surface of the current conducting layer close to the first sub-layer contacts the first doping layer.

4. The light-emitting chip epitaxial layer according to any one of claims 1 to 3, characterized in that: The concentration of doped Si in the current conducting layer is constant.

5. The light-emitting chip epitaxial layer according to any one of claims 1 to 3, characterized in that: The concentration of Si doped in the current conducting layer is greater than 1×10 19 cm 3 The concentration of Si doped in the first doping layer is 1×10 18 cm 3 ~1×10 19 cm 3 .

6. The light-emitting chip epitaxial layer according to any one of claims 1 to 3, characterized in that: The N-type layer also includes a second sublayer arranged between the current conduction layer and the active layer, and the second sublayer includes at least a plurality of second doped layers doped with Si; the concentration of doped Si in the current conduction layer is greater than or equal to the concentration of doped Si in the second doped layer close to the current conduction layer, and in any two adjacent second doped layers, the concentration of doped Si in the second doped layer close to the active layer is less than the concentration of doped Si in the second doped layer away from the active layer.

7. The light-emitting chip epitaxial layer according to claim 6, characterized in that: The second sublayer further includes a plurality of second non-doped layers, and the second doped layers and the second non-doped layers are alternately stacked in sequence.

8. The light-emitting chip epitaxial layer according to claim 6, characterized in that: The concentration of Si doping in each of the first doping layers in the first sublayer is respectively constant; and the concentration of Si doping in each of the second doping layers in the second sublayer is respectively constant.

9. The light-emitting chip epitaxial layer according to claim 6, characterized in that: The concentration of Si doped in the second doping layer is 1×10 18 cm 3 ~1×10 19 cm 3 .

10. A light-emitting chip, characterized in that: It comprises a positive electrode, a negative electrode, and the light-emitting chip epitaxial layer as described in any one of claims 1 to 9, wherein the negative electrode is electrically connected to the N-type layer, and the positive electrode is electrically connected to the P-type layer.

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