Secure access method and device of cache memory and electronic equipment

Abstract

The invention provides a secure access method and device of a cache memory and electronic equipment, and relates to the technical field of cache memories. The secure access method for the cache memory comprises the following steps: in response to the condition that a function for accessing the cache memory provided by firmware is called, determining whether interrupt requests from various peripherals connected with a processor are shielded or not by utilizing an interrupt status bit of an interrupt controller of the processor; in response to the situation that the interrupt request of the processor is not shielded, shielding the interrupt requests from various peripherals by using an interrupt control bit of an interrupt controller; and in response to the function accessing the cache being returned, resuming interrupt requests from the various peripherals using an interrupt control bit of the interrupt controller. According to the invention, the cache memory can be accessed safely and efficiently.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed cache memory, and in particular to a method, device and electronic device for securely accessing a high-speed cache memory. Background Art

[0002] Cache technology is widely used in modern computer systems as an efficient temporary data storage solution to speed up data access, reduce latency and improve overall system performance. Cache is usually deployed in memory, and its access speed is significantly better than that of primary storage (such as hard disk), and can be implemented at different levels, such as CPU cache, memory cache and disk cache. By storing frequently accessed data, cache can effectively reduce the latency of data access, thereby improving system throughput and significantly reducing the frequency of I / O operations.

[0003] As processor performance continues to improve, cache, as a key component of the processor, has a significant impact on the stability and security of the entire system. However, the current processor cache management system still has many deficiencies in data security. For example, there are various problems such as data inconsistency, performance bottlenecks, increased system complexity, improper expiration policies, security vulnerabilities, and resource competition.

[0004] Therefore, how to access the cache memory safely and efficiently is a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention provides a method, device and electronic device for securely accessing a cache memory, so as to access the cache memory securely and efficiently.

[0006] The present invention provides a method for securely accessing a high-speed cache memory, comprising the following steps.

[0007] In response to the function of accessing the cache memory provided by the firmware being called, the interrupt status bit of the interrupt controller of the processor is used to determine whether the interrupt requests from various peripherals connected to the processor are blocked; wherein the processor includes at least one core, and the interrupt controller distributes the interrupt requests from the various peripherals to the corresponding cores; in response to the interrupt request of the processor not being blocked, the interrupt control bit of the interrupt controller is used to block the interrupt requests from the various peripherals; and in response to the function of accessing the cache memory being returned, the interrupt control bit of the interrupt controller is used to restore the interrupt requests from the various peripherals.

[0008] According to a method for securely accessing a cache memory provided by the present invention, an interrupt masking code is called at the entry of the function for accessing the cache memory; the interrupt status bit of the interrupt controller of the processor is used to determine whether the interrupt requests from various peripherals connected to the processor are masked, including: the interrupt masking code queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests from the various peripherals are masked; in response to the interrupt request of the processor not being masked, the interrupt control bit of the interrupt controller is used to mask the interrupt requests from the various peripherals, including: when the interrupt masking code determines that the interrupt requests from the various peripherals are not masked according to the query result, the interrupt control bit of the interrupt controller is set to mask the interrupt requests from the various peripherals.

[0009] According to a method for securely accessing a cache memory provided by the present invention, an interrupt recovery code is called at the return point of the function for accessing the cache memory; in response to the function for accessing the cache memory being returned, the interrupt control bit of the interrupt controller is used to recover the interrupt requests from the various peripheral devices, including: the interrupt recovery code sets the interrupt control bit of the interrupt controller to recover the interrupt requests from the various peripheral devices.

[0010] According to a method for securely accessing a cache memory provided by the present invention, the method further includes: setting a cache access flag stored in a preset position at the entry of the function for accessing the cache memory; using the interrupt status bit of the interrupt controller of the processor to determine whether interrupt requests from various peripherals connected to the processor are blocked, including: when the polling function running in the firmware finds that the cache access flag is set, querying the interrupt status bit of the interrupt controller to determine whether the interrupt requests from the various peripherals are blocked; in response to the interrupt request of the processor not being blocked, using the interrupt control bit of the interrupt controller to block the interrupt requests from the various peripherals, including: when the polling function determines that the interrupt request is not blocked, setting the interrupt control bit of the interrupt controller to block the interrupt requests from the various peripherals.

[0011] According to a method for securely accessing a cache memory provided by the present invention, the cache access flag is cleared at the return point of the function for accessing the cache memory; in response to the function for accessing the cache memory being returned, the interrupt control bit of the interrupt controller is used to restore the interrupt requests from the various peripheral devices, including: when the polling function finds that the cache access flag is cleared, the interrupt control bit of the interrupt controller is set to restore the interrupt requests from the various peripheral devices.

[0012] According to a method for securely accessing a cache memory provided by the present invention, the function for accessing the cache memory includes: an invalid function, a clean function and a flush function; the function for accessing the cache memory is called, including: any one of the invalid function, the clean function and the flush function is called.

[0013] The present invention also provides a secure access device for a cache memory, comprising the following modules: A determination module, for determining whether interrupt requests from various peripherals connected to the processor are masked by using the interrupt status bit of the interrupt controller of the processor in response to the function of accessing the cache memory provided by the firmware being called; wherein the processor includes at least one core, and the interrupt controller distributes the interrupt requests from the various peripherals to the corresponding cores; a masking module, for masking the interrupt requests from the various peripherals by using the interrupt control bit of the interrupt controller in response to the interrupt request of the processor not being masked; and a recovery module, for recovering the interrupt requests from the various peripherals by using the interrupt control bit of the interrupt controller in response to the function of accessing the cache memory being returned.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for securely accessing the cache memory as described above is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method for securely accessing a cache memory as described in any one of the above is implemented.

[0016] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned methods for securely accessing a cache memory.

[0017] The method, device and electronic device for securely accessing a cache memory provided by the present invention, when a function provided by the firmware for accessing the cache memory is called, use the interrupt status bit of the interrupt controller of the processor to determine whether the interrupt request from various peripherals connected to the processor is shielded; when the interrupt request of the processor is not shielded, use the interrupt control bit of the interrupt controller to shield the interrupt request from various peripherals; and when the function for accessing the cache memory is returned, use the interrupt control bit of the interrupt controller to restore the interrupt request from various peripherals. Since various problems caused by interrupt interference can be avoided in the process of accessing the cache memory, the cache memory can be accessed safely and efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 This is one of the flow charts of the method for securely accessing a cache memory provided by the present invention.

[0020] Figure 2 This is the second flow chart of the method for securely accessing the cache memory provided by the present invention.

[0021] Figure 3 This is the third flow chart of the method for securely accessing the cache memory provided by the present invention.

[0022] Figure 4 It is a structural diagram of a multi-core processor.

[0023] Figure 5 It is a schematic diagram of the secure access process of the cache memory provided by the present invention.

[0024] Figure 6 It is a schematic diagram of the structure of the secure access device for the cache memory provided by the present invention.

[0025] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Combine the following Figure 1-Figure 5 The secure access method of the cache memory of the present invention is described.

[0028] Figure 1 FIG. 1 is a flow chart of a method for securely accessing a cache memory provided by the present invention. The method is executed by firmware running in a processor, such as Figure 1 As shown, the method includes the following: Step 101: In response to a call to a function for accessing a cache memory provided by the firmware, the interrupt status bit of the interrupt controller of the processor is used to determine whether interrupt requests from various peripherals connected to the processor are masked.

[0029] like Figure 5 As shown, the functions for accessing the cache memory (cache functions) may include: invalid function, clean function, flush function, etc. When any of the invalid function, clean function, and flush function is called, the method provided by the embodiment of the present invention is executed to safely access the cache memory.

[0030] The main function of the Invalid function is to mark a specific cache line in the cache as invalid. This means that the valid bit in the cache line is set to 0, indicating that the data in the cache is no longer valid or inconsistent with the data in the main memory.

[0031] The Clean function writes the cache line marked as dirty in the cache back to the main memory and clears its dirty bit. This means that the data in the cache line has been synchronized to the main memory and the cache line is now considered clean.

[0032] The Flush function is usually understood as performing a combination of the two operations Clean and Invalid. That is, it first writes all dirty cache lines back to main memory and then marks all cache lines as invalid.

[0033] The processor includes at least one core. The interrupt controller of the processor distributes interrupt requests from various peripherals to the corresponding core.

[0034] In the specific implementation process, in the firmware, it can be determined in a variety of ways that the function accessing the cache memory is called, so as to perform relevant processing of the interrupt. Figure 2 and Figure 3 The relevant content in will not be repeated here.

[0035] The interrupt controller includes an interrupt status bit, which can be used to determine whether interrupt requests from various peripherals connected to the processor are masked.

[0036] Just as an example, Figure 4 As shown in the figure, the processor has 8 A55 processor cores, which together form a cluster architecture. A55 has three levels of cache, of which L1 and L2 are private to each core, and L3 is in the DSU and is shared by all cores in the cluster architecture. In the cluster architecture, all interrupt signals originate from the Generic Interrupt Controller (GIC). The interrupt controller is a controller designed for managing and allocating interrupt requests in the ARM architecture. It can efficiently handle interrupts from various devices and accurately route them to the corresponding cores. Among them, the interrupt controller GIC600 version is optimized for large SoC (System-on-Chip) designs. Its distributed IP architecture enables each component to be flexibly deployed in different clock domains, power domains and hardware designs, thereby greatly improving the scalability and adaptability of the system.

[0037] Given that the processor's eight A55 cores all run at the highest execution level, EL3 (EL0 is mainly for application code execution, EL1 is reserved for the operating system, EL2 is the hypervisor's operating environment, and EL3 is designed for underlying firmware and security code), GIC configures all interrupts as FIQ (Fast Interrupt Request) interrupts by default. Therefore, in the specific implementation process, the second bit of the A55 processor's internal register SCR_EL3 can be used to determine whether the interrupt is masked, as well as to mask and restore the interrupt. For example, when the second bit of SCR_EL3 is 1, it means that the interrupt is masked; when it is 0, it means that the interrupt is not masked.

[0038] In a specific implementation process, when it is confirmed that the interrupt request of the processor has been shielded, it is not necessary to perform any processing on the interrupt controller.

[0039] Step 102: In response to the interrupt request of the processor not being masked, the interrupt request from various peripherals is masked by using the interrupt control bit of the interrupt controller.

[0040] When the interrupt request of the processor is not masked, the interrupt control bit of the interrupt controller can be used to mask the interrupt requests from various peripherals. For example, the second bit of the internal register SCR_EL3 of the A55 processor is set to 1, and the interrupt is masked.

[0041] Since the present invention relies on the coordinated operation of multiple processor cores, the system needs to go through a series of careful pre-check processes before executing the interrupt shutdown operation. These checks are intended to ensure that no process is currently accessing or modifying cache data, thereby maintaining data consistency and integrity. The pre-check may include locking operations on related resources and a detailed review of concurrent access status.

[0042] Step 103: In response to the function accessing the cache memory being returned, the interrupt control bit of the interrupt controller is used to restore the interrupt requests from various peripherals.

[0043] When it is determined that the function accessing the cache memory is returned, the interrupt control bit of the interrupt controller can be used to restore the interrupt request from various peripherals. For example, the second bit of the internal register SCR_EL3 of the A55 processor is cleared to zero, and the interrupt is restored.

[0044] In multitasking or real-time systems, cache operations may face a series of problems due to interrupt interference: Unpredictability of interrupts: Interrupts triggered by external events are unpredictable and may occur at critical moments in cache operations, disrupting their normal flow.

[0045] Interrupt priority problem: In a multi-tasking system, high-priority interrupts may preempt CPU resources, causing cache operations to be delayed or interrupted.

[0046] Data consistency issues: Interruptions may cause incomplete data write or update operations in the cache, resulting in data inconsistency and affecting subsequent data processing and system decisions.

[0047] System performance degradation: Frequent interrupts occupy CPU time, delay cache operation completion, and reduce system response speed and throughput.

[0048] Deadlock and resource contention: Interrupt handlers and cache operations accessing data simultaneously may cause deadlock or resource contention, affecting system stability.

[0049] Context switching overhead: Context switching when an interrupt occurs brings additional overhead, which may significantly affect performance, especially when cache operations are frequent.

[0050] Real-time issues: Interrupt interference may cause cache operations to time out, affecting the performance of real-time systems.

[0051] Error handling complexity: Cache operation recovery or error handling after interruption increases the complexity of the system and requires ensuring the atomicity of the operation.

[0052] Software and hardware coordination issues: The cache management strategy at the software level may be incompatible with the hardware interrupt handling mechanism, resulting in improper cache state management.

[0053] Security vulnerabilities: Failure of the interrupt handler to properly handle cache data may introduce security vulnerabilities, resulting in unauthorized access or tampering of sensitive data.

[0054] In the embodiment provided by the present invention, when the function of accessing the cache memory provided by the firmware is called, the interrupt status bit of the interrupt controller of the processor is used to determine whether the interrupt request from various peripherals connected to the processor is shielded; when the interrupt request of the processor is not shielded, the interrupt control bit of the interrupt controller is used to shield the interrupt request from various peripherals; and when the function of accessing the cache memory is returned, the interrupt control bit of the interrupt controller is used to restore the interrupt request from various peripherals. Since various problems caused by interrupt interference can be avoided in the process of accessing the cache memory, data security can be effectively protected when the processor uses the cache, and data leakage and malicious attacks can be prevented.

[0055] Figure 2 FIG. 2 is a flow chart of the method for securely accessing a cache memory provided by the present invention. Figure 2 As shown, the method includes the following: Step 201: Call the interrupt masking code at the entry of the function accessing the cache memory.

[0056] The interrupt masking code is the code for masking the interrupt of a specific processor.

[0057] For example, the interrupt masking code is used to process the second bit of the internal register SCR_EL3 of the A55 processor to check whether the interrupt is masked, and mask it if the interrupt is not masked.

[0058] The interrupt masking code is called at the entry of the function accessing the cache memory. When the code is called, the firmware can determine that the function accessing the cache memory is called, thereby ensuring that the interrupt can be masked in time when accessing the cache memory.

[0059] Step 202: The interrupt masking code queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests of various peripherals are masked.

[0060] The interrupt masking code can query the interrupt status bit of the interrupt controller to determine whether the interrupt requests of various peripherals are masked. For example, the second bit of the internal register SCR_EL3 of the A55 processor can be read. If it is 0, it can be determined that the interrupt bit of the processor is masked.

[0061] Step 203 , when the interrupt shielding code determines according to the query result that the interrupt requests of various peripheral devices are not shielded, the interrupt control bit of the interrupt controller is set to shield the interrupt requests from various peripheral devices.

[0062] When the interrupt masking code determines that the interrupt request of the processor is not masked, the interrupt control bit of the interrupt controller can be used to mask the interrupt requests from various peripherals. For example, the interrupt masking code can set the second position of the internal register SCR_EL3 of the A55 processor to 1, and the interrupt is masked.

[0063] Step 204: Call the interrupt recovery code at the return point of the function that accesses the cache memory.

[0064] The interrupt recovery code is a code that can recover the interrupt of a specific processor.

[0065] For example, the interrupt recovery code is a code for processing the second bit of the internal register SCR_EL3 of the A55 processor to recover the interrupt function.

[0066] The interrupt recovery code is called at the return of the function accessing the cache memory. When this code is called, the firmware can determine that the function accessing the cache memory is returned, thereby ensuring that the interrupt can be recovered in time when the access to the cache memory is completed.

[0067] Step 205: The interrupt recovery code sets the interrupt control bit of the interrupt controller to recover the interrupt requests from various peripherals.

[0068] When the function accessing the cache memory is determined to be returned, the interrupt recovery code can use the interrupt control bit of the interrupt controller to restore the interrupt request from various peripherals. For example, the second bit of the internal register SCR_EL3 of the A55 processor can be cleared to zero, and the interrupt is restored.

[0069] Figure 3 FIG. 3 is a flow chart of the method for securely accessing a cache memory provided by the present invention. Figure 3 As shown, the method includes the following: Step 301: at the entry of a function for accessing a cache memory, a cache access flag stored at a preset position is set.

[0070] The cache access flag is set to 1 to indicate that the cache memory is accessed.

[0071] Step 302: When the polling function running in the firmware finds that the cache access flag is set, it queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests of various peripherals are blocked.

[0072] In order to know in time that the cache memory is accessed, a polling function can be run in the firmware. The polling function periodically queries the cache access flag. When the polling function finds that the cache access flag is set, it queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests of various peripherals are blocked.

[0073] Step 303: When determining that the interrupt request is not masked, the polling function sets the interrupt control bit of the interrupt controller to mask the interrupt requests from various peripherals.

[0074] When the polling function determines that the interrupt request of the processor is not masked, the interrupt control bit of the interrupt controller can be used to mask the interrupt requests from various peripherals. For example, the polling function can set the second position of the internal register SCR_EL3 of the A55 processor to 1, and the interrupt is masked.

[0075] Step 304: Clear the cache access flag at the return point of the function that accesses the cache memory.

[0076] The cache access flag is cleared to indicate that the access task to the cache memory is completed.

[0077] Step 305 : When the polling function finds that the cache access flag is cleared, the polling function sets the interrupt control bit of the interrupt controller to restore interrupt requests from various peripherals.

[0078] When the polling function determines that the function accessing the cache memory is returned, the interrupt control bit of the interrupt controller can be used to restore the interrupt request from various peripherals. For example, the second bit of the internal register SCR_EL3 of the A55 processor can be cleared to zero, and the interrupt is restored.

[0079] The secure access device for a cache memory provided by the present invention is described below. The secure access device for a cache memory described below and the secure access method for a cache memory described above can be referred to each other.

[0080] Figure 6 FIG. 1 is a schematic diagram of the structure of the secure access device for the cache memory provided by the present invention. Figure 6 As shown, the device 600 includes the following modules.

[0081] The determination module 610 is used to determine whether the interrupt requests from various peripherals connected to the processor are blocked in response to the function of accessing the cache memory provided by the firmware being called, using the interrupt status bit of the interrupt controller of the processor; wherein the processor includes at least one core, and the interrupt controller distributes the interrupt requests from the various peripherals to the corresponding cores.

[0082] The shielding module 620 is used to shield the interrupt requests from the various peripheral devices by using the interrupt control bit of the interrupt controller in response to the interrupt request of the processor not being shielded.

[0083] The recovery module 630 is used to respond to the function of accessing the cache memory being returned, and to utilize the interrupt control bit of the interrupt controller to recover the interrupt requests from the various peripheral devices.

[0084] Figure 7 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 7 As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute a safe access method for a cache memory, the method comprising: in response to the function of accessing the cache memory provided by the firmware being called, using the interrupt status bit of the interrupt controller of the processor to determine whether the interrupt request from various peripherals connected to the processor is masked; wherein the processor includes at least one core, and the interrupt controller distributes the interrupt request from the various peripherals to the corresponding core; in response to the interrupt request of the processor not being masked, using the interrupt control bit of the interrupt controller to mask the interrupt request from the various peripherals; and in response to the function of accessing the cache memory being returned, using the interrupt control bit of the interrupt controller to restore the interrupt request from the various peripherals.

[0085] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0086] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the secure access method for the cache memory provided by the above-mentioned methods, and the method includes: in response to the function of accessing the cache memory provided by the firmware being called, using the interrupt status bit of the interrupt controller of the processor to determine whether the interrupt requests from various peripherals connected to the processor are blocked; wherein the processor includes at least one core, and the interrupt controller distributes the interrupt requests from the various peripherals to the corresponding cores; in response to the interrupt request of the processor not being blocked, using the interrupt control bit of the interrupt controller to block the interrupt requests from the various peripherals; and in response to the function of accessing the cache memory being returned, using the interrupt control bit of the interrupt controller to restore the interrupt requests from the various peripherals.

[0087] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the secure access method for the cache memory provided by the above-mentioned methods, the method comprising: in response to the function for accessing the cache memory provided by the firmware being called, using the interrupt status bit of the interrupt controller of the processor to determine whether the interrupt requests from various peripherals connected to the processor are blocked; wherein the processor includes at least one core, and the interrupt controller distributes the interrupt requests from the various peripherals to the corresponding cores; in response to the interrupt request of the processor not being blocked, using the interrupt control bit of the interrupt controller to block the interrupt requests from the various peripherals; and in response to the function for accessing the cache memory being returned, using the interrupt control bit of the interrupt controller to restore the interrupt requests from the various peripherals.

[0088] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0089] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for securely accessing a cache memory, characterized in that: The method is performed by firmware running in a processor, and the method includes: In response to a function provided by the firmware for accessing a cache memory being called, determining whether interrupt requests from various peripherals connected to the processor are masked using an interrupt status bit of an interrupt controller of the processor; wherein the processor includes at least one core, and the interrupt controller distributes the interrupt requests from the various peripherals to corresponding cores; In response to the interrupt request of the processor not being masked, masking the interrupt requests from the various peripheral devices using the interrupt control bit of the interrupt controller; and In response to the function accessing the cache memory being returned, the interrupt request from the various peripherals is restored using the interrupt control bit of the interrupt controller.

2. The method for securely accessing a cache memory according to claim 1, wherein: Calling an interrupt masking code at the entry of the function accessing the cache memory; The method of using the interrupt status bit of the interrupt controller of the processor to determine whether the interrupt requests from various peripherals connected to the processor are shielded includes: The interrupt masking code queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests of the various peripherals are masked; In response to the interrupt request of the processor not being masked, using the interrupt control bit of the interrupt controller to mask the interrupt requests from the various peripherals, comprising: When it is determined according to the query result that the interrupt requests of the various peripheral devices are not masked, the interrupt masking code sets the interrupt control bit of the interrupt controller to mask the interrupt requests from the various peripheral devices.

3. The method for securely accessing a cache memory according to claim 2, wherein: Calling interrupt recovery code at the return of the function accessing the cache memory; The function in response to the access to the cache memory is returned, and the interrupt control bit of the interrupt controller is used to restore the interrupt requests from the various peripherals, including: The interrupt recovery code sets the interrupt control bit of the interrupt controller to recover the interrupt requests from the various peripherals.

4. The method for securely accessing a cache memory according to claim 1, wherein: The method further comprises: setting a cache access flag stored at a preset position at the entry of the function accessing the cache memory; The method of using the interrupt status bit of the interrupt controller of the processor to determine whether the interrupt requests from various peripherals connected to the processor are shielded includes: When the polling function running in the firmware finds that the cache access flag is set, it queries the interrupt status bit of the interrupt controller to determine whether the interrupt requests of the various peripherals are blocked; In response to the interrupt request of the processor not being masked, using the interrupt control bit of the interrupt controller to mask the interrupt requests from the various peripherals, comprising: When determining that the interrupt request is not masked, the polling function sets the interrupt control bit of the interrupt controller to mask the interrupt requests from the various peripherals.

5. The method for securely accessing a cache memory according to claim 4, wherein: Performing a zeroing operation on the cache access flag at the return point of the function accessing the cache memory; The function in response to the access to the cache memory is returned, and the interrupt control bit of the interrupt controller is used to restore the interrupt requests from the various peripherals, including: When the polling function finds that the cache access flag is cleared, the polling function sets the interrupt control bit of the interrupt controller to restore the interrupt requests from the various peripherals.

6. The method for securely accessing a cache memory according to any one of claims 2 to 5, characterized in that: The functions for accessing the cache memory include: an invalid function, a clean function, and a flush function; The function accessing the cache memory is called, including: Any of the invalid function, clean function and flush function is called.

7. A secure access device for a cache memory, characterized in that: The device comprises: a determination module, configured to determine whether interrupt requests from various peripherals connected to the processor are masked by using an interrupt status bit of an interrupt controller of the processor in response to a function provided by the firmware for accessing a high-speed cache memory being called; wherein the processor includes at least one core, and the interrupt controller distributes the interrupt requests from the various peripherals to corresponding cores; a shielding module, configured to shield the interrupt requests from the various peripheral devices by using the interrupt control bit of the interrupt controller in response to the interrupt request of the processor not being shielded; and The recovery module is used for recovering the interrupt requests from various peripheral devices by using the interrupt control bit of the interrupt controller in response to the function accessing the cache memory being returned.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method for securely accessing the cache memory according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the cache memory security access method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the cache memory security access method according to any one of claims 1 to 6 is implemented.

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