Scene modeling method and system for memory chip preparation

Abstract

The invention relates to the technical field of storage chips, and discloses a scene modeling method for preparation of a storage chip, which comprises the following steps of: generating an internal circuit diagram of the storage chip by using a disassembled part, identifying an equivalent circuit diagram of the internal circuit diagram, constructing an equivalent circuit model of the equivalent circuit diagram, and performing model micro-differentiation on the equivalent circuit model to obtain a model; generating an electric signal modeling result of the storage chip by using the micro-differentiation model; querying a heating part of the storage chip from the disassembled parts, identifying a heating circuit diagram of the heating part by using an internal circuit diagram, constructing a heating circuit model of the heating circuit diagram, and calculating heating parameters belonging to the heating part in the heating circuit model; and querying the deformed parts of the storage chip from the disassembled parts, calculating deformation parameters of the deformed parts, constructing an initial deformation model between the temperature parameters and the deformation parameters of the deformed parts, and performing precision adjustment on the initial deformation model by using a particle swarm algorithm. According to the invention, the scene modeling workload can be reduced while the scene modeling is meticulous.

Description

Technical Field

[0001] The present invention relates to a scene modeling method and system for storage chip preparation, belonging to the technical field of storage chips. Background Art

[0002] With the development of chip manufacturing technology and 5G technology, the quality requirements for the prepared memory chips are gradually increasing. For example, there are high requirements for the thermal stability and electrical signal stability of memory chips. However, the existing technology in memory chip preparation still cannot keep up with the quality requirements for memory chip preparation.

[0003] At present, some solutions use scenario modeling and simulation to simulate various parameters of the memory chip that is about to be put into use. Scenario modeling refers to the process of abstracting the operation logic of various parameters of the memory chip during operation into a mathematical model, and simulation refers to the process of simulating the operation logic of various parameters of the memory chip during operation. Both are processes of describing the operation logic of the memory chip. However, whether it is the former or the latter, in the prior art, most of them model the memory chip as a whole, and do not model the various parts inside the memory chip. For example, when the memory chip is installed on a certain device A, the prior art models the electrical signal, temperature and other data of the memory chip as a whole on the device A, and there is no solution that can model the various parts inside a single memory chip. Secondly, the memory chip is the result of circuit integration and must contain a large number of electronic devices. If these large numbers of electronic devices are modeled one by one, the modeling workload will be huge. Therefore, a solution is urgently needed to refine the scenario modeling while reducing the workload of scenario modeling. Summary of the invention

[0004] The present invention provides a scene modeling method, system and computer-readable storage medium for storage chip preparation, the main purpose of which is to refine the scene modeling while reducing the workload of scene modeling.

[0005] To achieve the above object, the present invention provides a scenario modeling method for memory chip preparation, comprising:

[0006] Dividing the scenes to be modeled of the memory chip, wherein the scenes to be modeled include electrical signal scenes, temperature scenes, and structure scenes;

[0007] In the electrical signal scenario, the memory chip is disassembled to obtain disassembled parts, an internal circuit diagram of the memory chip is generated using the disassembled parts, an equivalent circuit diagram of the internal circuit diagram is identified, an equivalent circuit model of the equivalent circuit diagram is constructed, model differentiation is performed on the equivalent circuit model to obtain a differentiated model, and an electrical signal modeling result of the memory chip is generated using the differentiated model;

[0008] In the temperature scenario, query the heat-generating parts of the memory chip from the disassembled parts, identify the heat-generating circuit diagram of the heat-generating parts using the internal circuit diagram, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating parts in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip;

[0009] In the structural scenario, the deformed parts of the memory chip are queried from the disassembled parts, the deformation parameters of the deformed parts are calculated, an initial deformation model between the temperature parameters of the deformed parts and the deformation parameters is constructed, the initial deformation model is adjusted in precision using a preset particle swarm algorithm to obtain an adjusted deformation model, and the structural modeling result of the memory chip is determined using the adjusted deformation model;

[0010] The electrical signal modeling result, the temperature modeling result and the structure modeling result are used as the scene modeling result of the storage chip in the scene to be modeled.

[0011] Optionally, the identifying an equivalent circuit diagram of the internal circuit diagram includes:

[0012] When there are a first plurality of resistors connected in parallel with a single capacitor in the internal circuit diagram, the first plurality of resistors are combined using the following formula to obtain a first combined resistor:

[0013]

[0014] Wherein, R1 represents the first combined resistor, represents the r1th resistor in the first plurality of resistors, and r1′ represents the number of the first plurality of resistors;

[0015] When a second plurality of resistors are connected in series in the internal circuit diagram and there is no capacitance between the second plurality of resistors, combining the second plurality of resistors to obtain a second combined resistor;

[0016] When there are a third plurality of resistors connected in parallel in the internal circuit diagram and there is no capacitance between the third plurality of resistors, the third plurality of resistors are combined using the following formula to obtain a third combined resistor:

[0017]

[0018] Wherein, R3 represents the third combined resistor, represents the r3th resistor in the third plurality of resistors, and r3′ represents the number of the third plurality of resistors;

[0019] The internal circuit diagram is converted into an equivalent circuit diagram by using the first combined resistor, the second combined resistor, and the third combined resistor.

[0020] Optionally, constructing an equivalent circuit model of the equivalent circuit diagram includes:

[0021] Querying the input terminal and the output terminal in the equivalent circuit diagram;

[0022] Identify a first trunk resistor at the input end, a parallel resistor connected in parallel with a capacitor between the input end and the output end, and a second trunk resistor at the output end;

[0023] An equivalent circuit model of the equivalent circuit diagram is constructed according to the first main circuit resistance, the parallel resistance and the second main circuit resistance.

[0024] Optionally, performing model differentiation on the equivalent circuit model to obtain a differentiated model includes:

[0025] The equivalent circuit model is differentiated using the following formula to obtain a differentiated model:

[0026]

[0027] in, represents the differential model, t represents the time, I0(t) represents the current value of the input terminal, U1(t), U2(t), U n (t) represents the parallel resistance, n represents the number of parallel resistances, m1, m2, m n represents the derivative order, represents the m1-order derivative of U1(t), represents the m2-order derivative of U2(t), Indicates U n (t)m n Derivatives, R1, R2, R n Represents parallel resistance, C1, C2, C n Represents the capacitance connected in parallel with the parallel resistor.

[0028] Optionally, constructing a heating circuit model of the heating circuit diagram includes:

[0029] Identifying a circuit input terminal and a circuit output terminal in the heating circuit diagram;

[0030] According to the circuit input end and the circuit output end, a heating circuit model of the heating circuit diagram is constructed using the following formula:

[0031]

[0032] in, represents a heating circuit model, w0 represents the total power input to the circuit input end, ΔT represents the temperature difference between the circuit input end and the circuit output end, R0 represents the thermal resistance between the circuit input end and the circuit output end, and C0 represents the thermal capacitance corresponding to R0.

[0033] Optionally, the calculating the heating parameters of the heating components in the heating circuit model includes:

[0034] Constructing a temperature difference model between the input end temperature and the output end temperature in the heating circuit model;

[0035] Constructing the component thermal resistance of the heat generating component;

[0036] The temperature difference model and the component thermal resistance are used as heating parameters.

[0037] Optionally, the calculating the deformation parameters of the deformed part includes:

[0038] The average difference in distances between atoms in the deformed part is calculated using the following formula:

[0039]

[0040] Among them, y1 represents the average difference in distance, d uv represents the distance between the uth atom and the vth atom in the deformed part, represents the mean distance between atoms in the deformed part, u′ 2 represents the number of atoms in the deformed part, and v0 represents the volume of the deformed part;

[0041] The number of atoms melted in the deformed part is calculated using the following formula:

[0042]

[0043] Among them, y2 represents the melting quantity, represents the mean distance between the u1th neighbor atom and the u2th neighbor atom of the uth atom, It means that the uth atom is the center and A sphere with radius express The number of atoms in represents the number of u1-th neighboring atoms, u″″ u Indicates compliance The number of the uth atom in the deformed part, d0 represents the distance between the atomic layers in the deformed part, and u 0 The number of atoms representing the atomic layer in the deformed part;

[0044] The average distance difference and the melting amount are used as deformation parameters of the deformed part.

[0045] Optionally, constructing an initial deformation model between the temperature parameter of the deformed part and the deformation parameter includes:

[0046] Acquire an internal circuit diagram, and identify a deformed circuit diagram of the deformed part from the internal circuit diagram;

[0047] Performing component integration on the deformed components in the deformed circuit diagram to obtain integrated components;

[0048] Collect historical temperature parameter values ​​and historical deformation parameter values ​​of the integrated parts within a historical period;

[0049] Taking the historical temperature parameter value as the abscissa and the historical deformation parameter value as the ordinate, constructing a temperature-deformation scatter plot between the historical temperature parameter value and the historical deformation parameter value;

[0050] Determine a first curve model of coordinate points in the temperature-deformation scatter plot;

[0051] Substituting the temperature parameter and the deformation parameter into the independent variable and the dependent variable in the first curve model to obtain a second curve model;

[0052] The second curve model is subjected to calculus processing with respect to the time variable to obtain an initial deformation model.

[0053] Optionally, the using a preset particle swarm algorithm to adjust the accuracy of the initial deformation model to obtain an adjusted deformation model includes:

[0054] The preset particle swarm algorithm includes:

[0055] Randomly generating initial regression coefficients of the initial deformation model;

[0056] Calculate the fitness value between the virtual deformation parameter and the real deformation parameter of the initial deformation model under the initial regression coefficient;

[0057] Using the fitness value to update the individual optimal position and the global optimal position of the initial regression coefficient;

[0058] According to the individual optimal position and the global optimal position, the initial regression coefficient is updated to obtain an updated regression coefficient;

[0059] When the fitness value corresponding to the updated regression coefficient meets the preset fitness value, the updated regression coefficient is used to adjust the accuracy of the initial deformation model to obtain an adjusted deformation model.

[0060] In order to solve the above problems, the present invention also provides a scene modeling system for storage chip preparation, the system comprising:

[0061] A scene division module, used to divide the scenes to be modeled of the storage chip, wherein the scenes to be modeled include electrical signal scenes, temperature scenes and structure scenes;

[0062] an electrical signal modeling module, configured to, in the electrical signal scenario, disassemble the memory chip to obtain disassembled parts, generate an internal circuit diagram of the memory chip using the disassembled parts, identify an equivalent circuit diagram of the internal circuit diagram, construct an equivalent circuit model of the equivalent circuit diagram, perform model differentiation on the equivalent circuit model to obtain a differentiated model, and generate an electrical signal modeling result of the memory chip using the differentiated model;

[0063] a temperature modeling module, for querying the heat-generating parts of the memory chip from the disassembled parts under the temperature scenario, identifying the heat-generating circuit diagram of the heat-generating parts by using the internal circuit diagram, constructing a heat-generating circuit model of the heat-generating circuit diagram, calculating the heat-generating parameters belonging to the heat-generating parts in the heat-generating circuit model, inserting the heat-generating parameters into the heat-generating circuit model, and obtaining the temperature modeling result of the memory chip;

[0064] a structural modeling module, for querying the deformed parts of the memory chip from the disassembled parts in the structural scenario, calculating the deformation parameters of the deformed parts, constructing an initial deformation model between the temperature parameters of the deformed parts and the deformation parameters, adjusting the accuracy of the initial deformation model by using a preset particle swarm algorithm to obtain an adjusted deformation model, and determining the structural modeling result of the memory chip by using the adjusted deformation model;

[0065] The scene modeling module is used to use the electrical signal modeling result, the temperature modeling result and the structure modeling result as the scene modeling result of the storage chip in the scene to be modeled.

[0066] In order to solve the above problem, the present invention further provides an electronic device, the electronic device comprising:

[0067] at least one processor; and,

[0068] a memory communicatively connected to the at least one processor; wherein,

[0069] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to implement the above-mentioned scene modeling method for memory chip preparation.

[0070] In order to solve the above problems, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned scene modeling method for storage chip preparation.

[0071] Compared with the problems described in the background technology, the embodiment of the present invention disassembles the memory chip to decompose the memory chip into multiple subdivided parts, so as to perform detailed modeling on the subdivided parts later. Furthermore, the embodiment of the present invention identifies the equivalent circuit diagram of the internal circuit diagram to integrate and simplify the complex circuit diagram with a large number of parts, so as to reduce the workload of subsequent data modeling based on the circuit diagram. Furthermore, the embodiment of the present invention constructs an equivalent circuit model of the equivalent circuit diagram to abstract the circuit operation logic inside the memory chip into a model form. Furthermore, the embodiment of the present invention performs model differentiation on the equivalent circuit model to observe the changes of voltage signals and current signals over time and the relationship between voltage signals and current signals. Furthermore, the embodiment of the present invention The internal circuit diagram is used to identify the heating circuit diagram of the heating part, so as to convert the internal circuit diagram into an equivalent circuit diagram containing only the heating part. Furthermore, the embodiment of the present invention calculates the deformation parameters of the deformed part to calculate the parameters of each deformed part, and performs structural scene modeling on each part data. Furthermore, the embodiment of the present invention constructs an initial deformation model between the temperature parameter of the deformed part and the deformation parameter to generate a regression model between the temperature parameter and the deformation parameter, thereby determining the relationship between the change of the deformation parameter with temperature change. Furthermore, the embodiment of the present invention adjusts the accuracy of the initial deformation model by using a preset particle swarm algorithm to obtain an adjusted deformation model, which is used to solve the unknown regression coefficients in the initial deformation model by using a particle swarm algorithm. Therefore, the scene modeling method for storage chip preparation proposed by the present invention can refine the scene modeling while reducing the workload of scene modeling. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 A schematic flow chart of a scene modeling method for memory chip preparation provided by an embodiment of the present invention;

[0073] Figure 2 A schematic diagram of a module for implementing the scenario modeling method for storage chip preparation provided by an embodiment of the present invention;

[0074] Figure 3 A schematic diagram of the structure of an electronic device for implementing the scene modeling method for storage chip preparation provided in one embodiment of the present invention.

[0075] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0076] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0077] The embodiment of the present application provides a scenario modeling method for the preparation of a storage chip. The execution subject of the scenario modeling method for the preparation of a storage chip includes but is not limited to at least one of the electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiment of the present application. In other words, the scenario modeling method for the preparation of a storage chip can be executed by software or hardware installed in a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0078] Embodiment 1:

[0079] Reference Figure 1 FIG. 1 is a flow chart of a scene modeling method for memory chip preparation according to an embodiment of the present invention. In this embodiment, the scene modeling method for memory chip preparation includes:

[0080] S1. Divide the scenes to be modeled of the storage chip, wherein the scenes to be modeled include an electrical signal scene, a temperature scene, and a structure scene.

[0081] In an embodiment of the present invention, the memory chip refers to a memory with a storage function composed of an integrated circuit, such as a dynamic random access memory (DRAM) and a static random access memory (SRAM). The scenario to be modeled refers to a memory chip operation logic scenario that needs to be abstracted as a mathematical model or needs to be simulated. Furthermore, the electrical signal scenario refers to a scenario of changes in current and voltage signals in a circuit of the memory chip under input current and input voltage scenarios. The temperature scenario refers to a scenario of changes in temperature of a region on the memory chip under input current and input voltage scenarios. The structural scenario refers to a scenario of changes in the internal structure (such as atoms, crystals, and amorphous materials, etc.) of the memory chip under input current and input voltage scenarios.

[0082] S2. In the electrical signal scenario, the memory chip is disassembled to obtain disassembled parts, an internal circuit diagram of the memory chip is generated using the disassembled parts, an equivalent circuit diagram of the internal circuit diagram is identified, an equivalent circuit model of the equivalent circuit diagram is constructed, the equivalent circuit model is differentiated to obtain a differentiated model, and the electrical signal modeling result of the memory chip is generated using the differentiated model.

[0083] The embodiment of the present invention performs chip disassembly on the memory chip to decompose the memory chip into a plurality of subdivided parts, so as to subsequently perform detailed modeling on the subdivided parts.

[0084] Optionally, the process of disassembling the memory chip to obtain disassembled parts refers to the process of decomposing the memory chip as a whole into multiple parts.

[0085] Optionally, the process of generating the internal circuit diagram of the memory chip using the disassembled parts refers to the process of abstracting the physical integrated circuit on the memory chip into a circuit diagram, that is, drawing the circuit distribution on the memory chip into a circuit diagram.

[0086] Furthermore, the embodiment of the present invention identifies an equivalent circuit diagram of the internal circuit diagram to integrate and simplify a complex circuit diagram with a large number of parts, thereby reducing the workload of subsequent data modeling based on the circuit diagram.

[0087] The equivalent circuit diagram refers to a simplified circuit diagram that only includes a power supply, a resistor and a capacitor.

[0088] In one embodiment of the present invention, the identifying the equivalent circuit diagram of the internal circuit diagram includes: when there are first multiple resistors connected in parallel with a single capacitor in the internal circuit diagram, combining the first multiple resistors using the following formula to obtain a first combined resistor:

[0089]

[0090] Wherein, R1 represents the first combined resistor, represents the r1th resistor in the first plurality of resistors, and r1′ represents the number of the first plurality of resistors;

[0091] When there are a second plurality of resistors connected in series in the internal circuit diagram and there is no capacitance between the second plurality of resistors, the second plurality of resistors are combined to obtain a second combined resistor; when there are a third plurality of resistors connected in parallel in the internal circuit diagram and there is no capacitance between the third plurality of resistors, the third plurality of resistors are combined using the following formula to obtain a third combined resistor:

[0092]

[0093] Wherein, R3 represents the third combined resistor, represents the r3th resistor in the third plurality of resistors, and r3′ represents the number of the third plurality of resistors;

[0094] The internal circuit diagram is converted into an equivalent circuit diagram by using the first combined resistor, the second combined resistor, and the third combined resistor.

[0095] The first plurality of resistors refers to a plurality of resistors connected in parallel with a single capacitor at the same time,

[0096] Optionally, when there are a second plurality of resistors connected in series in the internal circuit diagram and there is no capacitance between the second plurality of resistors, the principle of merging the second plurality of resistors to obtain a second combined resistor is similar to the principle of merging the first plurality of resistors to obtain a first combined resistor, and no further details are given here.

[0097] Optionally, the process of converting the internal circuit diagram into an equivalent circuit diagram using the first combined resistor, the second combined resistor and the third combined resistor refers to the process of replacing the electronic components in the original internal circuit diagram with the first combined resistor, the second combined resistor and the third combined resistor.

[0098] Furthermore, the embodiment of the present invention constructs an equivalent circuit model of the equivalent circuit diagram to abstract the circuit operation logic inside the memory chip into a model form.

[0099] In one embodiment of the present invention, the construction of the equivalent circuit model of the equivalent circuit diagram includes: querying the input end and the output end in the equivalent circuit diagram; identifying a first main circuit resistor at the input end, a parallel resistor connected in parallel with a capacitor between the input end and the output end, and a second main circuit resistor at the output end; and constructing the equivalent circuit model of the equivalent circuit diagram using the following formula according to the first main circuit resistor, the parallel resistor, and the second main circuit resistor:

[0100] U out (t) = U int (t)-(I0(t)R0+U1(t)+U2(t)...U n (t)+I0(t)R′0)

[0101] Among them, U out (t) = U int (t)-(I0(t)R0+U1(t)+U2(t)...U n (t)+I′0(t)R′0) represents the equivalent circuit model, U int (t) represents the voltage value of the input terminal, t represents the time, I0(t) represents the current value of the input terminal, R0 represents the first trunk resistance, U1(t), U2(t), U n (t) represents the voltage across the parallel resistor, n represents the number of parallel resistors, and R′0 represents the second trunk resistor.

[0102] The first trunk resistor refers to a resistor connected in series with a power source, and the second trunk resistor refers to a resistor connected in series with a load end.

[0103] Furthermore, the embodiment of the present invention performs model differentiation on the equivalent circuit model to observe the changes of the voltage signal and the current signal over time and the relationship between the voltage signal and the current signal.

[0104] In one embodiment of the present invention, performing model differentiation on the equivalent circuit model to obtain a differentiated model includes: performing model differentiation on the equivalent circuit model using the following formula to obtain a differentiated model:

[0105]

[0106] in, represents the differential model, t represents the time, I0(t) represents the current value of the input terminal, U1(t), U2(t), U n (t) represents the parallel resistance, n represents the number of parallel resistances, m1, m2, m n represents the derivative order, represents the m1-order derivative of U1(t), represents the m2-order derivative of U2(t), Indicates U n (t)m n Derivatives, R1, R2, R n Represents parallel resistance, C1, C2, C n Represents the capacitance connected in parallel with the parallel resistor.

[0107] Optionally, the process of generating the electrical signal modeling result of the memory chip by using the differential differentiation model refers to the process of using the differential differentiation model as the electrical signal modeling result.

[0108] S3. In the temperature scenario, query the heat-generating parts of the memory chip from the disassembled parts, use the internal circuit diagram to identify the heat-generating circuit diagram of the heat-generating parts, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating parts in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip.

[0109] In the embodiment of the present invention, the heat generating component refers to an electronic device that generates heat under the action of input current and input voltage signals, such as a resistor.

[0110] Furthermore, the embodiment of the present invention uses the internal circuit diagram to identify the heating circuit diagram of the heating component, so as to convert the internal circuit diagram into an equivalent circuit diagram containing only the heating component.

[0111] The heating circuit diagram refers to converting the internal circuit diagram into an equivalent circuit diagram that only includes the heating components.

[0112] Optionally, the process of using the internal circuit diagram to identify the heating circuit diagram of the heating component refers to removing non-heating components from the internal circuit diagram and integrating the circuit diagram consisting of the remaining heating components into an equivalent circuit diagram.

[0113] In one embodiment of the present invention, the construction of the heating circuit model of the heating circuit diagram includes: identifying a circuit input end and a circuit output end in the heating circuit diagram; and constructing the heating circuit model of the heating circuit diagram according to the circuit input end and the circuit output end using the following formula:

[0114]

[0115] in, represents a heating circuit model, w0 represents the total power input to the circuit input end, ΔT represents the temperature difference between the circuit input end and the circuit output end, R0 represents the thermal resistance between the circuit input end and the circuit output end, and C0 represents the thermal capacitance corresponding to R0.

[0116] In one embodiment of the present invention, the calculation of the heating parameters of the heating component in the heating circuit model includes: constructing a temperature difference model between the input end temperature and the output end temperature in the heating circuit model; and constructing the component thermal resistance of the heating component using the following formula:

[0117]

[0118] Among them, R0 represents the thermal resistance of the part, α represents the thermal conductivity of the heat-generating part, s represents the area of ​​the heat-generating part, and l represents the thickness of the heat-generating part;

[0119] The temperature difference model and the component thermal resistance are used as heating parameters.

[0120] The temperature difference model refers to the temperature difference between the input end temperature and the output end temperature.

[0121] S4. In the structural scenario, the deformed parts of the memory chip are queried from the disassembled parts, the deformation parameters of the deformed parts are calculated, an initial deformation model between the temperature parameters of the deformed parts and the deformation parameters is constructed, the initial deformation model is adjusted in precision using a preset particle swarm algorithm to obtain an adjusted deformation model, and the structural modeling result of the memory chip is determined using the adjusted deformation model.

[0122] In the embodiment of the present invention, the deformable component refers to a component whose internal structure changes under temperature changes, such as a component on a memory chip that converts between crystal and amorphous under temperature.

[0123] Furthermore, the embodiment of the present invention calculates the deformation parameters of the deformed parts to calculate the parameters of each deformed part, thereby performing structural scene modeling on each part data.

[0124] In one embodiment of the present invention, the calculating of the deformation parameters of the deformed part includes: calculating the average distance difference of atoms in the deformed part using the following formula:

[0125]

[0126] Among them, y1 represents the average difference in distance, d uv represents the distance between the uth atom and the vth atom in the deformed part, represents the mean distance between atoms in the deformed part, u′ 2 represents the number of atoms in the deformed part, and v0 represents the volume of the deformed part;

[0127] The number of atoms melted in the deformed part is calculated using the following formula:

[0128]

[0129] Among them, y2 represents the melting quantity, represents the mean distance between the u1th neighbor atom and the u2th neighbor atom of the uth atom, It means that the u-th atom is the center and A sphere with radius express The number of atoms in represents the number of u1-th neighboring atoms, u″″ u Indicates compliance The number of the uth atom in the deformed part, d0 represents the distance between the atomic layers in the deformed part, and u 0 The number of atoms representing the atomic layer in the deformed part;

[0130] The average distance difference and the melting amount are used as deformation parameters of the deformed part.

[0131] The average distance difference refers to the average distance difference between atoms, and the melting quantity refers to the representation of the change in the number of atoms inside the deformed part due to the influence of temperature.

[0132] Furthermore, the embodiment of the present invention constructs an initial deformation model between the temperature parameter of the deformed part and the deformation parameter to generate a regression model between the temperature parameter and the deformation parameter, thereby determining the relationship between the change of the deformation parameter with the temperature change.

[0133] The initial deformation model refers to a regression model between the temperature parameter and the deformation parameter including unknown regression coefficients.

[0134] In one embodiment of the present invention, the construction of the initial deformation model between the temperature parameters and the deformation parameters of the deformable part includes: obtaining an internal circuit diagram and identifying the deformed circuit diagram of the deformable part from the internal circuit diagram; integrating the deformed parts in the deformed circuit diagram to obtain an integrated part; collecting historical temperature parameter values ​​and historical deformation parameter values ​​of the integrated part within a historical period; constructing a temperature-deformation scatter plot between the historical temperature parameter values ​​and the historical deformation parameter values ​​with the historical temperature parameter values ​​as the horizontal coordinate and the historical deformation parameter values ​​as the vertical coordinate; determining a first curve model of the coordinate points in the temperature-deformation scatter plot; substituting the temperature parameter and the deformation parameter into the independent variable and the dependent variable in the first curve model to obtain a second curve model; and performing calculus processing on the second curve model with respect to the time variable to obtain an initial deformation model.

[0135] Among them, the first curve model refers to a curve function estimated according to the distribution of the temperature-deformation scatter diagram, and is not the fitting result of all coordinate points in the temperature-deformation scatter diagram. For example, if the distribution of coordinate points in the temperature-deformation scatter diagram is shaped like a slant line, y=kx+b is used as the first curve model; if the distribution of coordinate points in the temperature-deformation scatter diagram is shaped like a parabola, y squared=2px is used as the first curve model.

[0136] Optionally, the principle of integrating the deformed parts in the deformed circuit diagram to obtain the integrated parts is similar to the principle of identifying the equivalent circuit diagram of the internal circuit diagram mentioned above. For example, when two deformed parts are connected in series, the deformation parameters of the two parts are combined into a sum of deformation parameters. Furthermore, the process of performing calculus processing on the second curve model with respect to the time variable to obtain the initial deformation model refers to performing partial derivative processing on the second curve model with respect to the time variable.

[0137] Furthermore, the embodiment of the present invention adjusts the accuracy of the initial deformation model by using a preset particle swarm algorithm to obtain an adjusted deformation model, which is used to solve the unknown regression coefficients in the initial deformation model by using the particle swarm algorithm.

[0138] The adjusted deformation model refers to the initial deformation model after solving the accurate regression coefficient.

[0139] In one embodiment of the present invention, the method of using a preset particle swarm algorithm to adjust the accuracy of the initial deformation model to obtain an adjusted deformation model includes: the preset particle swarm algorithm includes: randomly generating an initial regression coefficient of the initial deformation model; calculating the fitness value between the virtual deformation parameter and the real deformation parameter of the initial deformation model under the initial regression coefficient; using the fitness value to update the individual optimal position and the global optimal position of the initial regression coefficient; updating the initial regression coefficient according to the individual optimal position and the global optimal position to obtain an updated regression coefficient; when the fitness value corresponding to the updated regression coefficient meets the preset fitness value, using the updated regression coefficient to adjust the accuracy of the initial deformation model to obtain an adjusted deformation model.

[0140] Among them, the virtual deformation parameter refers to the value of the dependent variable calculated by substituting the initial regression coefficient into the initial deformation model, the real deformation parameter refers to the value of the fixed dependent variable corresponding to the independent variable in the initial deformation model, and the fitness value refers to the error between the virtual deformation parameter and the real deformation parameter.

[0141] Exemplarily, the preset particle swarm algorithm includes: randomly generating a set of solutions as the initial position and speed of particles (particles, i.e., regression coefficients); calculating the fitness value of each particle according to the objective function of the problem; for each particle, if its fitness value is better than the previous individual best fitness value, updating the individual best position; in the entire particle swarm, if the fitness value of a particle is better than the current global best fitness value, updating the global best position; updating the speed and position of the particle: updating the speed and position of the particle according to the formula corresponding to the particle swarm algorithm; repeating the above steps until the global best fitness value meets the preset accuracy).

[0142] Furthermore, in an embodiment of the present invention, the structural modeling result refers to the adjusted deformation model.

[0143] S5. Use the electrical signal modeling result, the temperature modeling result and the structure modeling result as the scene modeling result of the storage chip in the scene to be modeled.

[0144] Compared with the problems described in the background technology, the embodiment of the present invention disassembles the memory chip to decompose the memory chip into multiple subdivided parts, so as to perform detailed modeling on the subdivided parts later. Furthermore, the embodiment of the present invention identifies the equivalent circuit diagram of the internal circuit diagram to integrate and simplify the complex circuit diagram with a large number of parts, so as to reduce the workload of subsequent data modeling based on the circuit diagram. Furthermore, the embodiment of the present invention constructs an equivalent circuit model of the equivalent circuit diagram to abstract the circuit operation logic inside the memory chip into a model form. Furthermore, the embodiment of the present invention performs model differentiation on the equivalent circuit model to observe the changes of voltage signals and current signals over time and the relationship between voltage signals and current signals. Furthermore, the embodiment of the present invention The internal circuit diagram is used to identify the heating circuit diagram of the heating part, so as to convert the internal circuit diagram into an equivalent circuit diagram containing only the heating part. Furthermore, the embodiment of the present invention calculates the deformation parameters of the deformed part to calculate the parameters of each deformed part, and performs structural scene modeling on each part data. Furthermore, the embodiment of the present invention constructs an initial deformation model between the temperature parameter of the deformed part and the deformation parameter to generate a regression model between the temperature parameter and the deformation parameter, thereby determining the relationship between the change of the deformation parameter with temperature change. Furthermore, the embodiment of the present invention adjusts the accuracy of the initial deformation model by using a preset particle swarm algorithm to obtain an adjusted deformation model, which is used to solve the unknown regression coefficients in the initial deformation model by using a particle swarm algorithm. Therefore, the scene modeling method for storage chip preparation proposed by the present invention can refine the scene modeling while reducing the workload of scene modeling.

[0145] Embodiment 2:

[0146] like Figure 2 As shown, it is a functional module diagram of the scene modeling system under the preparation of the storage chip of the present invention.

[0147] The scene modeling system 200 for storage chip preparation according to the present invention can be installed in an electronic device. According to the functions implemented, the scene modeling system for storage chip preparation can include a scene division module 201, an electrical signal modeling module 02, a temperature modeling module 203, a structure modeling module 204, a scene modeling module 205, a step return module 206 and a result generation module 207. The module according to the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0148] In the embodiment of the present invention, the functions of each module / unit are as follows:

[0149] The scene division module 201 is used to divide the scenes to be modeled of the storage chip, wherein the scenes to be modeled include electrical signal scenes, temperature scenes and structure scenes;

[0150] The electrical signal modeling module 202 is used to disassemble the memory chip in the electrical signal scenario to obtain disassembled parts, generate an internal circuit diagram of the memory chip using the disassembled parts, identify an equivalent circuit diagram of the internal circuit diagram, construct an equivalent circuit model of the equivalent circuit diagram, perform model differentiation on the equivalent circuit model to obtain a differentiated model, and generate an electrical signal modeling result of the memory chip using the differentiated model;

[0151] The temperature modeling module 203 is used to query the heat-generating parts of the memory chip from the disassembled parts under the temperature scenario, identify the heat-generating circuit diagram of the heat-generating parts by using the internal circuit diagram, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating parts in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip;

[0152] The structural modeling module 204 is used to query the deformed parts of the memory chip from the disassembled parts in the structural scenario, calculate the deformation parameters of the deformed parts, construct an initial deformation model between the temperature parameters of the deformed parts and the deformation parameters, use a preset particle swarm algorithm to adjust the accuracy of the initial deformation model to obtain an adjusted deformation model, and use the adjusted deformation model to determine the structural modeling result of the memory chip;

[0153] The scene modeling module 205 is used to use the electrical signal modeling result, the temperature modeling result and the structure modeling result as the scene modeling result of the storage chip in the scene to be modeled.

[0154] In detail, the modules in the scene modeling system 200 for the storage chip in the embodiment of the present invention are used in the same manner as described above. Figure 1 The same technical means as the scene modeling method for storage chip preparation described in , and can produce the same technical effects, will not be repeated here.

[0155] Embodiment 3:

[0156] like Figure 3 1 is a schematic diagram of the structure of an electronic device for implementing a scene modeling method for a memory chip according to an embodiment of the present invention.

[0157] The electronic device 1 may include a processor 10, a memory 11, a bus 12 and a communication interface 13, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a scene modeling program prepared for a memory chip.

[0158] Among them, the memory 11 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (for example: SD or DX memory, etc.), magnetic memory, disk, optical disk, etc. The memory 11 may be an internal storage unit of the electronic device 1 in some embodiments, such as a mobile hard disk of the electronic device 1. The memory 11 may also be an external storage device of the electronic device 1 in other embodiments, such as a plug-in mobile hard disk, a smart memory card (SmartMediaCard, SMC), a secure digital (SecureDigital, SD) card, a flash card (FlashCard), etc. equipped on the electronic device 1. Further, the memory 11 may also include both an internal storage unit of the electronic device 1 and an external storage device. The memory 11 can not only be used to store application software and various types of data installed in the electronic device 1, such as the code of the scene modeling program prepared for the storage chip, but also be used to temporarily store data that has been output or is to be output.

[0159] The processor 10 may be composed of an integrated circuit in some embodiments, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor 10 is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes or executes programs or modules stored in the memory 11 (for example, scene modeling programs prepared for storage chips, etc.), and calls data stored in the memory 11 to execute various functions of the electronic device 1 and process data.

[0160] The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The bus is configured to realize connection and communication between the memory 11 and at least one processor 10, etc.

[0161] Figure 3 Only an electronic device with components is shown, and those skilled in the art will understand that Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0162] For example, although not shown, the electronic device 1 may also include a power source (such as a battery) for supplying power to various components. Preferably, the power source may be logically connected to the at least one processor 10 through a power management device, so that the power management device can realize functions such as charging management, discharging management, and power management. The power source may also include any components such as one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, etc. The electronic device 1 may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0163] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0164] Optionally, the electronic device 1 may further include a user interface, which may be a display (Display), an input unit (such as a keyboard (Keyboard)), and optionally, the user interface may also be a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch device, etc. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device 1 and to display a visual user interface.

[0165] It should be understood that the embodiment is for illustration only and the scope of the patent application is not limited to this structure.

[0166] The scene modeling program for the storage chip stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can achieve:

[0167] Dividing the scenes to be modeled of the memory chip, wherein the scenes to be modeled include electrical signal scenes, temperature scenes, and structure scenes;

[0168] In the electrical signal scenario, the memory chip is disassembled to obtain disassembled parts, an internal circuit diagram of the memory chip is generated using the disassembled parts, an equivalent circuit diagram of the internal circuit diagram is identified, an equivalent circuit model of the equivalent circuit diagram is constructed, model differentiation is performed on the equivalent circuit model to obtain a differentiated model, and an electrical signal modeling result of the memory chip is generated using the differentiated model;

[0169] In the temperature scenario, query the heat-generating parts of the memory chip from the disassembled parts, identify the heat-generating circuit diagram of the heat-generating parts using the internal circuit diagram, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating parts in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip;

[0170] In the structural scenario, the deformed parts of the memory chip are queried from the disassembled parts, the deformation parameters of the deformed parts are calculated, an initial deformation model between the temperature parameters of the deformed parts and the deformation parameters is constructed, the initial deformation model is adjusted in precision using a preset particle swarm algorithm to obtain an adjusted deformation model, and the structural modeling result of the memory chip is determined using the adjusted deformation model;

[0171] The electrical signal modeling result, the temperature modeling result and the structure modeling result are used as the scene modeling result of the storage chip in the scene to be modeled.

[0172] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 3 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0173] Furthermore, if the module / unit integrated in the electronic device 1 is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0174] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, the computer program can implement:

[0175] Dividing the scenes to be modeled of the memory chip, wherein the scenes to be modeled include electrical signal scenes, temperature scenes, and structure scenes;

[0176] In the electrical signal scenario, the memory chip is disassembled to obtain disassembled parts, an internal circuit diagram of the memory chip is generated using the disassembled parts, an equivalent circuit diagram of the internal circuit diagram is identified, an equivalent circuit model of the equivalent circuit diagram is constructed, model differentiation is performed on the equivalent circuit model to obtain a differentiated model, and an electrical signal modeling result of the memory chip is generated using the differentiated model;

[0177] In the temperature scenario, query the heat-generating parts of the memory chip from the disassembled parts, identify the heat-generating circuit diagram of the heat-generating parts using the internal circuit diagram, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating parts in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip;

[0178] In the structural scenario, the deformed parts of the memory chip are queried from the disassembled parts, the deformation parameters of the deformed parts are calculated, an initial deformation model between the temperature parameters of the deformed parts and the deformation parameters is constructed, the initial deformation model is adjusted in precision using a preset particle swarm algorithm to obtain an adjusted deformation model, and the structural modeling result of the memory chip is determined using the adjusted deformation model;

[0179] The electrical signal modeling result, the temperature modeling result and the structure modeling result are used as the scene modeling result of the storage chip in the scene to be modeled.

[0180] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0181] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0182] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0183] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A scenario modeling method for storage chip preparation, characterized in that: The method comprises: Dividing the scenes to be modeled of the memory chip, wherein the scenes to be modeled include electrical signal scenes, temperature scenes, and structure scenes; In the electrical signal scenario, the memory chip is disassembled to obtain disassembled parts, an internal circuit diagram of the memory chip is generated using the disassembled parts, an equivalent circuit diagram of the internal circuit diagram is identified, an equivalent circuit model of the equivalent circuit diagram is constructed, model differentiation is performed on the equivalent circuit model to obtain a differentiated model, and an electrical signal modeling result of the memory chip is generated using the differentiated model; In the temperature scenario, query the heat-generating parts of the memory chip from the disassembled parts, identify the heat-generating circuit diagram of the heat-generating parts using the internal circuit diagram, construct a heat-generating circuit model of the heat-generating circuit diagram, calculate the heat-generating parameters belonging to the heat-generating parts in the heat-generating circuit model, insert the heat-generating parameters into the heat-generating circuit model, and obtain the temperature modeling result of the memory chip; In the structural scenario, the deformed parts of the memory chip are queried from the disassembled parts, the deformation parameters of the deformed parts are calculated, an initial deformation model between the temperature parameters of the deformed parts and the deformation parameters is constructed, the initial deformation model is adjusted in precision using a preset particle swarm algorithm to obtain an adjusted deformation model, and the structural modeling result of the memory chip is determined using the adjusted deformation model; The electrical signal modeling result, the temperature modeling result and the structure modeling result are used as the scene modeling result of the storage chip in the scene to be modeled.

2. The scene modeling method for storage chip preparation according to claim 1, characterized in that: The identifying the equivalent circuit diagram of the internal circuit diagram comprises: When there are a first plurality of resistors connected in parallel with a single capacitor in the internal circuit diagram, the first plurality of resistors are combined using the following formula to obtain a first combined resistor: Wherein, R1 represents the first combined resistor, represents the r1th resistor in the first plurality of resistors, and r1′ represents the number of the first plurality of resistors; When a second plurality of resistors are connected in series in the internal circuit diagram and there is no capacitance between the second plurality of resistors, combining the second plurality of resistors to obtain a second combined resistor; When there are a third plurality of resistors connected in parallel in the internal circuit diagram and there is no capacitance between the third plurality of resistors, the third plurality of resistors are combined using the following formula to obtain a third combined resistor: Wherein, R3 represents the third combined resistor, represents the r3th resistor in the third plurality of resistors, and r3′ represents the number of the third plurality of resistors; The internal circuit diagram is converted into an equivalent circuit diagram by using the first combined resistor, the second combined resistor, and the third combined resistor.

3. The scenario modeling method for storage chip preparation according to claim 1, characterized in that: The constructing of the equivalent circuit model of the equivalent circuit diagram comprises: Querying the input terminal and the output terminal in the equivalent circuit diagram; Identify a first trunk resistor at the input end, a parallel resistor connected in parallel with a capacitor between the input end and the output end, and a second trunk resistor at the output end; An equivalent circuit model of the equivalent circuit diagram is constructed according to the first main circuit resistance, the parallel resistance and the second main circuit resistance.

4. The scenario modeling method for storage chip preparation according to claim 1, characterized in that: The step of performing model differentiation on the equivalent circuit model to obtain a differentiated model includes: The equivalent circuit model is differentiated using the following formula to obtain a differentiated model: in, represents the differential model, t represents the time, I0(t) represents the current value of the input terminal, U1(t), U2(t), U n (t) represents the parallel resistance, n represents the number of parallel resistances, m1, m2, m n represents the derivative order, represents the m1-order derivative of U1(t), represents the m2-order derivative of U2(t), Indicates U n (t)m n Derivatives, R1, R2, R n Represents parallel resistance, C1, C2, C n Represents the capacitance connected in parallel with the parallel resistor.

5. The scenario modeling method for storage chip preparation according to claim 1, characterized in that: The heating circuit model of the heating circuit diagram is constructed, comprising: Identifying a circuit input terminal and a circuit output terminal in the heating circuit diagram; According to the circuit input end and the circuit output end, a heating circuit model of the heating circuit diagram is constructed using the following formula: in, represents a heating circuit model, w0 represents the total power input to the circuit input end, ΔT represents the temperature difference between the circuit input end and the circuit output end, R0 represents the thermal resistance between the circuit input end and the circuit output end, and C0 represents the thermal capacitance corresponding to R0.

6. The scene modeling method for storage chip preparation according to claim 1, characterized in that: The calculating of the heating parameters of the heating components in the heating circuit model includes: Constructing a temperature difference model between the input end temperature and the output end temperature in the heating circuit model; Constructing the component thermal resistance of the heat generating component; The temperature difference model and the component thermal resistance are used as heating parameters.

7. The scene modeling method for storage chip preparation according to claim 1, characterized in that: The calculating the deformation parameters of the deformed part comprises: The average difference in distances between atoms in the deformed part is calculated using the following formula: Among them, y1 represents the average difference in distance, d uv represents the distance between the uth atom and the vth atom in the deformed part, represents the mean distance between atoms in the deformed part, u' 2 represents the number of atoms in the deformed part, and v0 represents the volume of the deformed part; The number of atoms melted in the deformed part is calculated using the following formula: Among them, y2 represents the melting quantity, represents the mean distance between the u1th neighbor atom and the u2th neighbor atom of the uth atom, It means that the u-th atom is the center and A sphere with radius express The number of atoms in the u1 represents the number of u1-th neighboring atoms, u"" u Indicates compliance The number of the uth atom in the deformed part, d0 represents the distance between the atomic layers in the deformed part, and u 0 The number of atoms representing the atomic layer in the deformed part; The average distance difference and the melting amount are used as deformation parameters of the deformed part.

8. The scene modeling method for storage chip preparation according to claim 1, characterized in that: The constructing of an initial deformation model between the temperature parameter of the deformed part and the deformation parameter comprises: Acquire an internal circuit diagram, and identify a deformed circuit diagram of the deformed part from the internal circuit diagram; Performing component integration on the deformed components in the deformed circuit diagram to obtain integrated components; Collect historical temperature parameter values ​​and historical deformation parameter values ​​of the integrated parts within a historical period; Taking the historical temperature parameter value as the abscissa and the historical deformation parameter value as the ordinate, constructing a temperature-deformation scatter plot between the historical temperature parameter value and the historical deformation parameter value; Determine a first curve model of coordinate points in the temperature-deformation scatter plot; Substituting the temperature parameter and the deformation parameter into the independent variable and the dependent variable in the first curve model to obtain a second curve model; The second curve model is subjected to calculus processing with respect to the time variable to obtain an initial deformation model.

9. The scene modeling method for storage chip preparation according to claim 1, characterized in that: The method of using a preset particle swarm algorithm to adjust the accuracy of the initial deformation model to obtain an adjusted deformation model includes: The preset particle swarm algorithm includes: Randomly generating initial regression coefficients of the initial deformation model; Calculate the fitness value between the virtual deformation parameter and the real deformation parameter of the initial deformation model under the initial regression coefficient; Using the fitness value to update the individual optimal position and the global optimal position of the initial regression coefficient; According to the individual optimal position and the global optimal position, the initial regression coefficient is updated to obtain an updated regression coefficient; When the fitness value corresponding to the updated regression coefficient meets the preset fitness value, the accuracy of the initial deformation model is adjusted by using the updated regression coefficient to obtain the adjusted deformation model.

10. A scene modeling system for storage chip preparation, characterized in that: The system comprises: A scene division module, used to divide the scenes to be modeled of the storage chip, wherein the scenes to be modeled include electrical signal scenes, temperature scenes and structure scenes; an electrical signal modeling module, configured to, in the electrical signal scenario, disassemble the memory chip to obtain disassembled parts, generate an internal circuit diagram of the memory chip using the disassembled parts, identify an equivalent circuit diagram of the internal circuit diagram, construct an equivalent circuit model of the equivalent circuit diagram, perform model differentiation on the equivalent circuit model to obtain a differentiated model, and generate an electrical signal modeling result of the memory chip using the differentiated model; a temperature modeling module, for querying the heat-generating parts of the memory chip from the disassembled parts under the temperature scenario, identifying the heat-generating circuit diagram of the heat-generating parts by using the internal circuit diagram, constructing a heat-generating circuit model of the heat-generating circuit diagram, calculating the heat-generating parameters belonging to the heat-generating parts in the heat-generating circuit model, inserting the heat-generating parameters into the heat-generating circuit model, and obtaining the temperature modeling result of the memory chip; a structural modeling module, for querying the deformed parts of the memory chip from the disassembled parts in the structural scenario, calculating the deformation parameters of the deformed parts, constructing an initial deformation model between the temperature parameters of the deformed parts and the deformation parameters, adjusting the accuracy of the initial deformation model by using a preset particle swarm algorithm to obtain an adjusted deformation model, and determining the structural modeling result of the memory chip by using the adjusted deformation model; The scene modeling module is used to use the electrical signal modeling result, the temperature modeling result and the structure modeling result as the scene modeling result of the storage chip in the scene to be modeled.

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