Memory device and memory test system thereof

Abstract

A memory device according to an embodiment of the present disclosure includes: a first memory cell including a first electric fuse and a first program transistor connected in series between a first bit line and a ground voltage node; a second memory cell including a second electric fuse and a second program transistor connected in series between the first bit line and the ground voltage node; and a first test unit including a first test transistor connected between the first bit line and a ground voltage node.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0107047 filed in the Korean Intellectual Property Office on August 16, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor memory device and more particularly to a memory device and a test system thereof. Background Art

[0003] A one-time programmable (OTP) memory device may include a plurality of OTP memory cells including an electric fuse. The OTP memory device may store data based on whether the electric fuse is blown. For example, an OTP memory cell including a blown electric fuse may store data corresponding to "1", while an OTP memory cell including an unblown electric fuse may store data corresponding to "0".

[0004] Whether data is stored in the OTP memory cell as expected can be tested by measuring the resistance value of the electric fuse included in the OTP memory cell. However, as memory devices tend to be highly integrated, it becomes increasingly difficult to accurately measure the resistance of the electric fuse. Summary of the invention

[0005] The embodiments of the present disclosure are to solve the above technical problems. More specifically, the embodiments disclosed herein relate to a memory device configured to more accurately measure the resistance value of an electric fuse and a test system thereof.

[0006] A memory device according to an embodiment of the present disclosure includes: a first memory cell, including a first electric fuse and a first programming transistor connected in series between a first bit line and a ground voltage node; a second memory cell, including a second electric fuse and a second programming transistor connected in series between the first bit line and the ground voltage node; and a first test cell, including a first test transistor connected between the first bit line and the ground voltage node.

[0007] A test system according to an embodiment of the present disclosure includes: a memory device, the memory device including: a first storage cell connected to a first word line and a first bit line, a first test cell connected to a first pseudo word line and the first bit line, and a power supply pad connected to the first bit line; and a test device configured to measure a first current supplied to the power supply pad in response to activation of the first word line and the first bit line, a second current supplied to the power supply pad in response to activation of the first pseudo word line and the first bit line, and a third current supplied to the power supply pad in response to activation of the first bit line.

[0008] A memory device according to an embodiment of the present disclosure includes a memory cell array and a test cell array, the memory cell array includes a plurality of memory cells connected to a first bit line, the test cell array includes a first test cell and a second test cell connected to the first bit line. The first test cell includes a first test transistor, the first test transistor includes a first drain terminal electrically connected to the first bit line and a first source terminal connected to a ground voltage node, and the second test cell includes a second test transistor, the second test transistor includes a second drain terminal not electrically connected to the first bit line and a second source terminal connected to the ground voltage node. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a test system according to an embodiment of the present disclosure.

[0010] Figure 2 The present invention is described in more detail according to the embodiment of the present invention. Figure 1 Block diagram of a storage device.

[0011] Figure 3 The embodiment according to the present disclosure is shown in more detail. Figure 2 Figure 1 shows some configurations of .

[0012] Figure 4 The embodiment according to the present disclosure is shown in more detail. Figure 3 Figure 1 shows some configurations of .

[0013] Figure 5 is a diagram showing a method according to some embodiments Figure 1 The test device measures Figure 4 A method of including a resistor of an electric fuse in a memory cell is shown in FIG.

[0014] Figure 6 Is the description Figure 1 The test device measures Figure 4 A diagram of the measurement error when the resistance of an electric fuse is included in a memory cell.

[0015] Figure 7 is a diagram illustrating the operation of the test system according to an embodiment of the present disclosure.

[0016] Figure 8 is a diagram illustrating the operation of the test system according to an embodiment of the present disclosure.

[0017] Fig. 9 is a diagram illustrating the operation of a test system according to an embodiment of the present disclosure.

[0018] Fig.10 is a diagram illustrating the operation of the test system according to an embodiment of the present disclosure.

[0019] Fig.11It is shown that the Figure 4 Schematic diagram of the first bit line and test unit.

[0020] Fig. 12A and Fig. 12B The embodiment is shown in more detail Fig.11 A cross-sectional view of the connection relationship between the first bit line and the test unit.

[0021] Fig.13 It is shown Figure 1 Flowchart of the operation of the test apparatus.

[0022] Fig.14 The embodiment is shown in more detail Figure 2 Figure 1 shows some configurations of .

[0023] Fig.15 The embodiment according to the present disclosure is shown in more detail. Fig.14 Figure 1 shows some configurations of .

[0024] Fig.16 It shows that when according to Fig.14 FIG. 1 is a diagram of first to third current measurement methods when implementing a memory device according to an embodiment of the present invention.

[0025] Fig.17 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Block diagram of a storage device.

[0026] Fig.18 The embodiment according to the present disclosure includes Figure 1 A block diagram of a storage system of a storage device.

[0027] Fig.19 The embodiment according to the present disclosure is shown in more detail. Fig.18 Block diagram of a storage device.

[0028] Fig. 20 The embodiment according to the present disclosure is shown in more detail. Fig.19 Figure 1 shows some configurations of .

[0029] Fig.21 The embodiment according to the present disclosure is shown in more detail. Fig. 20 A circuit diagram of the configuration of one of the memory cells.

[0030] Fig. 22 is shown in more detail Fig. 20 Circuit diagram of the test unit configuration.

[0031] Fig.23 The embodiment according to the present disclosure is shown in more detail. Fig. 20 A circuit diagram of a configuration of one of the bit line selection switches. DETAILED DESCRIPTION

[0032] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. In the following description, only details such as detailed configuration and structure are provided to help overall understanding. Therefore, without departing from the technical concept and scope of the present disclosure, those skilled in the art may modify the embodiments described in this specification. In addition, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted. The configurations in the accompanying drawings or the following detailed description may be shown in the drawings or may be connected to other components other than the components described in the detailed description. The terms used here are defined in view of the functions of the present invention and are not limited to specific functions. The definition of terms may be determined based on the details described in the detailed description. The constituent elements described with reference to the terms such as units, drivers or blocks used in the detailed description may be implemented in software, hardware or a combination thereof. Exemplarily, the software may be machine code, firmware, embedded code and application software. For example, the hardware may include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive devices or a combination thereof.

[0033] Figure 1 is a block diagram showing a test system according to an embodiment of the present disclosure. Figure 1 , the test system TS may include a test device TD and a memory device 100 .

[0034] The memory device 100 may be, for example, a semiconductor chip or a semiconductor package, and may include a memory cell array 110. The memory cell array 110 may include a plurality of memory cells. Each of the plurality of memory cells may be an OTP memory cell implemented based on an electric fuse. In this case, each of the plurality of memory cells may store data based on whether the electric fuse is blown or the resistance value of the electric fuse.

[0035] For a more concise description, an embodiment in which the memory device 100 is an OTP memory device implemented based on an electric fuse will be representatively described below. However, the scope of the present disclosure is not limited thereto, and the memory device 100 may be any type of nonvolatile memory device.

[0036] The test device TD may control the memory device 100 by sending commands CMD and / or addresses ADDR to the memory device 100. Therefore, the test device TD may include logic and other circuits and may be a controller, processor, semiconductor chip, and / or other hardware-based device configured to perform testing of the memory device 100.

[0037] The test device TD may provide a test power supply voltage VDD_test to the memory device 100. The memory device 100 may perform an operation corresponding to a received command CMD and / or address ADDR based on the test power supply voltage VDD_test.

[0038] In an embodiment, the test power supply voltage VDD_test may have a voltage level low enough so that an electrical fuse included in a memory cell is not blown. For example, the test power supply voltage VDD_test may have a voltage level less than "1V".

[0039] In an embodiment, the test power supply voltage VDD_test may be about “0.1V”.

[0040] In an embodiment, the test power supply voltage VDD_test may be provided to the memory device 100 through a power supply pad (not shown). That is, the memory device 100 may receive the test power supply voltage VDD_test from the test device TD through the power supply pad (not shown).

[0041] The test device TD may measure the resistance value of the electric fuse included in each of the plurality of memory cells of the memory device 100. For example, the test device TD may sequentially activate each memory cell by sequentially providing an address ADDR to each of the plurality of memory cells. The test device TD may measure the magnitude of a current supplied to a power supply pad (not shown) of the memory device 100 in response to the activation of each memory cell. That is, the test device TD may measure the resistance value of the electric fuse included in each of the plurality of memory cells based on the magnitude of a current required to supply the test power supply voltage VDD_test to the memory device 100.

[0042] However, the resistance value of the electric fuse measured by the test device TD may contain an error. For example, the current provided to the power pad (not shown) measured by the test device TD may include errors due to various factors (such as leakage current, metal resistance, and transistor on-resistance in the memory device 100). Therefore, an error may occur between the resistance value of the electric fuse measured by the test device TD and the actual resistance value of the electric fuse. Hereinafter, the structure and operation of the test system TS that minimizes such measurement errors are described.

[0043] The memory device 100 may include a test cell array 120. The test cell array 120 may include a plurality of test cells. The test device TD may control the plurality of test cells by transmitting a command CMD and / or an address ADDR to the memory device 100.

[0044] The test device TD may control the test cell array 120 to more accurately measure the resistance value of the electric fuse included in each of the plurality of memory cells. For example, the test device TD may compensate the magnitude of the current measured when the memory cell is activated based on the magnitude of the current provided to the power supply pad (not shown) measured when the test cell is activated. In this case, since the resistance value of the electric fuse included in each of the plurality of memory cells may be measured more accurately, the test accuracy of the test device TD may be improved. The specific operation of the test device TD will be described in more detail with reference to the following drawings.

[0045] In an embodiment, each of the plurality of test cells does not include an electrical fuse. That is, each of the plurality of test cells may not store data. However, the scope of the present disclosure is not limited thereto. The construction of the test cells will be described in detail with reference to the following drawings.

[0046] Figure 2 is shown in more detail Figure 1 A block diagram of a memory device. Figure 1 and Figure 2 , the memory device 100 may include a memory cell array 110, a test cell array 120, a control logic circuit 130, a row decoder 140, a bit line selector 150, a switch controller 160, and a power supply pad (PSP).

[0047] The memory cell array 110 may include a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL extending in a row direction and a plurality of bit lines BL extending in a column direction.

[0048] The test cell array 120 may include a plurality of test cells. The plurality of test cells may be connected to a plurality of pseudo word lines DWL extending in the row direction and a plurality of bit lines BL extending in the column direction. The pseudo word lines DWL are considered "pseudo" lines because they are not connected to memory cells, and therefore they are not used to store data to the cells to which they are connected.

[0049] That is, the memory cell array 110 and the test cell array 120 may be connected to the same bit line. For example, the memory cell array 110 and the test cell array 120 may share a bit line. Figure 3 The detailed implementation methods of the memory cell array 110 and the test cell array 120 are described.

[0050] The control logic circuit 130 may control the overall operation of the memory device 100 based on the command CMD and the address ADDR provided from the test device TD. For example, the control logic circuit 130 may control the operations of the row decoder 140 and the switch controller 160 based on the command CMD and the address ADDR.

[0051] The row decoder 140 may control the plurality of word lines WL and the plurality of dummy word lines DWL based on the address ADDR. For example, the row decoder 140 may activate one of the plurality of word lines WL and the plurality of dummy word lines DWL based on the address ADDR.

[0052] The bit line selector 150 may be connected to the plurality of bit lines BL. The bit line selector 150 may receive a test power supply voltage VDD_test from the test device TD through the power supply pad PSP.

[0053] The bit line selector 150 may include a plurality of bit line selection switches (not shown), one end of each of which may receive the test power supply voltage VDD_test, and the other end of each of which may be connected to different bit lines.

[0054] The switch controller 160 may control the bit line selector 150 in response to the control of the control logic circuit 130. For example, the switch controller 160 may provide the bit line selector 150 with a column selection signal CSS created based on the address ADDR.

[0055] The bit line selector 150 may provide the test power supply voltage VDD_test to the bit line corresponding to the column selection signal CSS. For example, the bit line selector 150 may turn on the bit line selection switch (not shown) corresponding to the column selection signal CSS. In this case, the test power supply voltage VDD_test will be provided to the corresponding bit line.

[0056] Hereinafter, for a more concise description, the test operation of the internal resistance of the memory device 100 will be mainly described. Figures 18 to 22 Embodiments of performing read and write operations of the memory device 100 are described in detail.

[0057] Figure 3 is shown in more detail Figure 2 See some configuration diagrams for more information. Figures 1 to 3 , the memory cell array 110 may include a plurality of memory cells MC. The plurality of memory cells MC may be arranged along row directions and column directions to form a matrix structure.

[0058] A plurality of memory cells MC may be connected to the first word line WL1 to the nth word line WLn. A plurality of memory cells MC may be connected to the first bit line BL1 to the mth bit line BLm. Hereinafter, for a more concise description, a memory cell connected to the (i)th word line and the (j)th bit line will be referred to as a memory cell MCij. For example, a memory cell connected to the second word line WL2 and the first bit line BL1 will be referred to as a memory cell MC21. However, the scope of the present disclosure is not limited thereto.

[0059] Each of the plurality of memory cells MC may include an electrical fuse. Each of the plurality of memory cells MC may store data based on whether the electrical fuse is blown. Figure 4 A more detailed configuration of each of the plurality of memory cells MC is described in detail.

[0060] The test cell array 120 may include a plurality of test cells TC. The plurality of test cells TC may be arranged along row and column directions to form a matrix structure.

[0061] A plurality of test cells TC may be connected to a first pseudo word line DWL1 and a second pseudo word line DWL2. A plurality of test cells TC may be connected to a first bit line BL1 to an mth bit line BLm. Hereinafter, for a more concise description, a test cell connected to the (i)th pseudo word line and the (j)th bit line will be referred to as a test cell TCij. For example, a test cell connected to a first pseudo word line DWL1 and a second bit line BL2 will be referred to as a test cell TC12. However, the scope of the present disclosure is not limited thereto.

[0062] Each of the plurality of test cells TC may not include an electrical fuse. Figure 4 A more detailed configuration of each of the plurality of test cells TC is described in detail.

[0063] Hereinafter, for a more concise description, an embodiment in which the test cell array 120 is connected to two pseudo word lines (i.e., the first pseudo word line DWL1 and the second pseudo word line DWL2) will be representatively described. However, the scope of the present disclosure is not limited thereto. For example, the test cell array 120 may be configured to be connected to one pseudo word line. Figures 14 to 16 An embodiment in which the test cell array 120 is connected to a dummy word line is described in more detail.

[0064] The bit line selector 150 (also described as a bit line selector circuit) may include first to m-th bit line selection switches 151 to 15m. First ends of the first to m-th bit line selection switches 151 to 15m may be connected to the first to m-th bit lines BL1 to BLm, respectively. Second ends (i.e., opposite ends) of the first to m-th bit line selection switches 151 to 15m may be connected to the power rail PSR.

[0065] The bit line selector 150 may connect the corresponding bit line to the power rail PSR in response to the column selection signal CSS. For example, the first to mth bit line selection switches 151 to 15m may be turned on or off in response to different column selection signals, respectively.

[0066] As a more detailed example, the switch controller 160 may output a first column selection signal CSS1 for controlling the first bit line BL1 in response to an address ADDR corresponding to the first bit line BL1. In this case, the first bit line selection switch 151 may connect the first bit line BL1 to the power rail PSR in response to the first column selection signal CSS1. However, the scope of the present disclosure is not limited thereto.

[0067] The power rail PSR may be connected to the power pad PSP. The power rail PSR may receive a voltage of a constant level from the power pad PSP. For example, the voltage level of the power rail PSR may be maintained at a test power supply voltage VDD_test. However, the magnitude of the current flowing to the power rail PSR through the power pad PSP may be variable. For example, the magnitude of the current flowing through the power pad PSP to the power rail PSR may vary depending on which storage cell (or test cell) is activated.

[0068] To describe it more concisely, Figure 3 The embodiment in which the memory cell array 110 is disposed adjacent to the power rail PSR and the test cell array 120 is disposed spaced apart from the power rail PSR is shown, but the scope of the present disclosure is not limited thereto. That is, the scope of the present disclosure will not be limited to the location where the test cell array 120 is disposed.

[0069] Figure 4 is shown in more detail Figure 3 In the following, the connection to Figure 3 However, the scope of the present disclosure is not limited thereto, and memory cells and test cells connected to the second to m-th bit lines BL2 to BLm may also be similarly configured.

[0070] Reference Figures 1 to 4 The first bit line selection switch 151 may connect the power rail PSR and the first bit line BL1 in response to the first column selection signal CSS1. For example, the first bit line selection switch 151 may be turned on in response to the first column selection signal CSS1 having a logic high level.

[0071] Each of the memory cells MC11 to MCn1 connected to the first bit line BL1 may include an electric fuse EF and a programming transistor PTR. Each of the memory cells MC11 to MCn1 may operate in response to the voltage level of the connected word line. For example, the programming transistor PTR included in the memory cell MC11 may operate in response to the voltage level of the first word line WL1. That is, the gate terminal of the programming transistor PTR included in the memory cell MC11 may be connected to the first word line WL1.

[0072] The electric fuse EF and the programming transistor PTR included in each of the memory cells MC11 to MCn1 may be connected in series between the first bit line BL1 and the ground voltage. For example, the ground voltage may be supplied to a ground voltage node, which is configured to receive the ground voltage from outside the memory device or from inside the memory device. All conductive pads, lines or other elements (e.g., connection terminals) configured to be connected to the ground voltage may be included in the ground voltage node. For example, one end of the electric fuse EF included in the memory cell MC11 may be connected to the first bit line BL1, and the other end may be connected to the drain terminal of the programming transistor PTR. The source terminal of the programming transistor PTR included in the memory cell MC11 may be connected to the ground voltage. However, the scope of the present disclosure is not limited to the specific connection method of the electric fuse EF and the programming transistor PTR. For example, the electric fuse EF may be connected between the source terminal of the programming transistor PTR and the ground voltage. However, hereinafter, for a more concise description, an embodiment in which the electric fuse EF is connected between the bit line and the drain terminal of the programming transistor will be representatively described.

[0073] Each of the memory cells MC11 to MCn1 can store data based on whether the electric fuse EF is blown. For example, a memory cell including a blown electric fuse EF can store data corresponding to "1" or a logic high, while a memory cell including an unblown electric fuse EF can store data corresponding to "0" or a logic low. However, the scope of the present disclosure is not limited thereto.

[0074] In an embodiment, the resistance value of the blown electrical fuse EF may be about 50 ohms, and the resistance value of the unblown electrical fuse EF may be about 10000 ohms. However, the scope of the present disclosure is not limited thereto.

[0075] Each of the test cells TC11 to TC21 connected to the first bit line BL1 may include a test transistor TTR. For example, the test cell TC11 may include a first test transistor TTR1, and the test cell TC12 may include a second test transistor TTR2. Hereinafter, for a more concise description, the test cell TC11 may be referred to as a first test cell TC11, and the test cell TC12 may be referred to as a second test cell TC12.

[0076] In some embodiments, each of the first test cell TC11 and the second test cell TC21 does not include the electric fuse EF. Therefore, each of the first test cell TC11 to the second test cell TC21 may not store data.

[0077] The first test cell TC11 may operate based on a voltage level of the first dummy word line DWL1 For example, a gate terminal of the first test transistor TTR1 may be connected to the first dummy word line DWL1.

[0078] The first test transistor TTR1 may be connected between the first bit line BL1 and the ground voltage. In one embodiment, the drain terminal of the first test transistor TTR1 and the first bit line BL1 may be directly electrically connected. For example, the drain terminal of the first test transistor TTR1 and the first bit line BL1 may be electrically short-circuited. As used herein, a component described as "electrically connected" is configured so that an electrical signal can be transmitted from one component to another component (although such an electrical signal may be attenuated in intensity when it is transmitted and may be selectively transmitted). In addition, "directly electrically connected" components share a common electrical node through electrical connections of one or more conductors (e.g., wires, pads, internal wires, vias, etc.). Therefore, directly electrically connected components do not include components electrically connected through separate circuit elements such as resistors, capacitors, fuses, transistors, or diodes.

[0079] In an embodiment, the first test transistor TTR1 may be directly electrically connected between the first bit line BL1 and the ground voltage. For example, the first test cell TC11 may not include an electrical fuse, and the first test transistor TTR1 may be directly electrically connected to the first bit line BL1 through a conductor (e.g., through a wire). Fig. 12A An example connection method between the first test transistor TTR1 and the first bit line BL1 is described in detail.

[0080] The second test cell TC12 may operate based on the voltage level of the second dummy word line DWL2. For example, the gate terminal of the second test transistor TTR2 may be connected to the second dummy word line DWL2.

[0081] The drain terminal of the second test transistor TTR2 and the first bit line BL1 may not be electrically connected. In other words, the drain terminal of the second test transistor TTR2 and the first bit line BL1 may be electrically open or isolated from each other.

[0082] According to an embodiment of the present disclosure, the drain terminal of the first test transistor TTR1 and the first bit line BL1 may be short-circuited in a hard-coded scheme, and the drain terminal of the second test transistor TTR2 and the first bit line BL1 may be open-circuited in a hard-coded scheme. Fig.11 , Fig. 12A and Fig. 12B The specific implementation methods of the first test unit TC11 to the second test unit TC21 are described in more detail.

[0083] In an embodiment, when the first dummy word line DWL1 is activated, the magnitude of the current input to the power supply pad PSP may be determined based on the internal resistance of the first bit line selection switch 151 and the transistor on-resistance of the first test transistor TTR1 .

[0084] In an embodiment, when the second dummy word line DWL2 is activated, the magnitude of the current input to the power supply pad PSP may correspond to the magnitude of the leakage current flowing to the memory cell connected to the deactivated word line. Fig. 9 The magnitude of the current input to the power supply pad PSP when the second dummy word line DWL2 is activated is described in detail.

[0085] In an embodiment, the memory device 100 may be implemented such that the first column selection signal CSS1 indicates a logic high only when any word line or any dummy word line is activated. Figure 4 In the embodiment of the present invention, the operation of the second test transistor TTR2 does not affect the current or voltage of the first bit line BL1. That is, the second dummy word line DWL2 and the test cells TC21 to TC2m connected to the second dummy word line DWL2 may be provided to change the logic level of the column selection signal CSS. In this case, even if the first to nth word lines WL1 to WLn and the first dummy word line DWL1 are not activated, when the second dummy word line DWL2 is activated, the test power supply voltage VDD_test may be provided to the first bit line BL1.

[0086] In an embodiment, the test cell array 120 may include only the test cells (eg, test cells TC11 to TC1m) connected to the first dummy word line DWL1. That is, the test cell array 120 may not include the test cells connected to the second dummy word line DWL2. Figures 14 to 16 DETAILED DESCRIPTION An embodiment in which the test cell array 120 includes only test cells connected to the first dummy word line DWL1 is described.

[0087] Figure 5 is a diagram showing a practical embodiment Figure 1 The test device measures Figure 4 1. In the following, for a more concise description, the test apparatus TD measurement method is representatively described. Figure 4An embodiment of the resistance value of an electric fuse (hereinafter referred to as a target electric fuse EF_target) included in a memory cell MC11 of FIG. 1 is provided. Therefore, hereinafter, the memory cell MC11 (e.g., the memory cell being measured) may be referred to as a target memory cell, and the word line connected to the memory cell MC11 may be referred to as a target word line. On the contrary, memory cells other than the target may be referred to as non-target memory cells, and word lines other than the target word line may be referred to as non-target word lines. However, the scope of the present disclosure is not limited to the above example, and the resistance value of the electric fuse EF included in other memory cells may be measured in a similar manner.

[0088] The test device TD may provide an address ADDR of a target memory cell to the memory device 100. In this case, the memory device 100 may activate a word line and a bit line (e.g., a first word line WL1 and a first bit line BL1) connected to the target memory cell. For example, the row decoder 140 may provide a voltage corresponding to a logic high to the first word line WL1, and the switch controller 160 may provide a first column selection signal CSS1 indicating a logic high to the first bit line selection switch 141. In this case, word lines other than the word line connected to the target memory cell and bit lines other than the bit line connected to the target memory cell may be deactivated.

[0089] The programming transistor PTR connected to the activated word line (ie, the target word line) may be turned on. For example, the programming transistor PTR included in the memory cell MC11 may be turned on. In this case, the target electrical fuse EF_target included in the memory cell MC11 may be electrically connected to the ground voltage.

[0090] On the other hand, the programming transistor PTR connected to the deactivated word line (i.e., the non-target word line) may be turned off. For example, each programming transistor PTR included in the memory cells MC21 to MCn1 may be turned off. In this case, the electric fuse EF included in the memory cells MC21 to MCn1 may not be electrically connected to the ground voltage.

[0091] The test device TD may provide the test power supply voltage VDD_test to the power supply pad PSP. That is, the test device TD may maintain the power supply rail PSR at the test power supply voltage VDD_test through the power supply pad PSP.

[0092] The first bit line selection switch 151 may be turned on in response to the first column selection signal CSS1. In this case, the first bit line BL1 may be connected to the power rail PSR through the first bit line selection switch 151. Therefore, the voltage level of the first bit line BL1 may be determined according to the voltage level of the test power supply voltage VDD_test.

[0093] The test device TD may measure the magnitude of the current supplied to the power supply pad PSP. That is, the test device TD may measure the magnitude of the current supplied by the test device TD to the power supply pad PSP.

[0094] The magnitude of the current supplied from the test device TD to the power supply pad PSP may correspond to the magnitude of the current flowing from the first bit line BL1 to the target memory cell. Figure 5 In the embodiment, since the current does not flow from the first bit line BL1 to the non-target memory cell, the magnitude of the current flowing from the first bit line BL1 to the target memory cell may be equal to the magnitude of the current I_ideal supplied from the test device TD to the power pad PSP.

[0095] The test device TD may calculate the resistance value of the target electrical fuse EF_target based on the measured current. For example, the test device TD may calculate the resistance value of the target electrical fuse EF_target based on Equation 1 below.

[0096] [Equation 1]

[0097]

[0098] (However, R target can represent the resistance value of the target electrical fuse EF_target, VDD_test can represent the voltage level of the test power supply voltage VDD_test, I ideal Can be expressed according to Figure 5 The magnitude of the current measured by the embodiment. )

[0099] However, when the memory device 100 is implemented in a non-ideal manner, the resistance value of the target electric fuse EF_target calculated by the test device TD based on the above equation 1 may include a measurement error. Figure 6 The measurement error of the calculated resistance value is described in more detail.

[0100] Figure 6 Is the description Figure 1 The test device measures Figure 4 A diagram showing the measurement error when the resistance of an electric fuse is included in a memory cell. Figures 1 to 6 , the memory device 100 may activate the word line and the bit line (e.g., the first word line WL1 and the first bit line BL1) connected to the target memory cell. For example, the row decoder 140 may provide a voltage corresponding to a logic high to the first word line WL1, and the switch controller 160 may provide the first column selection signal CSS1 indicating a logic high to the first bit line selection switch 151. In this case, the word lines other than the word line connected to the target memory cell and the bit lines other than the bit line connected to the target memory cell may be deactivated. Hereinafter, the description will be mainly made with reference to Figure 5 Describes the difference between the resistance value of an ideal memory device and the measured value.

[0101] The first bit line selection switch 151 may include an internal resistance component. For example, even if the first bit line selection switch 151 is turned on in response to the first column selection signal CSS1, the resistance of the first bit line selection switch 151 may be greater than "0". That is, even if the first bit line selection switch 151 is turned on in response to the first column selection signal CSS1, the bit line selection switch resistance R_BSS component may be included between the first bit line BL1 and the power rail PSR. In this case, the bit line selection switch resistance R_BSS component may be included between the first bit line BL1 and the power rail PSR. Figure 5 Different from the description above, the voltage level of the first bit line BL1 may be different from the voltage level of the power rail PSR.

[0102] In an embodiment, the size of the bit line selection switch resistance R_BSS may be determined based on a transistor on-resistance of a transistor included in the first bit line selection switch 151. However, the scope of the present disclosure is not limited thereto.

[0103] The programming transistor PTR included in the target memory cell may include an internal resistance component. For example, even if the programming transistor PTR included in the target memory cell is turned on, the resistance of the programming transistor PTR may be "0". In this case, Figure 5 Different from the description above, a programming transistor on-resistance R_PTR component may also be included between the target electrical fuse EF_target and the ground voltage.

[0104] A leakage current may occur from the first bit line BL1 to the non-target memory cell. For example, even if the programming transistor PTR included in the non-target memory cell is turned off, the leakage current may occur in a direction from the drain terminal to the source terminal of the programming transistor PTR included in the non-target memory cell. In this case, the magnitude of the current I_reality measured by the test device TD may be different from the magnitude of the current flowing through the target electrical fuse EF_target.

[0105] Therefore, a measurement error may occur in the resistance value of the target electric fuse EF_target calculated by the test device TD based on the current I_reality. Hereinafter, an operation of the test system TS for compensating for the measurement error will be described in detail.

[0106] Figure 7 is a diagram showing the operation of the test system according to an embodiment of the present disclosure. Figure 5 and Figure 6 Described Operation Similarly, the operation of the test system TS in the case where the memory cell MC11 is the target memory cell is representatively described.

[0107] Reference Figures 1 to 4 and Figure 7 , the test device TD may provide the address ADDR of the target memory cell to the memory device 100. For example, the test device TD may provide the address of the memory cell MC11 to the memory device 100. In this case, the memory device 100 may activate the first bit line BL1 and the first word line WL1. For example, the memory device 100 may turn on the first bit line selection switch 151 and may provide a voltage corresponding to a logic high to the first word line WL1.

[0108] Hereinafter, for a more concise description, in response to activation of the first bit line BL1 and the first word line WL1, the current flowing from the first bit line BL1 to the target memory cell will be referred to as the measurement target current MTC, and the current flowing from the first bit line BL1 to the memory cell (e.g., non-target memory cell) connected to the deactivated word line will be referred to as the leakage current ILK. However, the scope of the present disclosure is not limited to these terms.

[0109] The test device TD can measure the current (hereinafter referred to as the first current IA) supplied to the power supply pad PSP in response to the activation of the first bit line BL1 and the first word line WL1. In this case, the magnitude of the first current IA may correspond to the sum of the magnitude of the measurement target current MTC and the magnitude of the leakage current ILK. Although a single value of the leakage current ILK is given in various embodiments and discussions herein, it can be seen from the figure that multiple leakage currents ILK may appear for different unactivated word lines, which together result in the leakage current discussed in various embodiments where only one current is mentioned.

[0110] The measurement target current MTC may refer to a current flowing to the target memory cell through the power pad PSP and the first bit line selection switch 151. In this case, the magnitude of the measurement target current MTC may vary based on the resistance value of the target electrical fuse EF_target and the bit line selection switch resistance R_BSS and the programming transistor on-resistance R_PTR.

[0111] Therefore, when the resistance value of the target electrical fuse EF_target is calculated based on the magnitude of the first current IA, the above reference Figure 6 Similar to the description, the calculated resistance value may include the bit line selection switch resistance R_BSS and the programming transistor on-resistance R_PTR, and may be affected by the leakage current ILK. Figures 8 to 10 Describe the specific method used to compensate for this error.

[0112] Figure 8 is a diagram illustrating the operation of a test system according to an embodiment of the present disclosure. Figures 1 to 4 and Figures 7 and 8, the test device TD may provide the address ADDR of the first test cell TC11 to the memory device 100. In this case, the memory device 100 may activate the first bit line BL1 and the first dummy word line DWL1. For example, the row decoder 140 may provide a voltage corresponding to a logic high to the first dummy word line DWL1, and the switch controller 160 may turn on the first bit line selection switch 141.

[0113] Hereinafter, for a more concise description, a current flowing from the first bit line BL1 to the first test cell TC11 in response to activation of the first bit line BL1 and the first dummy word line DWL1 will be referred to as a test cell current TCC.

[0114] In response to the activation of the first bit line BL1 and the first dummy word line DWL1, the test device TD can measure the current (hereinafter, referred to as the second current IB) supplied to the power supply pad PSP. In this case, the magnitude of the second current IB may correspond to the sum of the magnitude of the test cell current TCC and the magnitude of the leakage current ILK.

[0115] The test cell current TCC may refer to a current flowing to the test cell TC11 through the power pad PSP and the first bit line selection switch 151. In this case, the magnitude of the test cell current TCC will vary based on the components of the bit line selection switch resistance R_BSS and the test transistor on-resistance R_TTR.

[0116] The size of the test transistor TTR1 may correspond to the size of the programming transistor PTR. For example, the size of the test transistor TTR1 may be the same as the size of the programming transistor PTR. In this case, the size of the test transistor on-resistance R_TTR may correspond to the size of the programming transistor on-resistance R_PTR.

[0117] Fig. 9 is a diagram illustrating the operation of a test system according to an embodiment of the present disclosure. Figures 1 to 4 and Figures 7 to 9 , the test device TD may provide the address ADDR of the second test cell TC12 to the memory device 100. In this case, the memory device 100 may activate the first bit line BL1 and the second dummy word line DWL2. For example, the row decoder 140 may provide a voltage corresponding to a logic high to the second dummy word line DWL2, and the switch controller 160 may turn on the first bit line selection switch 141.

[0118] The second test transistor TTR2 connected to the second dummy word line DWL2 may not be electrically connected to the first bit line BL1. Therefore, even when a voltage corresponding to a logic high is applied to the second dummy word line DWL2, the magnitude of the current flowing from the first bit line BL1 to the second test cell TC21 may be "0".

[0119] In response to the activation of the first bit line BL1 and the second dummy word line DWL2, the test device TD may measure the current (hereinafter referred to as the third current IC) supplied to the power supply pad PSP. In this case, the magnitude of the third current IC may correspond to the sum of the leakage currents ILK. That is, the third current IC may correspond to the sum of the currents flowing in the memory cells (i.e., non-target memory cells) connected to the deactivated word lines.

[0120] Fig.10 is a diagram illustrating the operation of a test system according to an embodiment of the present disclosure. Figures 1 to 4 as well as Figures 7 to 10 , when measuring the first current IA, a voltage corresponding to a logic high may be provided to a target word line (e.g., the first word line WL1). Conversely, a voltage corresponding to a logic low may be provided to non-target word lines (e.g., the second to nth word lines WL2 to WLn) and the first to second dummy word lines DWL1 to DWL2.

[0121] When measuring the second current IB, a voltage corresponding to logic high may be provided to the first pseudo word line DWL1. Conversely, a voltage corresponding to logic low may be provided to all word lines (ie, the first to nth word lines WL1 to WLn) connected to the memory cell array 110 and the second pseudo word line DWL2.

[0122] When measuring the third current IC, a voltage corresponding to logic high may be provided to the second pseudo word line DWL2. Conversely, a voltage corresponding to logic low may be provided to all word lines (ie, first to nth word lines WL1 to WLn) connected to the memory cell array 110 and the first pseudo word line DWL1.

[0123] The test device TD may calculate the resistance value of the target electrical fuse EF_target based on the first current IA, the second current IB and the third current IC. For example, the test device TD may perform a compensation calculation operation on the first current IA based on the second current IB and the third current IC to calculate the resistance value of the target electrical fuse EF_target.

[0124] The difference between the first current IA and the third current IC may correspond to the measurement target current MTC. Therefore, the measurement target current MTC may be calculated based on Equation 2 below.

[0125] [Equation 2]

[0126]

[0127] Here, I MTC It can represent the size of the measured target current MTC, I AIt can represent the magnitude of the first current IA, I C can represent the magnitude of the third current IC, VDD_test can represent the voltage level of the test power supply voltage VDD_test, R target It can represent the resistance value of the target electrical fuse EF_target, R BSS It can represent the size of the bit line selection switch resistance R_BSS, and R PTR It can represent the size of the programming transistor on-resistance R_PTR.

[0128] Similarly, the difference between the second current IB and the third current IC may correspond to the test cell current TCC. Therefore, the test cell current TCC may be calculated based on Equation 3 below.

[0129] [Equation 3]

[0130]

[0131] Here, I TCC Indicates the size of the test unit current TCC, I B Indicates the magnitude of the second current IB, I C represents the magnitude of the third current IC, VDD_test represents the voltage level of the test power supply voltage VDD_test, R BSS Indicates the size of the bit line selection switch resistance R_BSS, R TTR Indicates the size of the test transistor on-resistance R_TTR.

[0132] The size of the first test transistor TTR1 may be the same as the size of the programming transistor PTR. In this case, the size of the test transistor on-resistance R_TTR may be the same as the size of the programming transistor on-resistance R_PTR. That is, R in the above equation 2 PTR can have the same size as in Equation 3.

[0133] Therefore, the test device TD may calculate the resistance value of the target electric fuse EF_target based on the above Equation 2 and Equation 3. For example, the test device TD may calculate the resistance value of the target electric fuse EF_target based on the following Equation 4.

[0134] [Equation 4]

[0135]

[0136] That is, according to Equation 4, the error of the resistance value of the target electrical fuse EF_target caused by the bit line selection switch resistance R_BSS, the programming transistor on-resistance R_PTR, and the leakage current ILK can be compensated. Therefore, according to the embodiment of the present disclosure, since the resistance value of the target electrical fuse EF_target can be measured more accurately, the test operation of the memory device 100 can be performed more accurately.

[0137] Fig.11 It is shown that the Figure 4 Schematic diagram of the first bit line and test unit. Figures 1 to 4 and Fig.11 , the first bit line BL1 may be connected to the first bit line contact BLCT1 and the second bit line contact BLCT2 through the via VIA.

[0138] The test cell TC11 may include a first test transistor TTR1. A drain terminal of the first test transistor TTR1 may be connected to a first drain contact DCT1 through a via VIA. A source terminal of the first test transistor TTR1 may be connected to a ground voltage.

[0139] The test cell TC21 may include a second test transistor TTR2. A drain terminal of the second test transistor TTR2 may be connected to a second drain contact DCT2 through a via VIA. A source terminal of the second test transistor TTR2 may be connected to a ground voltage.

[0140] The first conductor CDU1 may be connected to the first bit line contact BLCT1 and the first drain contact DCT1 through the via VIA. That is, the first bit line BL1 and the drain terminal of the first test transistor TTR1 may be electrically connected to each other through the first bit line contact BLCT1, the first conductor CDU1, and the first drain contact DCT1. Fig. 12A A connection relationship between the first bit line BL1 and the drain terminal of the first test transistor TTR1 is described in detail.

[0141] In contrast, the second conductor CDU2 may not be electrically connected to the second bit line contact BLCT2 and the second drain contact DCT2. That is, the drain terminals of the first bit line BL1 and the second test transistor TTR2 may not be electrically connected to each other. Fig. 12B A connection relationship between the first bit line BL1 and the drain terminal of the second test transistor TTR2 is described in detail.

[0142] In an embodiment, the first conductor CDU1 and the second conductor CDU2 may be disposed at positions corresponding to the plurality of electrical fuses EF included in the memory cell array 110. For example, the relative position of the first conductor CDU1 relative to the first bit line BL1 and the first test transistor TTR1 may correspond to the relative position of the electrical fuse EF included in the memory cell MC11 relative to the first bit line BL1 and the programming transistor PTR. In this case, the production process of the memory device 100 may be further simplified. However, the scope of the present disclosure is not limited to the specific implementation method of the first conductor CDU1 and the second conductor CDU2.

[0143] Fig. 12A and Fig. 12B The embodiment is shown in more detail Fig.11 A cross-sectional view of the connection relationship between the first bit line and the test unit. Fig. 12A Description Fig.11 A cross-sectional view of the memory device 100 taken along the line AA' in the substrate direction, and referring to Fig. 12B Description Fig.11 A cross-sectional view of the memory device 100 taken along the substrate direction along the line BB′.

[0144] Reference Fig. 12A , a first metal layer MLa, a second metal layer MLb, and a third metal layer MLc may be stacked on a substrate SUB of the memory device 100. An interlayer insulating layer ISL may be formed between the first metal layer MLa, the second metal layer MLb, and the third metal layer MLc.

[0145] In embodiments, the interlayer insulating layer ISL may include or be formed of an insulating material such as silicon oxide or silicon nitride.

[0146] In embodiments, the first metal layer MLa, the second metal layer MLb, and the third metal layer MLc may include or be formed of a metal, a metal compound, or a conductive material such as polysilicon.

[0147] The first metal layer MLa may form a first conductor CDU1. The second metal layer MLb may form a first bit line contact BLCT1 and a first drain contact DCT1. The third metal layer MLc may form a first bit line BL1.

[0148] The first metal layer MLa and the second metal layer MLb may be connected through the first via VIAa. For example, the first metal layer MLa may be electrically connected to a region where a first bit line contact BLCT1 of the second metal layer MLb is formed and may be electrically connected to a region where a first drain contact DCT1 of the second metal layer MLb is formed through the first via VIAa.

[0149] The second metal layer MLb may be connected to the active area ACT on the substrate SUB through the second via VIAb. More specifically, the area of ​​the second metal layer MLb where the first drain contact DCT1 is formed may be connected to the active area ACT through the second via VIAb. The active area ACT may form a drain terminal of the first test transistor TTR1.

[0150] The second metal layer MLb and the third metal layer MLc may be connected through the third via VIAc. More specifically, a region of the second metal layer MLb where the first bit line contact BLCT1 is formed may be connected to the third metal layer MLc through the third via VIAc.

[0151] according to Fig. 12A In an embodiment of the present invention, the first bit line BL1 may be electrically connected to the drain terminal of the first test transistor TTR1 (eg, it may be directly electrically connected to the drain terminal).

[0152] To describe it more concisely, Fig. 12A An embodiment is shown in which the first bit line contact BLCT1 and the first drain contact DCT1 are formed on the same metal layer, and the first conductor CDU1 is disposed on a metal layer adjacent to the substrate SUB. However, the scope of the present disclosure is not limited to a specific method of forming the first bit line contact BLCT1, the first conductor CDU1, the first drain contact DCT1, and the first bit line BL1.

[0153] Reference Fig. 12B , a first metal layer MLa, a second metal layer MLb, and a third metal layer MLc may be stacked on a substrate of the memory device 100. An interlayer insulating layer ISL may be formed between the first metal layer MLa, the second metal layer MLb, and the third metal layer MLc.

[0154] The first metal layer MLa may form a second conductor CDU2. The second metal layer MLb may form a second bit line contact BLCT2 and a second drain contact DCT2. The third metal layer MLc may form a first bit line BL1.

[0155] The second metal layer MLb can be connected to the active area ACT on the substrate SUB through the second via VIAb. The second metal layer MLb and the third metal layer MLc can be connected through the third via VIAc. Fig. 12A The descriptions are similar, so their detailed descriptions will be omitted.

[0156] The first metal layer MLa and the second metal layer MLb may not be electrically connected. For example, no via hole may be formed between the first metal layer MLa and the second metal layer MLb. Fig. 12ADifferent from the related description, the first metal layer MLa and the second metal layer MLb may be separated and electrically isolated by the interlayer insulating layer ISL.

[0157] Therefore, according to Fig. 12B In the embodiment of the present invention, the first bit line BL1 may not be electrically connected to the drain terminal of the second test transistor TTR2. In this case, even if the voltage level supplied to the gate terminal of the second test transistor TTR2 is different, current does not flow from the first bit line BL1 to the drain terminal of the second test transistor TTR2.

[0158] In an embodiment, the first conductor CDU1 and the second conductor CDU2 may be formed at the same layer as the electric fuse EF included in the memory cell array 110. For example, the electric fuse EF may be formed at the first metal layer MLa. However, the scope of the present disclosure is not limited to the method of forming the first conductor CDU1, the second conductor CDU2, and the electric fuse EF. Fig. 12A and Fig. 12B Unlike those shown, the first conductor CDU1 , the second conductor CDU2 , and the electric fuse EF may be formed on the substrate SUB.

[0159] For a more concise description, Fig. 12B , an embodiment in which no via is formed between the first metal layer MLa and the second metal layer MLb is representatively shown, but the scope of the present disclosure is not limited thereto. For example, a via may be formed between the second conductor CDU2 and the first bit line contact BLCT1, but a via may not be formed between the second conductor CDU2 and the first drain contact DCT1. Alternatively, a via may not be formed between the second conductor CDU2 and the first bit line contact BLCT1, but a via may be formed between the second conductor CDU2 and the first drain contact DCT1. For another example, the second test unit TC12 may not include the second conductor CDU2. Even in these cases, the drain terminals of the first bit line BL1 and the second test transistor TTR2 may not be electrically connected. That is, the scope of the present disclosure is not limited to the specific method of electrically separating the drain terminals of the first bit line BL1 and the second test transistor TTR2.

[0160] Fig.13 Yes means Figure 1 Flow chart of the operation of the test device. Figures 1 to 12B In step S110, the test device TD can measure the first current IA. Figure 7 Similar to the description, the test device TD may provide the address ADDR of the target memory cell to the memory device 100 and measure the magnitude of the current provided to the power supply pad PSP.

[0161] In step S120, the test device TD can measure the second current IB. Figure 8 Similar to the description, the test device TD may provide the address ADDR of the first test cell TC11 to the memory device 100 and measure the magnitude of the current provided to the power supply pad PSP.

[0162] In step S130, the test device TD can measure the third current IC. Figure 8 Similar to the description, the test device TD may provide the address ADDR of the second test cell TC21 to the memory device 100 and measure the magnitude of the current provided to the power supply pad PSP.

[0163] In step S140, the test device TD may calculate the resistance value of the electric fuse (ie, the target electric fuse EF_target) included in the target memory cell based on the first current IA to the third current IC. For example, the test device TD may calculate the resistance value of the target electric fuse EF_target based on Equation 4 described above.

[0164] In an embodiment, the order of the above steps S110 to S130 may be different. Fig.13 Different from the illustration, step S130 may be performed before step S110 and / or step S120, or step S120 may be performed before step S110. That is, the scope of the present disclosure will not be limited to the execution order of steps S110 to S130.

[0165] Fig.14 The embodiment is shown in more detail Figure 2 See some configuration diagrams for more information. Figure 1 , Figure 2 and Fig.14 , the memory cell array 110 may include a plurality of memory cells MC. The plurality of memory cells MC may be connected to the first bit line BL1 to the mth bit line BLm. The first bit line BL1 to the mth bit line BLm may be connected to the bit line selector 150. Since the configuration and function of the memory cell array 110 and the bit line selector 150 are similar to those of the previous reference Figure 3 The descriptions are similar, so their detailed descriptions will be omitted.

[0166] The test cell array 120 may include a plurality of test cells TC. Each of the plurality of test cells TC may be connected to the first dummy word line DWL1. For example, the test cell array 120 may include test cells TC11 to TC1m. That is, Figure 3 Different from the description above, each of the test cells TC included in the test cell array 120 may be connected to one dummy word line.

[0167] Fig.15 is shown in more detail Fig.14 See some configuration diagrams for more information. Figure 1 , Figure 2 , Fig.14 and Fig.15 , the memory cells MC11 to MCn1 and the test cell TC11 may be connected to the first bit line BL1. Since the configuration and operation of the memory cells MC11 to MCn1 and the test cell TC11 are similar to those of the reference Figure 4 The descriptions are similar, so their detailed descriptions will be omitted.

[0168] Fig.16 It shows that when according to Fig.14 FIG. 1 is a diagram of first to third current measurement methods when implementing a memory device according to an embodiment of the present invention.

[0169] Reference Figure 1 , Figure 2 as well as Figures 14 to 16 , when measuring the first current IA, a voltage corresponding to a logic high may be provided to a target word line (e.g., the first word line WL1). On the other hand, a voltage corresponding to a logic low may be applied to non-target word lines (e.g., the second word line WL2 to the nth word line WLn) and the first dummy word line DWL1.

[0170] When measuring the second current IB, a voltage corresponding to logic high may be provided to the first dummy word line DWL1. On the other hand, a voltage corresponding to logic low may be applied to all word lines connected to the memory cell array 110 (ie, the first to nth word lines WL1 to WLn).

[0171] When measuring the third current IC, a voltage corresponding to logic low may be applied to all word lines and the first dummy word line DWL1 connected to the memory cell array 110. That is, when measuring the third current IC, only the first bit line BL1 may be activated. The third current IC may correspond to a leakage current occurring due to activation of the first bit line BL1.

[0172] Since the method in which the test device TD calculates the resistance value of the electric fuse included in the target memory cell based on the first current IA to the third current IC is the same as that described above with reference to Figures 1 to 10 The methods described are similar, so a detailed description will be omitted.

[0173] Fig.17 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A block diagram of a memory device. Figure 1 , Figure 2 and Fig.17, the memory device 100 may include a control logic circuit 130, a row decoder 140, a bit line selector 150, a switch controller 160, and a power supply pad PSP. Since the configuration and function of the control logic circuit 130, the row decoder 140, the bit line selector 150, the switch controller 160, and the power supply pad PSP are the same as those described above with reference to Figure 2 The descriptions are similar, so their detailed descriptions will be omitted.

[0174] The memory device 100 may include a plurality of memory cell arrays. For example, the memory device 100 may include a first memory cell array 110a and a second memory cell array 110b.

[0175] The memory device 100 may include a plurality of test cell arrays. For example, the memory device 100 may include a first test cell array 120a and a second test cell array 120b.

[0176] Hereinafter, for a more concise description, an embodiment in which the memory device 100 includes two memory cell arrays and two test cell arrays will be described. However, the scope of the present disclosure is not limited to the number of memory cell arrays and test cell arrays included in the memory device 100.

[0177] The first memory cell array 110a may be connected to the first word line WLa. The second memory cell array 110b may be connected to the second word line WLb. That is, the first memory cell array 110a and the second memory cell array 110b may be connected to different word lines.

[0178] The first test cell array 120a may be connected to the first dummy word line DWLa. The second test cell array 120b may be connected to the second dummy word line DWLb. That is, the first test cell array 120a and the second test cell array 120b may be connected to different dummy word lines.

[0179] When the target memory cell is included in the first memory cell array 110a, the test device TD may measure the second to third currents IB to IC using the first test cell array 120a. For example, the test device TD may sequentially activate the first dummy word line DWLa to measure the second to third currents IB to IC.

[0180] Similarly, when the target memory cell is included in the second memory cell array 110b, the test device TD may use the second test cell array 120b to measure the second to third currents IB to IC. For example, the test device TD may sequentially activate the second dummy word line DWLb to measure the second to third currents IB to IC.

[0181] The first test cell array 120a may be disposed adjacent to the first memory cell array 110a. The second test cell array 120b may be disposed adjacent to the second memory cell array 110b. In this case, the distance between the target memory cell and the test cell may be minimized. Fig.17 According to an embodiment of the present invention, an error in the resistance value of the target electrical fuse calculated by the test device TD that may be caused by the parasitic resistance of the bit line between the target memory cell and the test cell may be minimized.

[0182] Fig.18 It is shown that Figure 1 A block diagram of a storage system of a storage device. Figures 1 to 18 , the memory system MS may include a memory device 100 and a memory controller CTR.

[0183] The storage controller CTR may be one of various types of processors, such as a central processing unit (CPU) and a graphics processing unit (GPU).

[0184] The memory device 100 may include a plurality of memory cells MC. The memory controller CTR may write data DATA to the plurality of memory cells MC or read data DATA from the plurality of memory cells MC. For example, the memory controller CTR may control the memory device 100 by sending a command CMD and / or an address ADDR to the memory device 100.

[0185] The memory controller CTR may provide a driving power supply voltage VDD_op to the memory device 100. The memory device 100 may perform an operation corresponding to the received command CMD and / or address ADDR based on the driving power supply voltage VDD_op. For example, the memory controller CTR may perform a programming operation on the memory device 100 based on the driving power supply voltage VDD_op.

[0186] In an embodiment, when a program operation of the memory device 100 is performed, the driving power supply voltage VDD_op may have a higher voltage level than the test power supply voltage VDD_test.

[0187] In an embodiment, when the memory controller CTR performs a programming operation on the memory device 100, the driving power supply voltage VDD_op may have a voltage level of about 1.5V to 1.8V. However, the scope of the present disclosure is not limited to the voltage level of the driving power supply voltage VDD_op. For example, when the memory controller CTR performs a programming operation on the memory device 100, the voltage level of the driving power supply voltage VDD_op may be about 5V.

[0188] In an embodiment, the driving power supply voltage VDD_op and the test power supply voltage VDD_test may be provided to the memory device 100 through the same pad. That is, the memory device 100 may receive the test power supply voltage VDD_test from the test device TD or the driving power supply voltage VDD_op from the memory controller CTR through one power supply pad PSP.

[0189] Fig.19 is shown in more detail Fig.18 A block diagram of a memory device. Figures 1 to 19 , the memory device 100 may include a memory cell array 110, a test cell array 120, a control logic circuit 130, a row decoder 140, a bit line selector 150, a switch controller 160, a sense amplifier 170, an input / output circuit 180, and a power supply pad PSP. A detailed description of the above-mentioned memory cell array 110, the test cell array 120, the control logic circuit 130, the row decoder 140, the bit line selector 150, and the switch controller 160 is omitted.

[0190] The memory cell array 110 may include a plurality of memory cells. The plurality of memory cells may be connected to a plurality of program word lines PWL and a plurality of read word lines RWL extending in a row direction. The plurality of memory cells may be connected to a plurality of bit lines BL and a plurality of sense lines SL extending in a column direction.

[0191] In an embodiment, the plurality of programming word lines PWL may correspond to the previously referenced Figures 1 to 17 However, the scope of the present disclosure is not limited thereto.

[0192] The test cell array 120 may include a plurality of test cells. The plurality of test cells may be connected to a plurality of pseudo program word lines DPWL extending in a row direction and a plurality of pseudo read word lines DRWL. The plurality of test cells may be connected to a plurality of bit lines BL extending in a column direction and a plurality of sense lines SL.

[0193] In an embodiment, the plurality of dummy programming word lines DPWL may correspond to the previously referenced Figures 1 to 17 However, the scope of the present disclosure is not limited thereto.

[0194] Since reference has been made Figure 3 A detailed implementation method of the memory cell array 110 and the test cell array 120 connected to the bit lines BL is described, and thus a detailed description thereof will be omitted.

[0195] The memory cell array 110 and the test cell array 120 may be connected to the same sensing line SL. For example, the memory cell array 110 and the test cell array 120 may share the sensing line SL. Fig. 20A detailed implementation method of the memory cell array 110 and the test cell array 120 connected to the sensing line SL is described.

[0196] The control logic circuit 130 may control the overall operation of the memory device 100 based on the command CMD and the address ADDR provided from the memory controller CTR. For example, the control logic circuit 130 may control the operations of the row decoder 140, the switch controller 160, the sense amplifier 170, and the input / output circuit 180 based on the command CMD and the address ADDR.

[0197] The row decoder 140 may control a plurality of programming word lines PWL, a plurality of read word lines RWL, a plurality of pseudo programming word lines DPWL, and a plurality of pseudo read word lines DRWL based on the address ADDR. For example, the row decoder 140 may activate a plurality of programming word lines PWL, a plurality of read word lines RWL, a plurality of pseudo programming word lines DPWL, and a plurality of pseudo read word lines DRWL based on the address ADDR.

[0198] The bit line selector 150 may be connected to the plurality of bit lines BL. The bit line selector 150 may receive a driving power supply voltage VDD_op from the memory controller CTR through a power supply pad PSP.

[0199] The sense amplifier 170 may be connected to the memory cell array 110 through a plurality of sensing lines SL. The sense amplifier 170 may sense voltage level changes of the plurality of sensing lines SL and temporarily store data of the memory cell array 110. For example, the sense amplifier 170 may store data of memory cells connected to an activated word line.

[0200] The input / output circuit 180 may receive data from the memory controller CTR or transmit data to the memory controller CTR. For example, the input / output circuit 180 may write the received data into the memory cell array 110 or output the data stored in the sense amplifier 170 to the memory controller CTR.

[0201] Fig. 20 is shown in more detail Fig.19 See some configuration diagrams for more information. Figures 1 to 3 , the memory cell array 110 may include a plurality of memory cells MC. The test cell array 120 may include a plurality of test cells TC.

[0202] Since the configuration of the power supply pad PSP and the bit line selector 150 is the same as that of the above reference Figure 3 The descriptions are similar, so their detailed descriptions will be omitted.

[0203] A plurality of memory cells MC may be connected to the first programming word line PWL1 to the nth programming word line PWLn. A plurality of memory cells MC may be connected to the first read word line RWL1 to the nth read word line RWLn. A plurality of memory cells MC may be connected to the first bit line BL1 to the mth bit line BLm. A plurality of memory cells MC may be connected to the first sensing line SL1 to the mth sensing line SLm. Hereinafter, for a more concise description, a memory cell connected to the (i)th programming word line, the (i)th read word line, the (j)th bit line, and the (j)th sensing line is referred to as a memory cell MCij.

[0204] A plurality of test cells TC may be connected to first to second dummy program word lines DPWL1 to DPWLn. A plurality of test cells TC may be connected to first to second dummy read word lines DRWL1 to DRWL2.

[0205] A plurality of test cells TC may be connected to the first to mth bit lines BL1 to BLm. A plurality of test cells TC may be connected to the first to mth sensing lines SL1 to SLm. Hereinafter, for a more concise description, a test cell connected to the (i)th programming word line, the (i)th reading word line, the (j)th bit line, and the (j)th sensing line is referred to as a test cell TCij.

[0206] Hereinafter, for a more concise description, an embodiment in which the test cell array 120 is connected to the first to second pseudo programming word lines DPWL1 to DPWLn and the first to second pseudo reading word lines DRWL1 to DRWL2 will be representatively described. However, the scope of the present disclosure is not limited thereto. For example, Fig. 20 Unlike shown, the test cell array 120 may not be connected to the first to second dummy read word lines DRWL1 to DRWL2 .

[0207] Fig.21 is shown in more detail Fig. 20 A circuit diagram of a configuration of one of the storage cells of FIG. Fig.21 Representative description Fig. 20 However, the scope of the present disclosure is not limited thereto, and each of the plurality of memory cells MC may be configured similarly to the memory cell MC11.

[0208] Reference Figures 1 to 21 , the memory cell MC11 may include an electric fuse EF, a programming transistor PTR, and a reading transistor RTR. Since the functions and operations of the electric fuse EF and the programming transistor PTR are the same as those of the above reference Figures 1 to 17 The descriptions are similar, so the detailed description will be omitted.

[0209] The memory cell MC11 may be connected to a first bit line BL1 , a first sensing line SL1 , a first program word line PWL1 , and a first read word line RWL1 .

[0210] The electric fuse EF may be connected between the first bit line BL1 and the middle node IMN. The programming transistor PTR may be connected between the middle node IMN and the ground voltage. The reading transistor RTR may be connected between the middle node IMN and the first sensing line SL1.

[0211] The program transistor PTR may operate in response to a voltage level of the first program word line PWL1. The read transistor RTR may operate in response to a voltage level of the first read word line RWL1.

[0212] When the electric fuse EF is blown, even if a voltage corresponding to a logic high is applied to the first read word line RWL1, current does not flow from the first bit line BL1 to the first sense line SL1. In this case, the sense amplifier 170 can determine that the memory cell MC11 stores data corresponding to "1". However, the scope of the present disclosure is not limited thereto.

[0213] When the electric fuse EF is not blown, the read transistor RTR may be turned on in response to a voltage corresponding to a logic high being applied to the first read word line RWL1. Therefore, current may flow from the first bit line BL1 to the first sense line SL1. In this case, the sense amplifier 170 may determine that the memory cell MC11 stores data corresponding to "0". However, the scope of the present disclosure is not limited thereto.

[0214] Fig. 22 is shown in more detail Fig. 20 Hereinafter, reference will be made to the circuit diagram of the configuration of the test unit. Fig. 22 Representative description Fig. 20 However, the scope of the present disclosure is not limited thereto, and each of the plurality of test cells TC may be configured similarly to one of the test cells TC11 and TC21.

[0215] Reference Figures 1 to 22 , the memory cell MC11 may include an electric fuse EF, a programming transistor PTR, and a reading transistor RTR. Since the functions and operations of the electric fuse EF and the programming transistor PTR are the same as those of the above reference Figures 1 to 17 The descriptions are similar, so the detailed description will be omitted.

[0216] The test cell TC11 may include a first test transistor TTR1 and a first dummy read transistor DRTR1 .

[0217] The first test transistor TTR1 may be connected between the first bit line BL1 and a ground voltage. A gate terminal of the first test transistor TTR1 may be connected to a first dummy program word line DPWL1.

[0218] The first dummy read transistor DRTR1 may be connected between the first bit line BL1 and the first sensing line SL1. A gate terminal of the first dummy read transistor DRTR1 may be connected to a first dummy read word line DRWL1.

[0219] The test cell TC12 may include a second test transistor TTR2 and a second dummy read transistor DRTR2 .

[0220] The gate terminal of the second test transistor TTR2 may be connected to the second pseudo programming word line DPWL2. The drain terminal of the second test transistor TTR2 and the first bit line BL1 may not be electrically connected. Fig.11 , Fig. 12A and Fig. 12B A specific method in which the drain terminal of the second test transistor TTR2 and the first bit line BL1 are not electrically connected is described, and thus a detailed description thereof will be omitted.

[0221] The second dummy read transistor DRTR2 may be connected between a drain terminal of the second test transistor TTR2 and the first sensing line SL1. A gate terminal of the second dummy read transistor DRTR2 may be connected to a second dummy read word line DRWL2.

[0222] In an embodiment, the test cells TC11 and TC21 may not store data. That is, each of the test cells TC11 and TC21 may not include an electrical fuse.

[0223] To describe it more concisely, Fig. 22 , an embodiment in which the test cell TC11 includes the first dummy read transistor DRTR1 and the test cell TC21 includes the second dummy read transistor DRTR2 is representatively described in FIG. 1 . However, the scope of the present disclosure is not limited thereto. For example, the test cell TC11 may not include the first dummy read transistor DRTR1, and the test cell TC21 may not include the second dummy read transistor DRTR2. That is, the test cell TC11 and the test cell TC21 may be configured as described previously with reference to FIG. Figure 4 Described method to achieve.

[0224] Fig.23 is shown in more detail Fig. 20 A circuit diagram of a configuration of one of the bit line selection switches of FIG. Fig.23The configuration of the first bit line selection switch 151 is representatively described. However, the scope of the present disclosure is not limited thereto, and the second bit line selection switch 152 to the m-th bit line selection switch 15m may also be similarly implemented.

[0225] Reference Figures 1 to 23 , the first bit line selection switch 151 may be connected between the power rail PSR and the first bit line BL1 .

[0226] The first bit line selection switch 151 may include a first switching transistor NT and a second switching transistor PT. The first switching transistor NT and the second switching transistor PT may be connected in parallel between the power rail PSR and the first bit line BL1.

[0227] Gate terminals of the first and second switching transistors NT and PT may be connected to a control node CN. The control node CN may receive a first column selection signal CSS1. The first and second switching transistors NT and PT may operate in response to the first column selection signal CSS1.

[0228] For a more concise description, an embodiment in which the first switch transistor NT and the second switch transistor PT operate in response to a single first column selection signal CSS1 will be representatively described. However, the scope of the present disclosure is not limited thereto, and the switch controller 160 may be implemented to individually control the first switch transistor NT and the second switch transistor PT through different control signals. That is, the scope of the present disclosure will not be limited to the specific method in which the switch controller 160 controls the bit line selector 150.

[0229] When the test power supply voltage VDD_test is provided from the power supply pad PSP, the first column selection signal CSS1 may be logic high. In this case, the test power supply voltage VDD_test may be provided to the first bit line BL1 through the first switch transistor NT. That is, when the test operation of the memory device 100 is performed, the test power supply voltage VDD_test may be provided to the first bit line BL1 through the first switch transistor NT.

[0230] When the driving power supply voltage VDD_op is provided from the power supply pad PSP, the first column selection signal CSS1 may be logic low. In this case, the test power supply voltage VDD_test may be provided to the first bit line BL1 through the second switching transistor PT. That is, when a programming operation of the memory device 100 is performed, the driving power supply voltage VDD_op may be provided to the first bit line BL1 through the second switching transistor PT.

[0231] In an embodiment, the first switch transistor NT may be implemented as an N-channel metal oxide semiconductor (NMOS) transistor, and the second switch transistor PT may be implemented as a P-channel metal oxide semiconductor (PMOS) transistor.

[0232] In this case, the driving power supply voltage VDD_op, which is a relatively high voltage, can be provided to the first bit line BL1 through the PMOS transistor. On the contrary, the test power supply voltage VDD_test, which is a relatively low voltage, can be provided to the first bit line BL1 through the NMOS transistor. Therefore, according to an embodiment of the present disclosure, the type of transistor used to connect between the first bit line BL1 and the power rail PSR can be optimized according to the level of the voltage provided from the power pad PSP.

[0233] The above content is a specific implementation method for implementing the present disclosure. The present disclosure may include not only the above-mentioned embodiments, but also embodiments that can simply or easily change the design. In addition, the present disclosure may also include technologies that are easily changed to be implemented using the embodiments. Therefore, the scope of the present application should not be limited to the above-mentioned embodiments, but should be limited by the equivalents of the attached claims and the attached claims.

[0234] Ordinal numbers such as "first", "second", and "third" may simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referenced with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0235] It will be understood that when an element is referred to as being "connected" or "coupled" to or "on" another element, the element may be directly connected or coupled to or directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to or "contacting" or "in contact with" another element (or any form of the word "contacting"), there are no intervening elements at the point of contact. Other words used to describe the relationship between elements (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

Claims

1. A storage device, comprising: A first memory cell including a first electrical fuse and a first programming transistor connected in series between a first bit line and a ground voltage node; a second memory cell including a second electrical fuse and a second programming transistor connected in series between the first bit line and the ground voltage node; as well as The first test unit includes a first test transistor connected between the first bit line and the ground voltage node.

2. The memory device according to claim 1, wherein: The first programming transistor operates in response to a voltage level of a first word line, The second programming transistor operates in response to a voltage level of a second word line, and The first test transistor operates in response to a voltage level of a first dummy word line.

3. The memory device according to claim 2, further comprising: The second test unit includes a second test transistor that operates in response to a voltage level of a second dummy word line.

4. The memory device according to claim 3, wherein: the first bit line and a drain terminal of the first test transistor are electrically short-circuited to each other, The first bit line and a drain terminal of the second test transistor are electrically isolated from each other.

5. The memory device of claim 4, configured to perform a test, wherein: The first word line is activated at a first time point, The first dummy word line is activated at a second time point, and The second dummy word line is activated at a third time point.

6. The memory device of claim 5, wherein during testing: At the first time point, the first dummy word line, the second dummy word line, and the second word line are deactivated, At the second time point, the first word line, the second word line and the second dummy word line are deactivated, At the third time point, the first word line, the second word line, and the first dummy word line are deactivated.

7. The memory device according to claim 5, further comprising: Power rail, connected to the power pad; as well as a first bit line selection switch connected between the power rail and the first bit line, During the test, the first bit line selection switch is turned on at the first time point, the second time point and the third time point.

8. The memory device of claim 7, wherein during the test, a resistance value of the first electrical fuse is measured based on: a first current provided from an external device to the power pad at the first time point; a second current provided from the external device to the power pad at the second time point; as well as A third current is supplied from the external device to the power supply pad at the third time point.

9. The memory device according to claim 7, wherein the first bit line selection switch comprises: An N-channel metal oxide semiconductor (NMOS) transistor is connected between the first bit line and the power rail and is turned on at the first time point, the second time point and the third time point.

10. The memory device according to claim 1, wherein: The size of the first test transistor corresponds to the size of the first programming transistor.

11. A testing system comprising: A memory device comprising a first memory cell connected to a first word line and a first bit line, a first test cell connected to a first dummy word line and the first bit line, and a power supply pad connected to the first bit line; as well as A test device is configured to measure a first current supplied to the power pad in response to activation of the first word line and the first bit line, a second current supplied to the power pad in response to activation of the first pseudo word line and the first bit line, and a third current supplied to the power pad in response to activation of the first bit line.

12. The test system according to claim 11, wherein: The first memory cell includes a first programming transistor and a first electrical fuse connected in series between the first bit line and a ground voltage; The first test unit includes a first test transistor connected between the first bit line and the ground voltage, The first programming transistor operates in response to a voltage level of the first word line, and the first test transistor operates in response to a voltage level of the first dummy word line. 13 . The test system according to claim 12 , wherein the test device further comprises a second test unit connected to the first bit line and the second dummy word line.

14. The test system according to claim 13, wherein the second test unit comprises: A second test transistor includes a gate terminal connected to the second dummy word line, a source terminal connected to the ground voltage, and a drain terminal not electrically connected to the first bit line. 15 . The test system according to claim 12 , wherein the test device is configured to calculate a resistance value of the first electrical fuse based on the first current to the third current. 16 . The test system of claim 15 , wherein the test device is configured to provide a first voltage to the power supply pad while measuring the first current, the second current, and the third current.

17. The test system of claim 16, wherein: The testing device is configured to calculate the resistance value of the first electrical fuse based on the following equation, Equation: Among them, R target represents the resistance value of the first electrical fuse, VDD_test represents the voltage level of the first voltage, and I A represents the magnitude of the first current, I B represents the magnitude of the second current, I C Indicates the magnitude of the third current.

18. The test system of claim 12, wherein sizes of the first programming transistor and the first test transistor correspond to each other.

19. A storage device comprising: a memory cell array including a plurality of memory cells connected to a first bit line; as well as a test cell array including a first test cell and a second test cell connected to the first bit line, Wherein, the first test unit comprises: a first test transistor including a first drain terminal electrically connected to the first bit line and a first source terminal connected to a ground voltage node, Wherein, the second test unit comprises: The second test transistor includes a second drain terminal not electrically connected to the first bit line and a second source terminal connected to the ground voltage node.

20. The memory device of claim 19, wherein: The first testing unit comprises: a first bit line contact connected to the first bit line; a first drain contact connected to the first drain terminal; and a first conductor connected to the first bit line contact and the first drain contact through one or more vias, and The second test unit comprises: a second bit line contact connected to the first bit line; a second drain contact connected to the second drain terminal; and a second conductor; and An interlayer insulating layer electrically separates the second conductor, the second bit line contact and the second drain contact.

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