Test method and test device for memory chip

Abstract

The invention provides a test method and a test device for a storage chip, and belongs to the technical field of storage. The test method of the memory chip comprises the following steps: writing filling data into the memory chip until a memory is filled with the filling data; starting a cache function of the storage chip, and writing test data into the storage chip, the data format of the test data in each data unit being related to the writing sequence, and the data formats of the test data written in each data unit being the same; when the data volume of the test data written into the storage chip reaches a set threshold value, power supply of the storage chip is cut off in the process of writing the test data into the storage chip; and obtaining the capacity of the write buffer according to the test data which is finally written in the memory and the test data which is finally written in the write buffer. According to the test method and the test device for the memory chip, the capacity of the write buffer can be obtained.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and in particular relates to a testing method and a testing device for a storage chip. Background Art

[0002] Solid-state memory is a new type of storage device. It can be used to make a variety of storage chips, such as solid-state hard disks, embedded multimedia memory cards, universal flash storage, security cards and other storage chips. The new storage chip is equipped with a controller, a cache and a memory, and the cost of the cache is much higher than that of the memory.

[0003] When doing competitive product analysis, it is necessary to evaluate the capacity of the cache. Although the size of the internal cache can be detected through physical means such as X-rays, this method is expensive and cannot obtain the size of specific types of caches in the cache, such as the size of the write cache. Summary of the invention

[0004] The object of the present invention is to provide a memory chip testing method and a testing device, which can solve the problem of being unable to effectively obtain the size of a specific type of buffer in the memory chip.

[0005] To achieve the above object, the present invention provides a memory chip testing method and a memory chip testing device, and the memory chip testing method at least comprises the following steps: Writing filling data to the memory chip until the filling data fills up the memory; Turning on the cache function of the memory chip and writing test data into the memory chip, wherein the data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same; When the amount of the test data written into the memory chip reaches a set threshold, disconnecting the power supply of the memory chip during the process of writing the test data into the memory chip; and The capacity of the write buffer is obtained according to the test data last written in the memory and the test data last written in the write buffer.

[0006] In an embodiment of the present invention, the data format of the filling data is different from that of the test data.

[0007] In an embodiment of the present invention, the value of the padding data is greater than the number of the data units in the memory.

[0008] In one embodiment of the present invention, the amount of the padding data written into the storage chip is greater than the total capacity of the memory and the buffer.

[0009] In one embodiment of the present invention, when writing test data into the memory chip, each time the test data of one data unit is written, the value of the test data is increased by one.

[0010] In an embodiment of the present invention, the amount of the test data in each data format is equal to the capacity of the data unit divided by the size of one test data.

[0011] In an embodiment of the present invention, the set threshold is greater than the capacity of the write buffer.

[0012] In one embodiment of the present invention, the capacity of the write buffer is obtained by the following formula: T = (mn) × Q; Wherein, T is the capacity of the write buffer, m is the value of the test data last written in the write buffer, n is the value of the test data last written in the memory, and Q is the capacity of the data unit.

[0013] In one embodiment of the present invention, the testing method further includes: The capacity of the data unit is reduced to regain the capacity of the write buffer.

[0014] The present invention also provides a test device for a memory chip, the test device comprising: a memory storing program instructions; and A processor runs the program instructions to implement any one of the memory chip testing methods described above.

[0015] In summary, the present invention provides a test method and a test device for a memory chip, in which a host sends fill data to a memory chip to fill up the memory. Then, under the condition that the cache function is turned on, the test data is written into the memory chip. After the test data fills up the write buffer, the memory chip is powered off. According to the test data last written into the write buffer and the test data last sent, the amount of test data stored in the write buffer is obtained, and then the size of the write buffer is obtained. Therefore, through this application, when the internal structure of the memory chip is not clear, the size of the read buffer can be tested more accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of the structure of a storage chip in one embodiment of the present application.

[0018] Figure 2 It is a flow chart of a method for testing a memory chip in one embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of the structure of a testing device in one embodiment of the application. DETAILED DESCRIPTION

[0020] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0022] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. The degrees indicated by "high" and "low" are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have high and low, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0023] See also Figure 1As shown, in one embodiment of the present invention, the storage chip 200 using Nand flash memory as the storage medium has the characteristics of non-volatility, fast read and write speed, shock resistance, low power consumption, small size, etc. compared with the traditional magnetic disk, and is currently widely used in embedded systems, consumer electronics, aerospace and other fields. According to the different protocols of communication between the storage chip 200 and the host 100, it can be divided into embedded memory 203 standard specifications (Embedded Multi Media Card, eMMC), universal flash storage (Universal Flash Storage, UFS), serial hard disk (Serial ATA, SATA) and high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe), etc.

[0024] See also Figure 1 As shown, in one embodiment of the present invention, a memory chip 200 is provided with a controller 201, a buffer 202 and a memory 203. The controller 201 can execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations such as writing, reading and erasing data in the memory 203 according to the instructions of the host 100.

[0025] See also Figure 1 As shown, in one embodiment of the present invention, the memory 203 is a non-volatile storage unit, and the memory 203 stores data written by the host 100 and other necessary data such as a mapping table. Among them, the memory 203 can be a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, a resistance random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM) or a spin transfer torque random access memory (STT-RAM). The memory 203 may include a storage cell array block connected to a word line, a string selection line, a ground selection line and a bit line. The memory 203 may include a super block including a plurality of storage blocks. The plurality of storage blocks may include a plurality of pages. The memory 203 may include a two-dimensional (2D) memory array block or a three-dimensional (3D) memory array block. Other types of non-volatile storage units may also be used. In this embodiment, the structure of the NAND flash memory 203 is taken as an example for explanation, and the memory 203 includes a plurality of flash memory blocks 2031. It is understandable that in other embodiments, the memory 203 may also adopt other types of non-volatile storage unit structures.

[0026] See also Figure 1As shown, in one embodiment of the present invention, the flash memory blocks 2031 in the memory 203 may belong to the same memory 203 die or to different memory 203 die. Each flash memory block 2031 has a plurality of physical pages, and each physical page has at least one physical sector, wherein the physical pages belonging to the same flash memory block 2031 can be independently written and erased simultaneously. For example, each flash memory block 2031 is composed of 128 physical pages, and each physical page has 8 physical sectors. That is to say, in an example where each physical sector is 512 bytes, the capacity of each physical page is 4 kilobytes (K). However, in one embodiment, each flash memory block 2031 may be composed of 64 physical pages, 256 physical pages, or any other number of physical pages.

[0027] See also Figure 1 As shown, in one embodiment of the present invention, the flash memory block 2031 is the minimum unit of erasure. That is, each flash memory block 2031 contains the minimum number of storage cells that are erased together. The physical page is the minimum unit that can be programmed. That is, the physical page is the minimum unit for writing data. However, in some embodiments, the minimum unit for writing data can also be a physical sector or other size. Each physical page generally includes a data bit area and a redundant bit area. The data bit area is used to store user data, and the redundant bit area is used to store system data (e.g., error checking and correction code).

[0028] See also Figure 1As shown, in one embodiment of the present invention, the buffer 202 is a high-speed storage device with a faster access speed than the memory 203. The buffer 202 includes a read buffer 2021 and a write buffer 2022. When the cache function of the memory chip 200 is turned on, when reading data from the memory chip 200, the host 100 first searches in the buffer 202 when reading the data, and immediately reads and sends it to the controller 201 for processing if it is found. If it is not found in the buffer 202, it is read from the memory 203 with a relatively slow speed and sent to the controller 201 for processing. At the same time, the data block where the data is located is transferred into the cache, so that the entire block of data can be read from the cache in the future, and there is no need to call the memory. In this way, the time for data reading is greatly saved, and the controller 201 basically does not need to wait when reading data. When writing data to the memory chip 200, the write data will be stored in the write buffer 2022 first, and then a "data has been written" signal will be fed back to the host 100, and then the host 100 will think that the data has been written. When the write buffer 2022 is full of write data, or the amount of write data in the write buffer 2022 reaches a set threshold, the write data in the write buffer 2022 is sent to the memory 203 in batches. If the memory chip 200 loses power during data transmission, the data in the write buffer 2022 will be lost.

[0029] See also Figure 1 and Figure 2 As shown, the present invention provides a memory chip testing method and a testing device, which can obtain the size of the write buffer 2022 in the memory chip 200. Specifically, the memory chip testing method includes steps S101 to S104.

[0030] Step S101, writing filling data into the storage chip until the filling data fills up the memory.

[0031] Step S102, enable the cache function of the memory chip, and write test data into the memory chip, the data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same.

[0032] Step S103: when the amount of test data written into the memory chip reaches a set threshold, power supply to the memory chip is disconnected during the process of writing the test data into the memory chip.

[0033] Step S104: Acquire the capacity of the write buffer according to the test data last written into the memory and the test data last written into the write buffer.

[0034] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, in step S101, padding data is first written into the memory chip 200 until the padding data fills up the memory 203. At this time, the memory chip 200 does not enable the cache function of the memory chip 200. In some embodiments, when padding data is written into the memory chip 200, the written padding data can be directly stored in the memory 203 of the memory chip 200. In other embodiments, when padding data is written into the memory chip 200, the written padding data can be first stored in the write buffer 2022 and then sent to the memory 203.

[0035] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the data format of the filling data is different from the data format of the subsequent writing to the storage chip 200, so as to avoid confusion when the capacity of the write buffer 2022 is obtained by the data format of the test data in the subsequent process. Since the data format of the test data written in the subsequent process is related to the writing order, and the data format of the test data in each data unit is the same, the maximum value of the test data written in the subsequent process is equal to the number of data units. Therefore, when writing the filling data, the value of the filling data is set to be greater than the number of data units in the memory 203, so as to ensure that the data format of the filling data is different from the data format of the subsequent writing to the storage chip 200. In a specific embodiment of the present invention, if the size of the memory 203 in the storage chip 200 is 1GB, and the capacity of each data unit is 4KB, then there are a total of 1GB / 4KB=256K data units in the memory 203. Converted into hexadecimal, there are a total of 0x40000 data units in the memory 203. Then the value of the filling data is greater than 0x40000, so that the data format of the filling data is different from the data format of the test data written in the storage chip 200 in the subsequent process. Specifically, the data format of the filling data is, for example, 0xFFFFF, 0x100000 or 0xFFFFFF, etc. The present application is described with the data format of the filling data being 0xFFFFFFFF.

[0036] Please note that Figure 1 and Figure 2 As shown, the data unit is the smallest programmable unit. In this embodiment, the data unit is the size of a physical page, that is, 4KB. The format of the filling data is 0xFFFFFFFF, and the size of the filling data is 4B, so 1024 filling data are required to fill a data unit. In other embodiments, the data unit may also be the size of a physical sector, for example, 512B. Of course, the data unit may also be of other sizes. The amount of filling data required to fill a data unit needs to be set according to the capacity of the data unit and the size of the filling data.

[0037] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, to ensure that the padding data fills up the memory 203, the amount of padding data written into the memory chip 200 is greater than the total capacity of the memory 203 and the write buffer 2022. It is ensured that even if part of the padding data is stored in the write buffer 2022, the remaining padding data can also fill up the memory 203.

[0038] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after the filling data fills up the memory 203, the cache function of the memory chip 200 is turned on. At this time, the test data written into the memory chip 200 is first stored in the write buffer 2022. When the write buffer 2022 is full of test data, the test data is written into the memory chip 200 again, and the test data first written into the write buffer 2022 will be sent to the memory 203, and the test data written later will be stored in the write buffer 2022.

[0039] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, when writing test data into the memory chip 200, the data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same. In this embodiment, each time the test data of a data unit is written, the value of the test data is increased by one, so that the data format of the test data in a data unit is different from the data format of the test data in the previous data unit, while the data format of the test data in the same data unit is the same. The number of test data in each data format is equal to the capacity of the data unit divided by the size of one test data.

[0040] For details, please refer to Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the test data of the first data format sent to the memory chip 200 is, for example, 0x00000001, and the size of the test data of the first data format is 4B. The capacity of the data unit is, for example, 4KB. Then, 1024 test data of the first data format are sent to the memory chip 200, that is, 1024 0x00000001 are sent to the memory chip 200.

[0041] After sending a data unit of test data of the first data format to the memory chip 200, the value of the test data is increased by 1 to form test data of the second data format, and the test data of the second data format is sent to the memory chip 200. The test data of the second data format is, for example, 0x00000002, and the size of the test data of the second data format is 4B. The capacity of the data unit is, for example, 4KB. Then, 1024 test data of the second data format are sent to the memory chip 200, that is, 1024 0x00000002 are sent to the memory chip 200.

[0042] Next, 1024 test data in the third data format, 1024 test data in the fourth data format, and 1024 test data in the fifth data format are sent to the memory chip 200 in sequence. That is, 1024 0x00000003, 1024 0x00000004, and 1024 0x00000005 are sent to the memory chip 200 in sequence. These test data are first stored in the write buffer 2022. When the write buffer 2022 is full of test data, the test data in the write buffer 2022 is sent to the memory 203 in the writing order. Then 1024 test data in the first data format are first sent to the memory 203, and the 1024 test data in the first data format cover the padding data in the original data unit. That is, 1024 0x00000001 first cover the padding data 0xFFFFFFFF in a data unit in the memory 203.

[0043] Then, as the input end of the write buffer 2022 writes data, the write buffer 2022 sends 1024 test data in the second data format, 1024 test data in the third data format, 1024 test data in the fourth data format, and 1024 test data in the fifth data format to the memory 203. That is, 1024 0x00000002s cover the padding data 0xFFFFFFFF in a data unit in the memory 203, 1024 0x00000003s cover the padding data 0xFFFFFFFF in a data unit in the memory 203, 1024 0x00000004s cover the padding data 0xFFFFFFFF in a data unit in the memory 203, and 1024 0x00000005s cover the padding data 0xFFFFFFFF in a data unit in the memory 203, etc.

[0044] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, in step S103, the threshold is set to be greater than the capacity of the write buffer 2022. When the amount of test data written to the memory chip 200 is greater than the capacity of the write buffer 2022, the test data in the write buffer 2022 will be sent to the memory 203 according to the writing order of the test data, thereby ensuring that the sent test data is in the memory 203. When sending the test data in the write buffer 2022 to the memory 203, since the speed of writing the test data to the write buffer 2022 is much greater than the speed of sending the test data from the write buffer 2022 to the memory 203, the write buffer 2022 is always in a full state.

[0045] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, since the capacity of the write buffer 2022 cannot be confirmed, the write buffer 2022 capacity can be processed according to the maximum capacity of the write buffer 2022 on the market, or double or triple the maximum capacity of the write buffer 2022 on the market. This ensures that the test data fills up the write buffer 2022, and the test data is sent to the memory 203.

[0046] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, a control switch 101 is provided between the host 100 and the memory chip 200, and the control switch 101 may be a control switch 101 such as a relay or a circuit breaker. When the amount of test data written into the memory chip 200 reaches a set threshold, the power supply of the memory chip 200 is disconnected by disconnecting the control switch 101 during the process of writing the test data into the memory chip 200. At this time, due to the sudden power failure outside the memory chip 200, the test data stored in the write buffer 2022 will be lost, while the test data saved in the memory 203 is still saved in the memory 203.

[0047] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, a monitoring program is provided at the host 100 to monitor the test data last sent to the storage chip 200, that is, the test data last written to the write buffer 2022 before power failure.

[0048] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, after the memory chip 200 is powered off, the power supply of the memory chip 200 is restored by controlling the switch 101. By querying the test data and the fill data stored in the memory 203, the test data and the fill data can be distinguished according to the format of the test data and the fill data. Since the value of the last test data written is the maximum value of all the test data, the test data with the largest value is the last test data written.

[0049] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after obtaining the last test data written in the memory 203 and the last test data written in the write buffer 2022, the range of the value of the test data stored in the write buffer 2022 can be obtained according to the value of the last test data written in the memory 203 and the value of the last test data written in the write buffer 2022, thereby obtaining the capacity of the write buffer 2022. In this embodiment, the capacity of the write buffer 2022 is obtained by the following formula: T = (mn) × Q; Wherein, T is the capacity of the write buffer 2022, m is the value of the test data last written in the write buffer 2022, n is the value of the test data last written in the memory 203, and Q is the capacity of the data unit.

[0050] It should be noted that, under the condition that the value of the data unit capacity Q is the same, the larger the value of mn is, the larger the capacity of the write buffer 2022 in the memory chip 200 is. If the value of mn is zero, it means that there is no write buffer 2022 in the memory chip 200.

[0051] See also Figure 1 and Figure 2 As shown, in a specific embodiment of the present invention, the last test data written in the memory 203 is, for example, 0x00008000, and the last test data written in the memory 203 is, for example, 0x00007000, and the capacity of the data unit is, for example, 4KB, then the capacity of the write buffer 2022 is: T=(0x00008000-0x00007000)×4KB=0x1000×4KB=16MB.

[0052] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, when it is necessary to obtain a more accurate capacity of the write buffer 2022, the capacity of the data unit is reduced. For example, it is reduced from 4KB to 512B. After that, steps S101 to S104 are repeatedly executed in a loop until the size of the capacity of the write buffer 2022 is obtained again. As the capacity of the data unit decreases, the value of the test data increases, and the range of the capacity of the write buffer 2022 obtained is more accurate.

[0053] See also Figure 3 As shown, the present invention also provides a memory chip testing device, the testing device includes a memory 302 and a processor 301, the memory 302 stores program instructions, and the processor 301 runs the program instructions in the memory 302 to implement the above-mentioned memory chip testing method.

[0054] See also Figure 3 As shown, the memory 302 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (for example, SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory may be an internal storage unit of an electronic device, such as a mobile hard disk of the electronic device. In other embodiments, the memory may also be an external storage device of an electronic device, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device. Further, the memory may also include both an internal storage unit of the electronic device and an external storage device. The memory may be used not only to store application software and various types of data installed in the electronic device, but also to temporarily store data that has been output or is to be output.

[0055] See also Figure 3 As shown, in some embodiments, the processor 301 may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips. The processor is the control core (Control Unit) of the host, and executes various functions of the host and processes data by running or executing programs or modules stored in the memory, and calling data stored in the memory.

[0056] The processor executes the operating system of the host and various installed application programs. The processor executes the application programs to implement the steps in the above method embodiment.

[0057] Exemplarily, the program may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of program instruction segments capable of completing specific functions, which are used to describe the execution process of the program in the host.

[0058] The above-mentioned integrated unit implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, and includes a number of instructions for enabling a computer device (which can be a personal computer, a computer device, or a network device, etc.) or a processor to perform part of the functions of the lithium battery cold solder joint detection method of each embodiment of the present invention.

[0059] In summary, a method and device for testing a memory chip are provided, wherein the method includes writing fill data to the memory chip until the fill data fills up the memory. Next, the cache function of the memory chip is turned on, and test data is written to the memory chip. The data format of the test data in each data unit is related to the write order, and the data format of the test data written in each data unit is the same. When the amount of test data written to the memory chip reaches a set threshold, the power supply of the memory chip is disconnected during the process of writing test data to the memory chip. The capacity of the write buffer is obtained based on the last test data written to the memory and the last test data written to the write buffer.

[0060] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for testing a memory chip, characterized in that: At least the following steps are included: Writing filling data to the memory chip until the filling data fills up the memory; Turning on the cache function of the memory chip and writing test data into the memory chip, wherein the data format of the test data in each data unit is related to the writing order, and the data format of the test data written in each data unit is the same; When the amount of the test data written into the memory chip reaches a set threshold, disconnecting the power supply of the memory chip during the process of writing the test data into the memory chip; as well as The capacity of the write buffer is obtained according to the test data last written in the memory and the test data last written in the write buffer.

2. A memory chip testing method according to claim 1, characterized in that: The padding data and the test data have different data formats.

3. The memory chip testing method according to claim 1, characterized in that: The value of the filling data is greater than the number of the data units in the memory.

4. The method for testing a memory chip according to claim 1, characterized in that: The amount of the filling data written into the storage chip is greater than the total capacity of the memory and the buffer.

5. The method for testing a memory chip according to claim 1, characterized in that: When writing test data into the memory chip, each time the test data of one data unit is written, the value of the test data is increased by one.

6. The method for testing a memory chip according to claim 1, characterized in that: The amount of the test data in each data format is equal to the capacity of the data unit divided by the size of one test data.

7. The memory chip testing method according to claim 1, characterized in that: The set threshold is greater than the capacity of the write buffer.

8. The method for testing a memory chip according to claim 1, characterized in that: The capacity of the write buffer is obtained by the following formula: T = (mn) × Q; Wherein, T is the capacity of the write buffer, m is the value of the test data last written in the write buffer, n is the value of the test data last written in the memory, and Q is the capacity of the data unit.

9. The method for testing a memory chip according to claim 1, characterized in that: The test method also includes: The capacity of the data unit is reduced to regain the capacity of the write buffer.

10. A memory chip testing device, characterized in that: The testing device comprises: a memory storing program instructions; and A processor runs the program instructions to implement the memory chip testing method according to any one of claims 1 to 9.

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