Method for manufacturing aluminum bonding pad of semiconductor chip

Abstract

The invention discloses a method for manufacturing an aluminum bonding pad of a semiconductor chip. A grown top metal layer is arranged on the upper surface of a semiconductor substrate; depositing a passivation layer with a SiN-OX-SiN-OX four-layer structure from bottom to top on the top metal layer; removing the passivation layer in the connecting hole region, and reserving the passivation layer outside the connecting hole region; performing an aluminum bonding pad layer process; photoetching and etching, removing the aluminum in the area which does not need the aluminum, and reserving the aluminum in the area of the connecting hole; and completing the preparation of the aluminum bonding pad. According to the manufacturing method of the semiconductor chip aluminum bonding pad, on the premise that the functionality of the aluminum bonding pad is guaranteed, the hidden danger of crystallization of the Al bonding pad can be solved from the source, a mask and a developing layer can be saved, cost is low, and the technology is stable.

Description

Technical Field

[0001] The invention relates to semiconductor manufacturing technology, and in particular to a method for manufacturing an aluminum pad of a semiconductor chip. Background Art

[0002] As the interface between the internal circuit of the chip and the external leads, the pad has an important impact on the yield and reliability of the chip. On the one hand, the state of the pad surface will affect the quality of wire bonding. Defects on the pad surface will cause wire bonding failure or poor wire bonding reliability, thereby reducing the yield of the back-end packaging and testing, and even affecting the reliability of the final product. On the other hand, since the pad manufacturing process is at the end of the entire wafer manufacturing process, the scrapped wafers due to defects on the pad surface are close to finished products, making the scrapping cost very high. Therefore, studying the defect problem in pad manufacturing has a positive significance for ensuring chip production quality, improving the overall chip manufacturing yield and reliability, and reducing the risk of product scrapping.

[0003] Aluminum metal is still retained as a material for manufacturing off-chip interconnects and pads in process nodes due to its good oxidation resistance and welding performance. Pad crystallization defects are a type of crystallization defect caused by fluorine corrosion on the surface of aluminum pads. Crystal defects are damaging defects that will cause wire bonding failures in the packaging process, seriously affecting the yield and reliability of the chip. There are many reasons for pad crystallization defects. In addition to the impact caused by transportation packaging, chip packaging and other processes, the introduction of fluorine in the pad during wafer processing is an important reason.

[0004] When aluminum is used as the surface metal layer, after the passivation layer on the aluminum surface is etched to open the pad window in the semiconductor process, the aluminum pad is exposed to the air and is prone to electrochemical reactions with water vapor and fluorine in the environment to form crystal defects such as fluoride oxides.

[0005] In the Al-TiN stacked structure formed by the conventional APL (Aluminum Pad Layer) process, Al is covered by TiN, which plays an initial protective role. In the conventional APL (Aluminum Pad Layer) process, when defining the Al pad area, in order to expose Al, a Cover-Etch process is required, and the TiN on the surface of the Al pad area needs to be removed. The current means of removing TiN in the industry require the introduction of fluorine-containing polymers. Once the fluorine-containing polymer is not cleaned up in time after removing TiN, Fluorine residue will easily appear. Moreover, when Al is subsequently exposed to the air, combined with the air environment (including water vapor, fluorine and other substances), an electrochemical reaction will occur to form crystals such as fluorine oxides, which can easily cause Al pad crystallization (AlPad crystal) on the surface of the newly exposed Al pad, thereby greatly increasing the resistance of the Al pad, causing the functional failure of the Al pad, and seriously affecting the performance of the chip. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a method for manufacturing an aluminum pad for a semiconductor chip. Under the premise of ensuring the functionality of the aluminum pad, the hidden danger of Al pad crystallization can be solved from the source, and a mask and a developing layer can be saved, with low cost and stable process.

[0007] In order to solve the above technical problems, the present invention provides a method for manufacturing an aluminum pad for a semiconductor chip, which comprises the following steps:

[0008] S1. Providing a semiconductor substrate, wherein the upper surface of the semiconductor substrate is a top metal layer 100 that has been grown;

[0009] S2. Depositing a passivation layer on the top metal layer 100, the passivation layer being a four-layer structure of SiN-OX-SiN-OX from bottom to top;

[0010] S3. Removing the passivation layer in the connection hole region, and retaining the passivation layer outside the connection hole region;

[0011] S4. Performing aluminum pad layer process;

[0012] S5. Photolithography and etching are performed to remove aluminum in areas where aluminum is not needed and to retain aluminum in the connection hole area; thus, the preparation of the aluminum pad is completed.

[0013] Preferably, the semiconductor chip is a SONOS memory.

[0014] Preferably, in step S3, the connection hole region is defined by an RV process, the passivation layer in the connection hole region is removed, and the passivation layer outside the connection hole region is retained.

[0015] Preferably, the RV process includes distributed through-hole photoresist development and distributed through-hole etching;

[0016] By developing the distributed through-hole photoresist 105, a connection hole area is defined;

[0017] The passivation layer in the connection hole area is removed by distributing the through hole etching process, and the passivation layer outside the connection hole area is retained.

[0018] Preferably, the aluminum pad layer process includes aluminum line formation and aluminum deposition.

[0019] Preferably, in step S2, depositing a passivation layer on the top metal layer 100 comprises the following steps:

[0020] S21. Depositing a first SiN layer 101 on the top metal layer 100;

[0021] S22. Depositing a first OX layer 102 on the first SiN layer 101;

[0022] S23. Depositing a second SiN layer 103 on the first OX layer 102;

[0023] S24 . Depositing a second OX layer 104 on the second SiN layer 103 .

[0024] Preferably, the first SiN layer 101 , the first OX layer 102 , the second SiN layer 10 and the second OX layer 104 are formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0025] Preferably, the thickness of the first SiN layer 101 is 800nm ​​to 1200nm;

[0026] The first OX layer 102 has a thickness of 6800 nm to 7200 nm;

[0027] The second SiN layer 103 has a thickness of 3800nm ​​to 4200nm;

[0028] The second OX layer 104 has a thickness of 1000 nm to 5000 nm.

[0029] Preferably, in step S4 , the aluminum pad layer process adopts physical vapor deposition, first depositing the TaN / Ti / TiN layer 106 and then depositing the Al layer 107 .

[0030] Preferably, the top metal layer 100 is metal Cu.

[0031] The manufacturing method of the semiconductor chip aluminum pad of the present invention does not need to perform a cover-ET loop, does not need to deposit a barrier layer film on the Al surface as a chip cover, does not need to perform area definition again on the formed Al pad to remove the chip cover, and does not introduce fluorine elements / ions, so there will be no Al pad crystallization (Al Pad crystal) phenomenon; moreover, when the aluminum pad layer (Aluminum Pad Layer, APL) is etched (APL-ET), the top OX (oxide) layer of the passivation layer of the SiN-OX-SiN-OX four-layer structure can also play a protective role, and the sandwich structure of the lower three layers of SiN-OX-SiN is completely maintained, and the same parts as the conventional process are retained, and there are no other hidden dangers (side effects). The manufacturing method of the aluminum pad of a semiconductor chip, under the premise of ensuring the functionality of the aluminum pad, combines the device structural characteristics and skips the entire protective layer process link (Cover loop), which can not only solve the hidden danger of Al pad crystallization from the source, but also save a mask plate (Mask) and a developing layer (Photo Layer), with low cost and stable process. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 This is a schematic cross-sectional view of a four-layer structure of SiN-OX-SiN-OX deposited on a top metal layer in an embodiment of a method for manufacturing an aluminum pad of a semiconductor chip of the present invention;

[0034] Figure 2 A schematic cross-sectional view of a region where Al growth is required is photolithographically defined in a method for manufacturing an aluminum pad of a semiconductor chip according to an embodiment of the present invention;

[0035] Figure 3 A schematic cross-sectional view of removing the passivation layer in the area where Al growth is required according to an embodiment of a method for manufacturing an aluminum pad of a semiconductor chip of the present invention;

[0036] Figure 4 A schematic cross-sectional view of an aluminum pad layer process for a method for manufacturing an aluminum pad for a semiconductor chip according to an embodiment of the present invention;

[0037] Figure 5 A schematic cross-sectional view of a connection hole region defined by photolithography in a method for manufacturing an aluminum pad of a semiconductor chip according to an embodiment of the present invention;

[0038] Figure 6 The present invention is a schematic cross-sectional view of a method for manufacturing an aluminum pad for a semiconductor chip, wherein etching is performed to remove excess Al outside the connection hole area. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprises" and similar terms mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "front", "back" and the like are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0041] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0042] Embodiment 1

[0043] A method for manufacturing an aluminum pad for a semiconductor chip, such as Figures 1 to 6 As shown, the following steps are included:

[0044] S1. Providing a semiconductor substrate, wherein the upper surface of the semiconductor substrate is a top metal layer (Top metal) 100 that has been grown;

[0045] S2. Depositing a passivation layer on the top metal layer 100, the passivation layer is a four-layer structure of SiN-OX-SiN-OX from bottom to top, such as Figure 1 As shown;

[0046] S3. Remove the passivation layer in the via region and retain the passivation layer outside the via region; Figure 2 , Figure 3 As shown;

[0047] S4. Perform an aluminum pad layer (APL) process, such as Figure 4 As shown;

[0048] S5. Photolithography and etching are performed to remove the excess Al in the area where Al is not needed (outside the connection hole area), and the Al in the connection hole (Via) area is retained to complete the preparation of the Al pad (Aluminum Pad).

[0049] Preferably, the semiconductor chip is a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory.

[0050] In the manufacturing method of the aluminum pad of a semiconductor chip of the first embodiment, oxide and nitride are deposited on the surface of the top metal layer 100 to form a passivation layer (Passivation layer) of a SiN-OX-SiN-OX four-layer structure, wherein the three layers below the passivation layer are conventional SiN-OX-SiN sandwich structures, and the top layer of the passivation layer is an oxide (OX) protective layer, which can protect the bottom sandwich structure from being damaged during the etching (APL-ET) of the aluminum pad layer (Aluminum Pad Layer, APL); then, the passivation layer is subjected to an RV (Redistribution Via) process to define a via region, remove the passivation layer in the via region, and retain the passivation layer outside the via region; then, the aluminum pad layer (Aluminum Pad Layer, APL) is subjected to an etch process (APL-ET); Layer (APL) process, and finally remove the excess Al in the area where Al is not needed by etching (Etch), retaining the Al in the area of ​​the connection hole (Via), and then form an Al pad that can be used or tested directly (such as various electrical tests on Wafer). At this time, the structure around the Al pad is different from the structure around the Al pad area grown by conventional processes (the top layer is a layer of oxide (OX) protective layer), and the Al surface does not need to grow another layer of TiN to protect Al; in addition, the exposed Al can form a protective layer by itself because its surface is easily oxidized by oxygen. During testing and use, the protective layer is formed spontaneously and has a thin film thickness, which is easy to penetrate, so it will not affect testing and use.

[0051] The manufacturing method of the aluminum pad of a semiconductor chip in the first embodiment does not require a cover-ET loop, does not require deposition of a barrier film on the Al surface as a chip cover, does not require re-regional definition of the formed Al pad to remove the chip cover, and does not introduce fluorine elements / ions, so there will be no Al pad crystallization (Al Pad crystal) phenomenon; moreover, during the etching (APL-ET) of the aluminum pad layer (Aluminum Pad Layer, APL), the top OX (oxide) layer of the passivation layer of the SiN-OX-SiN-OX four-layer structure can also play a protective role, completely maintaining the sandwich structure of the lower three layers of SiN-OX-SiN, retaining the same parts as the conventional process, and there are no other hidden dangers (side effects). The manufacturing method of the semiconductor chip aluminum pad of the first embodiment, under the premise of ensuring the functionality of the aluminum pad, combines the device structure characteristics and skips the entire protection layer process link (Cover loop). It can not only solve the hidden danger of Al pad crystallization from the source, but also save a mask plate (Mask) and a developing layer (PhotoLayer), with low cost and stable process.

[0052] Embodiment 2

[0053] Based on the method for manufacturing the aluminum pad of a semiconductor chip of the first embodiment, in step S3, a connection hole area is defined through an RV (Redistribution Via) process, the passivation layer in the connection hole area is removed, and the passivation layer outside the connection hole area is retained.

[0054] Preferably, the RV (Redistribution Via) process includes RV-Photo (development of the distribution via photoresist 105) and RV-Etch (etching of the distribution via);

[0055] By performing RV-Photo (distribution through-hole photoresist 105 development), the area where Al growth is required is defined, such as Figure 2 As shown;

[0056] The passivation layer (Passivation layer) of the connection hole area is removed by the RV-Etch (distribution through hole etching) process to expose the top metal layer (Top metal) 100 of the connection hole area, and the passivation layer (Passivation layer) of the area outside the connection hole area where Al growth is not required is retained, such as Figure 3 shown.

[0057] Preferably, the aluminum pad layer (APL) process includes Al-Liner (Al line) formation and Al-Dep (Al deposition).

[0058] Embodiment 3

[0059] Based on the method for manufacturing the aluminum pad of a semiconductor chip in the first embodiment, in step S2, depositing a passivation layer on the top metal layer 100 includes the following steps:

[0060] S21. Depositing a first SiN layer 101 on the top metal layer (Top metal) 100;

[0061] S22. Depositing a first OX layer 102 on the first SiN layer 101;

[0062] S23. Depositing a second SiN layer 103 on the first OX layer 102;

[0063] S24. Depositing a second OX layer 104 on the second SiN layer 103, such as Figure 1 shown.

[0064] Preferably, the first SiN layer 101 , the first OX layer 102 , the second SiN layer 10 , and the second OX layer 104 are formed by chemical vapor deposition, physical vapor deposition (PVD) or atomic layer deposition.

[0065] Preferably, the thickness of the first SiN layer 101 is 800 nm to 1200 nm (eg, 1000 nm);

[0066] The first OX layer 102 has a thickness of 6800 nm to 7200 nm, for example 7000 nm);

[0067] The second SiN layer 103 has a thickness of 3800 nm to 4200 nm (eg, 4000 nm);

[0068] The thickness of the second OX layer 104 is 1000 nm to 5000 nm, preferably 2000 nm to 4000 nm (eg, 3000 nm).

[0069] Embodiment 4

[0070] Based on the method for manufacturing the aluminum pad of a semiconductor chip in the first embodiment, in step S4, the aluminum pad layer process adopts a physical vapor deposition (PVD) process to first deposit a TaN / Ti / TiN layer 106 and then deposit an Al layer 107. Figure 4 shown.

[0071] Preferably, the top metal layer (Top metal) 100 is metal Cu.

[0072] Embodiment 5

[0073] Based on the method for manufacturing the aluminum pad of a semiconductor chip in the first embodiment, in step S5, firstly, the photoresist 105 is photolithographically defined to define a connection hole (Via) area, such as Figure 5 As shown; then the excess Al outside the connection hole (Via) area is etched away, and the Al in the connection hole (Via) area is retained, as shown Figure 6 As shown, the preparation of the Al pad is completed.

[0074] In the manufacturing method of the semiconductor chip aluminum pad of the fifth embodiment, all the excess Al outside the connection hole (Via) area is removed, and the Al in the connection hole (Via) area is retained. Since it is necessary to ensure that there is no Al residue in other areas, it is necessary to etch down to a certain depth as much as possible. At this time, the top layer OX (oxide) of the passivation layer plays the role of a sacrificial layer. By sacrificing the film thickness of the top layer OX (oxide) itself, the three-layer structure below is protected to maintain the basic performance of the Al pad (Aluminum Pad).

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing an aluminum pad for a semiconductor chip, characterized in that: The following steps are involved: S1. Providing a semiconductor substrate, wherein the upper surface of the semiconductor substrate is a top metal layer (100) that has been grown; S2. depositing a passivation layer on the top metal layer (100), wherein the passivation layer is a four-layer structure of SiN-OX-SiN-OX from bottom to top; S3. Removing the passivation layer in the connection hole region, and retaining the passivation layer outside the connection hole region; S4. Performing aluminum pad layer process; S5. Photolithography and etching are performed to remove aluminum in areas where aluminum is not needed and to retain aluminum in the connection hole area; thus, the preparation of the aluminum pad is completed.

2. The method for manufacturing a semiconductor chip aluminum pad according to claim 1, characterized in that: The semiconductor chip is a SONOS memory.

3. The method for manufacturing a semiconductor chip aluminum pad according to claim 1, characterized in that: In step S3, a connection hole region is defined through an RV process, the passivation layer in the connection hole region is removed, and the passivation layer outside the connection hole region is retained.

4. The method for manufacturing a semiconductor chip aluminum pad according to claim 3, characterized in that: The RV process includes distributed through-hole photoresist development and distributed through-hole etching; By developing the distributed through-hole photoresist (105), a connection hole area is defined; The passivation layer in the connection hole area is removed by distributing the through hole etching process, and the passivation layer outside the connection hole area is retained.

5. The method for manufacturing a semiconductor chip aluminum pad according to claim 1, characterized in that: The aluminum pad layer process includes aluminum line formation and aluminum deposition.

6. The method for manufacturing a semiconductor chip aluminum pad according to claim 1, characterized in that: In step S2, depositing a passivation layer on the top metal layer (100) comprises the following steps: S21. Depositing a first SiN layer (101) on the top metal layer (100); S22. Depositing a first OX layer (102) on the first SiN layer (101); S23. Depositing a second SiN layer (103) on the first OX layer (102); S24. Depositing a second OX layer (104) on the second SiN layer (103).

7. The method for manufacturing a semiconductor chip aluminum pad according to claim 6, characterized in that: The first SiN layer (101), the first OX layer (102), the second SiN layer 10, and the second OX layer (104) are formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

8. The method for manufacturing a semiconductor chip aluminum pad according to claim 6, characterized in that: The first SiN layer (101) has a thickness of 800nm ​​to 1200nm; The first OX layer (102) has a thickness of 6800nm ​​to 7200nm; The second SiN layer (103) has a thickness of 3800nm ​​to 4200nm; The second OX layer (104) has a thickness of 1000 nm to 5000 nm.

9. The method for manufacturing a semiconductor chip aluminum pad according to claim 1, characterized in that: In step S4, the aluminum pad layer process adopts physical vapor deposition, first depositing the TaN / Ti / TiN layer (106) and then depositing the Al layer (107).

10. The method for manufacturing a semiconductor chip aluminum pad according to claim 1, characterized in that: The top metal layer (100) is metal Cu.

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