Packaging body with high heat dissipation performance and preparation method thereof

Abstract

The invention relates to a packaging body with high heat dissipation performance and a preparation method thereof, the packaging body with high heat dissipation performance comprises a substrate, a chip and a plastic packaging layer, and the plastic packaging layer covers the substrate and the chip. At least one layer of heat dissipation channel is arranged in the plastic package layer, and the heat dissipation channel penetrates from one side of the plastic package layer to the other side of the plastic package layer. As the heat dissipation channel penetrates through the plastic package layer, gas or liquid or a material with better heat dissipation can be introduced to take away or lead out heat generated by the chip, thereby effectively improving the heat dissipation capability of the product.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a package with high heat dissipation performance and a preparation method thereof. Background Art

[0002] For some packaging structure products, a plastic layer is formed on one side of the chip to protect the circuit inside the chip from being affected by the external environment.

[0003] For this type of product, the traditional process is usually to directly form a plastic encapsulation material on one side of the chip, and then solidify it to form a plastic encapsulation layer. However, the product formed in this way has poor heat dissipation performance. Summary of the invention

[0004] Based on this, the present application provides a high heat dissipation package and a preparation method thereof that can improve the heat dissipation performance of a product.

[0005] A package with high heat dissipation performance, comprising:

[0006] substrate;

[0007] A chip, located on one side of the substrate;

[0008] The plastic sealing layer covers the substrate and the chip. The plastic sealing layer is provided with at least one heat dissipation channel, and the heat dissipation channel runs from one side of the plastic sealing layer to the other side of the plastic sealing layer.

[0009] In one embodiment, the plastic encapsulation layer includes n sub-plastic encapsulation layers, and the side of the i-th sub-plastic encapsulation layer away from the substrate has a first groove, wherein n≥2, 1≤i<n, and n and i are positive integers;

[0010] The heat dissipation channel is located between the first groove and the (i+1)th sub-plastic packaging layer.

[0011] In one embodiment, a side of the (i+1)th sub-molding layer close to the (i)th sub-molding layer has a second groove, and an orthographic projection of the second groove on the substrate overlaps with an orthographic projection of the first groove on the substrate;

[0012] The heat dissipation channel is located between the first groove and the second groove.

[0013] In one embodiment, the plastic encapsulation layer further includes:

[0014] a first lining layer, covering an inner wall of the first groove;

[0015] The second lining layer covers the inner wall of the second groove, and the heat dissipation channel is located between the first lining layer and the second lining layer.

[0016] In one embodiment, the plastic encapsulation layer further includes:

[0017] a first lining layer, covering an inner wall of the first groove;

[0018] The first isolation film is located on a side of the first liner layer away from the substrate, and the heat dissipation channel is located between the first liner layer and the first isolation film in the first groove.

[0019] In one embodiment, the plastic encapsulation layer further includes:

[0020] A third groove, located at at least one side of the first groove, passes through the first isolation film and exposes a portion of the i-th sub-plastic sealing layer;

[0021] The (i+1)th sub-molding layer fills the third groove and covers the (i)th sub-molding layer.

[0022] In one embodiment, the plastic encapsulation layer further includes a fourth liner layer, and the fourth liner layer is located between the first isolation film and the (i+1)th sub-plastic encapsulation layer;

[0023] The third groove passes through the fourth liner layer and the first isolation film.

[0024] In one embodiment, the first liner layer further covers the surface of the i-th sub-molding layer outside the first groove and away from the substrate;

[0025] The third groove passes through the first isolation film and the first liner layer.

[0026] In one embodiment, the plastic encapsulation layer further includes:

[0027] The heat dissipation structure is located in the heat dissipation channel.

[0028] In one of the embodiments, carbon nanotubes are disposed in the plastic sealing layer, the carbon nanotubes extend from one side of the plastic sealing layer to the other side of the plastic sealing layer, and the heat dissipation channel is located in the carbon nanotubes.

[0029] A method for preparing a package with high heat dissipation performance, comprising:

[0030] providing a substrate;

[0031] forming a chip on one side of the substrate;

[0032] Forming an i-th sub-plastic encapsulation layer on the side of the substrate where the chip is formed, wherein the i-th sub-plastic encapsulation layer has a first groove on a side away from the substrate;

[0033] The i+1th sub-plastic encapsulation layer is formed on the i-th sub-plastic encapsulation layer to form a heat dissipation channel between the first groove and the i+1th sub-plastic encapsulation layer, wherein 1≤i<n, n≥2, and n and i are positive integers.

[0034] In one embodiment, the thickness of the first sub-plastic encapsulation layer is less than the height of the chip, and after the first sub-plastic encapsulation layer is formed, the method includes:

[0035] A second isolation film is attached along the surface of the first sub-molding layer away from the substrate and the surface of the chip;

[0036] Performing a reverse molding process on the second isolation film to form a first mold;

[0037] Forming a second sub-molding layer based on the first mold, wherein the second sub-molding layer has a second groove;

[0038] forming a first lining layer on the inner wall of the first groove of the first sub-molding layer;

[0039] forming a second lining layer on the inner wall of the second groove of the second sub-molding layer;

[0040] The second sub-molding layer is invertedly placed on the first sub-molding layer and compounded.

[0041] In one embodiment, before forming the (i+1)th sub-plastic encapsulation layer on the (i)th sub-plastic encapsulation layer, the method includes:

[0042] forming a first liner layer on a side of the i-th sub-molding layer away from the substrate;

[0043] forming a first isolation film on a side of the first liner layer away from the substrate, wherein the heat dissipation channel is located between the first liner layer and the first isolation film in the first groove;

[0044] A fourth liner layer is formed on a side of the first isolation film away from the substrate.

[0045] In one embodiment, after forming the fourth liner layer on the side of the first isolation film away from the substrate, the method includes:

[0046] At least one side of the first groove is etched to form a third groove that penetrates the fourth liner layer, the first isolation film, and the first liner layer and exposes a portion of the i-th sub-molding layer.

[0047] The above-mentioned high heat dissipation package provided by the present application includes a substrate, a chip and a plastic sealing layer, and the plastic sealing layer covers the substrate and the chip. At least one heat dissipation channel is provided in the plastic sealing layer, and the heat dissipation channel runs from one side of the plastic sealing layer to the other side of the plastic sealing layer. Since the heat dissipation channel runs through the plastic sealing layer, gas or liquid or a material with better heat dissipation can be introduced to take away or export the heat generated by the chip, thereby effectively increasing the heat dissipation capacity of the product.

[0048] At the same time, the method for preparing a package with high heat dissipation performance of the present application forms a heat dissipation channel between the i-th sub-plastic encapsulation layer and the i+1-th sub-plastic encapsulation layer, and at least one layer of heat dissipation channel can be obtained. The heat generated by the chip is taken away or exported by passing gas or liquid or a material with better heat dissipation into the heat dissipation channel, thereby achieving the purpose of improving the heat dissipation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 A schematic diagram of a cross-sectional structure of a package body with high heat dissipation provided in an embodiment;

[0051] Figures 2 to 14 is a schematic structural diagram of a plastic sealing layer provided in an embodiment;

[0052] Fig.15 A schematic cross-sectional structure diagram of a package body with high heat dissipation provided in another embodiment;

[0053] Fig.16 is a flow chart of a method for preparing a package with high heat dissipation performance provided in one embodiment;

[0054] Figures 17 to 42 The cross-sectional structure schematic diagram of the structure obtained in each step of the method for preparing a package with high heat dissipation provided in one embodiment.

[0055] Description of the reference numerals: 01-substrate, 02-chip, 03-plastic layer, 04-heat dissipation channel, 05-first groove, 06-second groove, 07-first pad layer, 08-second pad layer, 09-first isolation film, 10-third groove, 11-fourth pad layer, 12-heat dissipation structure, 13-carbon nanotube, 011-intermediate layer structure, 0111-intermediate layer substrate, 011a-intermediate layer initial structure, 0111a-intermediate layer initial sheet, 0112-wiring layer, 0113-conductive Through-hole structure, 0113a-conductive initial structure, 0115-first soldering pad, 0116-second soldering pad, 14-external circuit module, 141-passive device, 142-external plug-in, 1411-voltage management module, 1412-connector, 0114-protective layer, 0114a-protective material layer, 16-heat sink, 161-graphene double-sided tape, 17-first fixing hole, 18-fixing part, 19-first carrier board, 20-second carrier board, 21-annular space, 22-supporting plate. DETAILED DESCRIPTION

[0056] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0058] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0059] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0060] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0061] In one embodiment, see Figure 1 , provides a high heat dissipation package, which includes a substrate 01, a chip 02 and a plastic packaging layer 03.

[0062] The substrate 01 may be a silicon interposer. The chip 02 is located on one side of the substrate 01 .

[0063] The plastic encapsulation layer 03 covers the substrate 01 and the chip 02 . At least one layer of heat dissipation channel 04 may be provided in the plastic encapsulation layer 03 . The heat dissipation channel 04 runs from one side of the plastic encapsulation layer 03 to the other side of the plastic encapsulation layer 03 .

[0064] The heat dissipation channel 04 may include a microchannel, and gas or liquid, such as nitrogen or coolant, may be passed into the through heat dissipation channel 04 to increase the heat dissipation effect.

[0065] The shape of the heat dissipation channel 04 can be straight or serpentine (see Figure 2 or Figure 3 ). The heat dissipation channels 04 of the same layer may be arranged crosswise or staggered, and the orthographic projections of the heat dissipation channels 04 of different layers may at least partially overlap.

[0066] In this embodiment, at least one layer of heat dissipation channel 04 is provided, and the heat dissipation channel 04 runs through one side of the plastic encapsulation layer 03 to the other side of the plastic encapsulation layer 03. Since the heat dissipation channel 04 runs through the plastic encapsulation layer 03, gas or liquid or a material with better heat dissipation can be passed through to take away or output the heat generated by the chip 02, thereby effectively increasing the heat dissipation capacity of the product.

[0067] In one embodiment, the plastic sealing layer 03 includes n layers of sub-plastic sealing layers 031 , where n≥2 and n is a positive integer, for example, there may be 2 layers of sub-plastic sealing layers 031 , 3 layers of sub-plastic sealing layers 031 , 4 layers of sub-plastic sealing layers 031 , etc.

[0068] The side of the i-th sub-molding layer 031a away from the substrate 01 has a first groove 05 (see Figure 4 ), 1≤i<n, and i is a positive integer. For example, when there are two sub-molding layers 031 , the first sub-molding layer 031 has a first groove 05 on a side away from the substrate 01 .

[0069] The first groove 05 may include but is not limited to a semicircular groove. The heat dissipation channel 04 is located between the first groove 05 and the (i+1)th sub-plastic encapsulation layer 031b (see Figure 5 ). The first groove 05 can be formed by cutting or scoring.

[0070] In this embodiment, the first groove 05 can accommodate the heat dissipation channel 04, so that the heat dissipation channel 04 can be arranged between the i-th sub-plastic packaging layer 031a and the (i+1)-th sub-plastic packaging layer 031b.

[0071] In one embodiment, a side of the i+1-th sub-molding layer 031b close to the i-th sub-molding layer 031a has a second groove 06 (see Figure 6 ). The second groove 06 can be formed by cutting or scoring.

[0072] The orthographic projection of the second groove 06 on the substrate 01 overlaps with the orthographic projection of the first groove 05 on the substrate 01 , and at this time, a heat dissipation channel 04 is formed between the second groove 06 and the first groove 05 .

[0073] In this embodiment, compared with only providing the first groove 05 , the cross-sectional area of ​​the heat dissipation channel 04 is increased, thereby further improving the heat dissipation performance.

[0074] In one embodiment, see Figure 7 The plastic encapsulation layer 03 further includes: a first liner layer 07, and the material of the first liner layer 07 may include but is not limited to SiO2 material.

[0075] The first liner layer 07 covers the inner wall of the first groove 05 and serves as a supporting wall for the i-th sub-plastic packaging layer 031 a to ensure that the heat dissipation channel 04 will not be fused.

[0076] The material of the second liner layer 08 may include but is not limited to SiO 2 material.

[0077] The second lining layer 08 covers the inner wall of the second groove 06 and serves as a supporting wall of the (i+1)th sub-plastic packaging layer 031 b to ensure that the heat dissipation channel 04 will not collapse.

[0078] In this embodiment, the first pad layer 07 and the second pad layer 08 serve as support walls, and the heat dissipation channel 04 is disposed in the plastic packaging layer 03. At this time, since the heat dissipation channel 04 is located between the first pad layer 07 and the second pad layer 08, the hardness and stability of the heat dissipation channel 04 are increased.

[0079] In one embodiment, see Figure 8 The plastic encapsulation layer 03 further includes: a first liner layer 07, and the material of the first liner layer 07 may include but is not limited to SiO2 material.

[0080] The first liner layer 07 covers the inner wall of the first groove 05 and serves as a supporting wall for the i-th sub-plastic packaging layer 031 a to ensure that the heat dissipation channel 04 will not be fused.

[0081] In addition, a first isolation film 09 is provided on the side of the first liner layer 07 away from the substrate 01, and the heat dissipation channel 04 is located between the first liner layer 07 and the first isolation film 09 in the first groove 05, that is, the first groove 05 between the first isolation film 09 and the first liner layer 07 is the heat dissipation channel 04. In addition, the first liner layer 07 can also fully cover the i-th sub-plastic encapsulation layer 031a, and there is no specific limitation (please refer to Fig. 9 ).

[0082] In this embodiment, the first isolation film 09 can isolate the (i+1)th sub-plastic encapsulation layer 031 b from the first liner layer 07 , and serve as a support wall to provide a basis for the formation of the heat dissipation channel 04 .

[0083] In one embodiment, see Fig.10 The plastic encapsulation layer 03 further includes: a third groove 10, and the third groove 10 can be formed by etching.

[0084] The third groove 10 is located on at least one side of the first groove 05 , extends in a direction perpendicular to the substrate 01 , penetrates the first isolation film 09 and etches a portion of the i-th sub-plastic encapsulation layer 031 a to expose a portion of the i-th sub-plastic encapsulation layer 031 a .

[0085] At this time, when the i+1th sub-molding layer 031 b is formed, the i+1th sub-molding layer 031 b fills the third groove 10 and covers the i-th sub-molding layer 031 a.

[0086] In this embodiment, the third groove 10 can increase the packaging firmness of the i+1th sub-plastic encapsulation layer 031b and the i-th sub-plastic encapsulation layer 031a, and further improve the composite effect of the i+1th sub-plastic encapsulation layer 031b and the i-th sub-plastic encapsulation layer 031a.

[0087] In one embodiment, see Fig.11 and Fig.12 The plastic encapsulation layer 03 further includes a fourth liner layer 11, and the material of the fourth liner layer 11 may include but is not limited to SiO2 material.

[0088] The fourth liner layer 11 is located between the first isolation film 09 and the (i+1)th sub-plastic sealing layer 031 b and serves as a supporting wall of the (i+1)th sub-plastic sealing layer 031 b to ensure that the heat dissipation channel 04 does not collapse.

[0089] When the fourth liner layer 11 is provided, the third groove 10 penetrates the fourth liner layer 11 and the first isolation film 09, and etches part of the i-th sub-plastic encapsulation layer 031a to expose part of the i-th sub-plastic encapsulation layer 031a. In this way, the composite effect of the i+1-th sub-plastic encapsulation layer 031b and the i-th sub-plastic encapsulation layer 031a can be increased.

[0090] In this embodiment, the fourth liner layer 11 serves as a support wall for the (i+1)th sub-plastic encapsulation layer 031 b , which can prevent the (i+1)th sub-plastic encapsulation layer 031 b from causing the first isolation film 09 to collapse, thereby preventing the heat dissipation channel 04 from collapsing.

[0091] In one embodiment, see Fig.13 The plastic sealing layer 03 further includes: a heat dissipation structure 12. The material of the heat dissipation structure 12 may be a material with good thermal conductivity, including but not limited to thermal conductive metal materials.

[0092] The heat dissipation structure 12 is located in the heat dissipation channel 04. At this time, the heat generated by the chip 02 can be conducted out through the heat dissipation structure 12, thereby improving the heat dissipation performance of the product. It should be noted that the shape of the heat dissipation structure 12 is not specifically limited, and can be filled and set according to the shape of the heat dissipation channel 04. For example, when the cross-section of the heat dissipation channel 04 is a circular channel, the cross-section of the heat dissipation structure 12 is circular; when the cross-section of the heat dissipation channel 04 is a semicircular channel, the cross-section of the heat dissipation structure 12 is semicircular.

[0093] In one embodiment, see Fig.14 The plastic sealing layer 03 is provided with carbon nanotubes 13, and the carbon nanotubes 13 are hollow structures.

[0094] The carbon nanotubes 13 extend from one side of the plastic encapsulation layer 03 to the other side of the plastic encapsulation layer 03 , that is, the interior formed by the carbon nanotubes 13 is the heat dissipation channel 04 .

[0095] In this embodiment, the carbon nanotubes 13 are used as the support wall of the heat dissipation channel 04 , which can make the preparation of the heat dissipation channel 04 easier.

[0096] It should be noted that in the above-mentioned high heat dissipation package, refer to Fig.15 The substrate 01 may be an interposer structure 011 , and the interposer structure 011 includes an interposer substrate 0111 , a wiring layer 0112 , and a conductive through-hole structure 0113 .

[0097] The interposer structure 011 may include but is not limited to a silicon interposer. The interposer substrate 0111 may include but is not limited to a silicon wafer.

[0098] The wiring layer 0112 is located on one side of the interposer substrate 0111. One side of the interposer substrate 0111 may be provided with multiple interconnected wiring layers 0112, and an insulating dielectric layer may be provided between adjacent wiring layers 0112. It should be noted that the figure only simply illustrates a partial structure of the wiring layer 0112.

[0099] The conductive via structure 0113 penetrates the interposer substrate 0111 and connects the wiring layer 0112. The material of the conductive via structure 0113 may include but is not limited to metal materials such as copper.

[0100] The chip 02 is located on one side of the substrate 01 .

[0101] A plurality of chips 02 may be disposed on a side of the wiring layer 0112 away from the interposer substrate 0111. The chips 02 may be electrically connected to the wiring layer 0112. The plurality of chips 02 may be disposed at intervals. Different chips 02 may have different functions.

[0102] The plastic encapsulation layer 03 covers the chip 02 and the interposer structure 011, thereby performing plastic encapsulation protection on the chip 02. The material of the plastic encapsulation layer 03 may include, but is not limited to, epoxy molding compound (EMC).

[0103] See also Fig.26 The interposer structure 011 further includes a protective layer 0114. The material of the protective layer 0114 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride.

[0104] The protection layer 0114 is located on a side of the interposer substrate 0111 away from the wiring layer 0112 , and the conductive via structure 0113 penetrates the protection layer 0114 and the interposer substrate 0111 .

[0105] The protection layer 0114 can prevent metal in the conductive via structure 0113 from entering the interposer substrate 0111 , thereby preventing leakage between adjacent conductive via structures 0113 .

[0106] The interposer structure 011 further includes a first pad 0115. The material of the first pad 0115 may include but is not limited to copper.

[0107] The first pad 0115 is located on the surface of the wiring layer 0112 and may cover at least a portion of the wiring layer 0112 , thereby being electrically connected to the wiring layer 0112 .

[0108] The chip 02 is surface mounted or hybrid bonded to the first pad 0115 .

[0109] The interposer structure 011 further includes a second pad 0116 .

[0110] The second pad 0116 is located on a side of the interposer substrate 0111 away from the wiring layer 0112 and covers the conductive via structure 0113, thereby being electrically connected to the conductive via structure 0113. The material of the second pad 0116 may include but is not limited to copper, etc. The number of the second pad 0116 may be multiple.

[0111] See also Fig.41 The side of the substrate 01 away from the chip 02 also includes an external circuit module 14 , and the external circuit module 14 includes a passive device 141 and an external plug-in 142 .

[0112] The passive component 141 is mounted to a portion of the second pad 0116. The passive component 141 can be directly mounted to the second pad 0116 by SMD mounting. Meanwhile, the package with high heat dissipation performance can also have another portion of the second pad 0116 not covered by the passive component 141.

[0113] The external plug-in 142 is electrically connected to the second pad 0116 , and may include but is not limited to a voltage management module 1411 and / or a connector 1412 .

[0114] See also Fig.42 The high heat dissipation package further includes a heat dissipation plate 16 , a first fixing hole 17 and a fixing member 18 .

[0115] The heat sink 16 is located on a side of the plastic packaging layer 03 away from the intermediate layer structure 011. As an example, the heat sink 16 can be bonded to the plastic packaging layer 03 by using a graphene double-sided adhesive 161.

[0116] The first fixing hole 17 passes through the intermediate layer structure 011 and the plastic packaging layer 03 .

[0117] The fixing member 18 passes through the first fixing hole 17 to fix the heat sink 16. The fixing member 18 may include but is not limited to bolts and the like.

[0118] After passing through the first fixing hole 17 , the fixing member 18 may not penetrate the heat dissipation plate 16 , or may penetrate the heat dissipation plate 16 .

[0119] As an example, the package with high heat dissipation may also include a mechanical frame, etc. The mechanical frame may be located on a side of the external circuit module 14 away from the interposer structure 011. A second fixing hole may also be provided in the mechanical frame. The second fixing hole may be arranged opposite to the first fixing hole 17. The fixing member 18 may also pass through the second fixing hole at the same time, thereby fixing the mechanical frame and the heat dissipation plate 16 at the same time.

[0120] The fixing member 18 can make the connection between the heat sink 16 and the plastic packaging layer 03 more reliable.

[0121] In one embodiment, see Fig.16 , a method for preparing a package with high heat dissipation performance is provided, comprising the following steps:

[0122] Step S10, providing a substrate 01.

[0123] The substrate 01 may be an interposer structure 011 (see Fig.15 ).

[0124] Step S20 , forming a chip 02 on one side of the substrate 01 .

[0125] A plurality of chips 02 may be formed on one side of the substrate 01. The chips 02 may be electrically connected to the substrate 01. The plurality of chips 02 may be arranged at intervals. Different chips 02 may have different functions.

[0126] Step S30, forming an i-th sub-molding layer 031a on the side of the substrate 01 where the chip 02 is formed, and the i-th sub-molding layer 031a has a first groove 05 on the side away from the substrate 01 (see Fig.17 ).

[0127] A plurality of first grooves 05 may be formed on one side of the i-th sub-plastic encapsulation layer 031a, and may be formed by cutting or notching. It should be noted that the i-th sub-plastic encapsulation layer 031a here first forms the first sub-plastic encapsulation layer 031, and then forms subsequent layers in sequence. The number of first grooves 05 on different sub-plastic encapsulation layers 031 may be the same or different. The orthographic projection of the first grooves 05 of different layers is also not specifically limited.

[0128] After each sub-plastic encapsulation layer 031 is formed, it needs to be cured.

[0129] Step S40, forming the i+1th sub-plastic layer 031b on the i-th sub-plastic layer 031a to form a heat dissipation channel 04 between the first groove 05 and the i+1th sub-plastic layer 031b, wherein 1≤i<n, n≥2, and n and i are positive integers (see Fig.18 ).

[0130] The i+1th sub-plastic sealing layer 031b is formed on the i-th sub-plastic sealing layer 031a. At this time, a heat dissipation channel 04 is formed between the first groove 05 and the i+1th sub-plastic sealing layer 031b. The heat dissipation channel 04 can be a hollow microchannel or include a heat dissipation structure 12 arranged in the heat dissipation channel 04.

[0131] The shape of the heat dissipation channel 04 can be linear or serpentine, etc. The heat dissipation channels 04 on the same layer can be arranged crosswise or staggered, and the orthographic projections of the heat dissipation channels 04 on different layers can overlap partially or completely.

[0132] In this embodiment, a heat dissipation channel 04 is formed between the i-th sub-plastic encapsulation layer 031a and the i+1-th sub-plastic encapsulation layer 031b, and at least one layer of heat dissipation channel 04 can be obtained. The heat generated by the chip 02 is taken away or exported by passing gas or liquid or a material with better heat dissipation into the heat dissipation channel 04, thereby achieving the purpose of improving the heat dissipation performance.

[0133] In one embodiment, step S10 includes:

[0134] Step S101 , providing a first carrier board 19 .

[0135] The first carrier plate 19 is a carrier plate that can be used for support. The material of the first carrier plate 19 can include but is not limited to a glass plate, a metal plate or a plastic plate.

[0136] Step S102, forming an interposer structure 011 on the first carrier 19, the interposer structure 011 comprising an interposer substrate 0111, a wiring layer 0112 and a conductive via structure 0113, the wiring layer 0112 being located on a side of the interposer substrate 0111 away from the first carrier 19, and the conductive via structure 0113 penetrating the interposer substrate 0111 and connecting the wiring layer 0112 (see Fig.28 ).

[0137] The interposer structure 011 may include but is not limited to a silicon interposer. The interposer substrate 0111 may include but is not limited to a silicon wafer. The material of the conductive via structure 0113 may include but is not limited to metal materials such as copper.

[0138] One side of the interposer substrate 0111 may be provided with multiple interconnected wiring layers 0112, and an insulating dielectric layer may be provided between adjacent wiring layers 0112. It should be noted that the figure only simply illustrates a partial structure of the wiring layer 0112.

[0139] Step S102 includes:

[0140] Step S1021, providing an interposer initial structure 011a, the interposer initial structure 011a comprising an interposer initial sheet 0111a, a wiring layer 0112 and a conductive initial structure 0113a, wherein the wiring layer 0112 is located on one side of the interposer initial sheet 0111a, and the conductive initial structure 0113a extends inward from the side of the interposer initial sheet 0111a where the wiring layer 0112 is located (see Fig.19 ).

[0141] In the interposer initial structure 011a, one end of the conductive initial structure 0113a may be connected to the wiring layer 0112. Meanwhile, the other end of the conductive initial structure 0113a may extend to the inside of the interposer initial sheet 0111a, but does not penetrate the interposer initial sheet 0111a.

[0142] Step S1022, forming a first pad 0115 on the wiring layer 0112 (see Fig. 20 ), and the side of the initial structure of the interposer 011a where the first pad 0115 is formed is bonded to the second carrier 20 (see Fig. 22 ).

[0143] The material of the first pad 0115 may include, but is not limited to, copper, etc. The first pad 0115 may cover at least a portion of the wiring layer 0112 , thereby being electrically connected to the wiring layer 0112 .

[0144] After the initial structure of the interposer 011 a is bonded to the second carrier 20 , the second carrier 20 may serve as a support for subsequent processes.

[0145] Step S1023, etching the side of the interposer initial sheet 0111a away from the wiring layer 0112 to expose the conductive initial structure 0113a, and the remaining interposer initial sheet 0111a forms the interposer substrate 0111, and the conductive initial structure 0113a protrudes from the surface of the interposer substrate 0111 (see Fig.23 ).

[0146] The interposer initial sheet 0111a may be etched and thinned from the side away from the wiring layer 0112 by dry etching process, etc., until the thickness of the remaining interposer initial sheet 0111a (interposer substrate 0111) is smaller than the height of the conductive initial structure 0113a.

[0147] Step S1024, forming a protective material layer 0114a covering the conductive initial structure 0113a and the intermediate layer substrate 0111 (see Fig.24 ).

[0148] The protective material layer 0114a may be formed by a deposition process (such as chemical vapor deposition or atomic layer deposition, etc.). The material of the protective material layer 0114a may include but is not limited to silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0149] Step S1025, grinding the conductive initial structure 0113a and the protective material layer 0114a to grind the protruding portion of the conductive initial structure 0113a flat, and the remaining conductive initial structure 0113a forms a conductive through-hole structure 0113, and the remaining protective material layer 0114a forms a protective layer 0114 (see Fig.25 ).

[0150] Before grinding, the surface of the interposer substrate 0111 is covered by the protective material layer 0114a. Therefore, during the grinding process, the protective material layer 0114a can prevent the metal of the conductive initial structure 0113a from entering the interposer substrate 0111, thereby preventing leakage between adjacent conductive via structures 0113.

[0151] Step S1026, forming a second pad 0116 covering the conductive through-hole structure 0113 and the protective layer 0114, (see Fig.26 ) to form an interposer structure 011, and the side of the interposer structure 011 forming the second pad 0116 is bonded to the first carrier 19 (see Fig. 27 ).

[0152] The material of the second pad 0116 may include, but is not limited to, copper, etc. After the second pad 0116 is formed, the preparation of the interposer structure 011 may be completed.

[0153] After the interposer initial structure 011 a is bonded to the first carrier 19 , the first carrier 19 and the second carrier 20 may be disposed opposite to each other.

[0154] Step S1027, remove the second carrier board 20 (see Fig.28 ).

[0155] The second carrier board 20 may be removed by laser lift-off or the like.

[0156] After the second carrier 20 is removed, the first carrier 19 can be used as a support for subsequent processes.

[0157] In one embodiment, step S20 includes:

[0158] Step S201, forming a chip 02 on a side of the wiring layer 0112 away from the interposer substrate 0111 (see Fig.29 ).

[0159] In one embodiment, step S1022 includes:

[0160] Step S1122 , forming a first pad 0115 on the wiring layer 0112 .

[0161] First, a first patterned dielectric layer may be formed by a photolithography process, etc., and the first patterned dielectric layer has a first opening. The material of the first patterned dielectric layer may include, but is not limited to, PI. Then, a first patterned photoresist layer may be formed on the first patterned dielectric layer. The first patterned photoresist layer has a second opening, and the second opening is arranged opposite to the first opening. Then, a first pad 0115 may be formed in the second opening and the first opening by an electroplating process, etc., and the first patterned photoresist layer is removed.

[0162] Step S1222, the structure after forming the first pad 0115 is circularly cut to form a circular cutting space 21 (see Fig.21 ).

[0163] During the ring cutting, a portion of the thickness of the edge of the initial intermediate layer sheet 0111 a may be cut off.

[0164] As an example, the depth of the cutout of the interposer initial piece 0111 a may be greater than the height of the conductive initial structure 0113 a .

[0165] Step S1322, forming a first adhesive layer 0115a on the side of the annular space 21 and the initial structure 011a of the intermediate layer where the first pad 0115 is formed (see Fig. 22 ).

[0166] Step S1422 , bonding the second carrier 20 via the first adhesive layer 0115 a .

[0167] Thereafter, the first adhesive layer 0115a may be cured.

[0168] The formation of the annular space 21 facilitates the initial structure of the intermediate layer 011 a to be more firmly adhered to the second carrier board 20 .

[0169] At the same time, step S1023 etches the side of the initial interposer sheet 0111a away from the wiring layer 0112 to expose the initial conductive structure 0113a and remove the first adhesive layer 0115a located in the annular space 21. At this time, the annular space 21 can be hollowed out again.

[0170] When the cutting depth of the initial sheet 0111a of the intermediate layer in step S1222 can be greater than the height of the conductive initial structure 0113a, it can be ensured that step S1023 can etch the initial sheet 0111a of the intermediate layer to expose the first adhesive layer in the annular space 21, and then the first adhesive layer 0115a in the annular space 21 can be effectively etched and removed.

[0171] Step S1026 includes:

[0172] Step S1126, forming a second pad 0116 covering the conductive via structure 0113 and the protective layer 0114 to form the interposer structure 011 (see Fig.26 ).

[0173] The second pad 0116 may be formed in a similar manner to the first pad 0115 .

[0174] First, a second patterned dielectric layer may be formed by a photolithography process, etc., and the second patterned dielectric layer has a third opening. The material of the second patterned dielectric layer may include, but is not limited to, PI. Then, a second patterned photoresist layer may be formed on the second patterned dielectric layer. The second patterned photoresist layer has a fourth opening, and the fourth opening is arranged opposite to the third opening. Then, a second pad 0116 may be formed in the fourth opening and the third opening by an electroplating process, etc., and the second patterned photoresist layer is removed.

[0175] Step S1226, forming a second adhesive layer 0116a on the annular space 21 and on the side of the interposer structure 011 where the second pad 0116 is formed (see Fig. 27 ).

[0176] Step S1326, bonding the first carrier board 19 via the second adhesive layer 0116a.

[0177] Thereafter, the second adhesive layer 0116a may be cured.

[0178] At this time, the annular space 21 facilitates the initial structure of the intermediate layer 011 a to be more firmly adhered to the first carrier board 19 .

[0179] Then, the structure in the area corresponding to the annular space 21 can be completely removed. Then, in step S1027, the second carrier 20 is removed. In step S1027, after the second carrier 20 is removed, the first adhesive layer 0115a can be removed to expose the first pad 0115 (see Fig.28 ).

[0180] Meanwhile, after step S40, the method further includes:

[0181] Step S50, remove the first carrier plate 19 (see Fig.40).

[0182] The first carrier 19 may be removed by laser lift-off or the like, thereby exposing a side of the interposer structure 011 away from the chip 02 .

[0183] After the first carrier 19 is removed, the second adhesive layer 0116 a may be removed to expose the second pad 0116 .

[0184] In one embodiment, see Fig.30 The thickness of the first sub-plastic encapsulation layer 031 is less than the height of the chip 02. After the first sub-plastic encapsulation layer 031 is formed, the method includes:

[0185] Step S410 , attaching a second isolation film (not shown in the figure) along the surface of the first sub-molding layer 031 away from the substrate 01 and the surface of the chip 02 .

[0186] Since the heat dissipation channel 04 is located in the plastic encapsulation layer 03, the thickness of the first sub-plastic encapsulation layer 031 is less than the height of the chip 02. The first sub-plastic encapsulation layer 031 has a first groove 05. A second isolation film is attached along the surface of the first sub-plastic encapsulation layer 031 away from the substrate 01 and the surface of the chip 02, and the second isolation film is also attached to the inner wall of the first groove 05.

[0187] Step S412, performing a mold-inverting process on the second isolation film to form a first mold.

[0188] The second isolation film is subjected to a reverse molding process, and the second isolation film can make it easier to demould the first mold formed subsequently.

[0189] Step S413 , forming a second sub-molding layer 031 based on the first mold, wherein the second sub-molding layer 031 has a second groove 06 .

[0190] The first mold is fitted with the shape of the first sub-molding layer 031 . When the second sub-molding layer 031 is formed based on the first mold, the second groove 06 on the second sub-molding layer 031 can correspond to the first groove 05 on the first sub-molding layer 031 , thereby forming a heat dissipation channel 04 .

[0191] Step S414 , forming a first lining layer 07 on the inner wall of the first groove 05 of the first sub-molding layer 031 .

[0192] After forming the first mold, the second isolation film is peeled off, and in order to ensure that the first groove 05 will not be fused, a first liner layer 07 is formed on the inner wall of the first groove 05. The hardness of the first groove 05 is increased to ensure the formation of the heat dissipation through hole.

[0193] Forming the first liner layer 07 includes:

[0194] Step S4141 , forming a first liner material layer covering the first sub-plastic encapsulation layer 031 .

[0195] Step S4142, removing the first liner material layer outside the first groove 05, and the remaining

[0196] The first pad material layer is the first pad layer 07 .

[0197] Step S415 , forming a second lining layer 08 on the inner wall of the second groove 06 of the second sub-molding layer 031 .

[0198] A second liner layer 08 is formed on the inner wall of the second groove 06. The second liner layer 08 is formed in the same manner as the first liner layer 07, including:

[0199] Step S4151 , forming a second liner material layer covering the second sub-plastic encapsulation layer 031 .

[0200] Step S4152, removing the second liner material layer outside the second groove 06, and the remaining second liner material layer inside the second groove 06

[0201] The second pad material layer is the second pad layer 08 .

[0202] The provision of the second liner layer 08 can ensure that the heat dissipation channel 04 will not collapse.

[0203] Step S416, placing the second sub-molding layer 031 upside down on the first sub-molding layer 031 and compounding them.

[0204] The formed second sub-plastic sealing layer 031 is inverted on the first sub-plastic sealing layer 031 and laminated. The lamination may include but is not limited to lamination by adhesive or lamination by hot pressing.

[0205] In this embodiment, the first sub-plastic encapsulation layer 031 and the second sub-plastic encapsulation layer 031 are formed by reverse molding, and the first sub-plastic encapsulation layer 031 and the second sub-plastic encapsulation layer 031 are both hard films. At this time, if adhesive bonding is used, the first liner layer 07 and the second liner layer 08 may not be provided, and the heat dissipation channel 04 can be formed. If hot pressing bonding is used, the first liner layer 07 and the second liner layer 08 need to be provided to ensure that the heat dissipation channel 04 does not collapse.

[0206] In one embodiment, before forming the (i+1)th sub-plastic encapsulation layer 031b on the i-th sub-plastic encapsulation layer 031a, the following steps are included:

[0207] Step S31, forming a first liner layer 07 on the side of the i-th sub-molding layer 031a away from the substrate 01 (see Fig.31 ).

[0208] The first liner layer 07 can be formed by a deposition process (such as chemical vapor deposition or atomic layer deposition, etc.), and the first liner layer 07 can cover the i-th sub-molding layer 031a. At this time, the first liner layer 07 of the first groove 05 serves as a supporting layer for the i-th sub-molding layer 031a.

[0209] Step S32, forming a first isolation film 09 on the side of the first liner layer 07 away from the substrate 01, and the heat dissipation channel 04 is located between the first liner layer 07 and the first isolation film 09 in the first groove 05 (see Fig.32 ).

[0210] The first isolation film 09 can isolate the (i+1)th sub-plastic encapsulation layer 031 b from the first liner layer 07 , and serve as a support wall to provide a basis for the formation of the heat dissipation channel 04 .

[0211] Step S33, forming a fourth liner layer 11 on the side of the first isolation film 09 away from the substrate 01 (see Fig.33 ).

[0212] The material of the fourth liner layer 11 may include but is not limited to SiO 2 material.

[0213] The fourth liner layer 11 is located between the first isolation film 09 and the (i+1)th sub-plastic sealing layer 031 b and serves as a supporting wall of the (i+1)th sub-plastic sealing layer 031 b to ensure that the heat dissipation channel 04 does not collapse.

[0214] In this embodiment, the i+1th sub-plastic encapsulation layer 031b is formed on the fourth liner layer 11, and the heat dissipation channel 04 formed in the entire plastic encapsulation layer 03 will not collapse. The fourth liner layer 11 provides support for the i+1th sub-plastic encapsulation layer 031b (see Fig.34 ).

[0215] In one embodiment, after forming the fourth liner layer 11 on the side of the first isolation film 09 away from the substrate 01, the method includes:

[0216] At least one side of the first groove 05 is etched to form a third groove 10 that penetrates the fourth liner layer 11, the first isolation film 09 and the first liner layer 07 and exposes a portion of the i-th sub-plastic encapsulation layer 031a (see Fig.35 ).

[0217] It should be noted that the third groove 10 can be formed by etching.

[0218] The third groove 10 is located on at least one side of the first groove 05 , extends in a direction perpendicular to the substrate 01 , penetrates the first isolation film 09 and etches a portion of the i-th sub-plastic encapsulation layer 031 a to expose a portion of the i-th sub-plastic encapsulation layer 031 a .

[0219] At this time, when the i+1th layer of sub-molding layer 031b is formed, the i+1th layer of sub-molding layer 031b fills the third groove 10 and covers the i-th layer of sub-molding layer 031a (see Fig.36 ).

[0220] In this embodiment, the third groove 10 can increase the packaging firmness of the i+1th sub-plastic encapsulation layer 031b and the i-th sub-plastic encapsulation layer 031a, and further improve the composite effect of the i+1th sub-plastic encapsulation layer 031b and the i-th sub-plastic encapsulation layer 031a.

[0221] In one embodiment, the plastic encapsulation layer 03 further includes a heat dissipation structure 12 located in the heat dissipation channel 04, and after forming the first sub-plastic encapsulation layer 031, further includes:

[0222] Step S421 , forming a first liner material layer covering the first sub-plastic encapsulation layer 031 .

[0223] Step S422 , removing the first liner material layer outside the first groove 05 , and the remaining first liner material layer located in the first groove 05 is the first liner layer 07 .

[0224] Step S423 , forming a heat dissipation intermediate structure covering the first sub-plastic packaging layer 031 and the first liner layer 07 .

[0225] Step S424 , removing the heat dissipation intermediate structure except the first groove 05 to form a heat dissipation structure 12 .

[0226] The material of the heat dissipation structure 12 may be a material with good thermal conductivity, including but not limited to thermally conductive metal materials.

[0227] The heat dissipation structure 12 is located in the heat dissipation channel 04 . At this time, the heat generated by the chip 02 can be discharged through the heat dissipation structure 12 , thereby improving the heat dissipation performance of the product.

[0228] In one embodiment, a carbon nanotube 13 is provided in the plastic encapsulation layer 03, and the carbon nanotube 13 extends from one side of the plastic encapsulation layer 03 to the other side of the plastic encapsulation layer 03, and the heat dissipation channel 04 is located in the carbon nanotube 13. After the first sub-plastic encapsulation layer 031 is formed, the following is further included:

[0229] Step S431, provide a support plate 22 (see Fig.37 ).

[0230] Step S432, placing the substrate 01 in the support plate 22, and suspending the carbon nanotubes 13 on the upper side of the substrate 01, the height of the carbon nanotubes 13 being greater than the height of the i-th sub-plastic sealing layer 031a, and less than the height of the i+1-th sub-plastic sealing layer 031b (see Fig.38 ).

[0231] Step S433, forming a plastic encapsulation layer 03 on the side of the chip 02 away from the substrate 01 (see Fig.39 ).

[0232] Step S434, removing the carbon nanotubes 13 outside the plastic packaging layer 03.

[0233] Since the carbon nanotubes 13 are suspended on the upper side of the substrate 01, the height of the carbon nanotubes 13 is greater than the height of the i-th sub-plastic sealing layer 031a, and less than the height of the i+1-th sub-plastic sealing layer 031b, so when the plastic sealing layer 03 is formed, the carbon nanotubes 13 will be sealed in the plastic sealing layer 03. Finally, the carbon nanotubes 13 outside the plastic sealing layer 03 are removed, and the carbon nanotubes 13 extending from one side of the plastic sealing layer 03 to the other side of the plastic sealing layer 03 can be obtained. The center of the carbon nanotube 13 is a hollow channel, and the hollow channel of the carbon nanotube 13 can be used as a heat dissipation channel 04, wherein the carbon nanotube 13 itself can be used as a heat conducting medium to increase heat dissipation, and gas can also be introduced into the hollow channel of the carbon nanotube 13 to increase heat dissipation.

[0234] In this embodiment, the hollow channels of the carbon nanotubes 13 are used as the heat dissipation channels 04, which saves the preparation steps and further increases the speed of preparing the product.

[0235] In one embodiment, see Fig.41 The method for preparing a package with high heat dissipation performance further comprises:

[0236] Step S60 , forming a first fixing hole 17 penetrating the interposer structure 011 and the plastic encapsulation layer 03 .

[0237] Step S70 , forming an external circuit module 14 on a side of the interposer structure 011 away from the chip 02 , and the external circuit module 14 is connected to the chip 02 through the interposer structure 011 .

[0238] After removing the first carrier board 19 , the structure can be turned over to facilitate forming the external circuit module 14 .

[0239] The external circuit module 14 may include a passive device 141 (IPD) and / or an external plug-in 142, etc. The external plug-in 142 may include a voltage management module 1411 and / or a connector 1412, etc.

[0240] Step S80: Use the fixing member 18 to pass through the first fixing hole 17 to fix the heat sink 16 on the side of the plastic layer 03 away from the intermediate layer structure 011 (see Fig.42 ).

[0241] The fixing member 18 may include but is not limited to a bolt or the like.

[0242] As an example, the heat sink 16 may be firstly bonded to the side of the plastic packaging layer 03 away from the intermediate layer structure 011 by using graphene double-sided adhesive. Then, the heat sink 16 may be fixed by passing the fixing member 18 through the first fixing hole 17 .

[0243] After passing through the first fixing hole 17 , the fixing member 18 may not penetrate the heat dissipation plate 16 , or may penetrate the heat dissipation plate 16 .

[0244] In this embodiment, the fixing member 18 can make the connection between the heat sink 16 and the plastic packaging layer 03 more reliable.

[0245] It should be understood that although Fig.16 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Fig.16 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0246] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0247] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0248] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A package with high heat dissipation performance, characterized in that: include: substrate; A chip, located on one side of the substrate; The plastic sealing layer covers the substrate and the chip. The plastic sealing layer is provided with at least one heat dissipation channel, and the heat dissipation channel runs from one side of the plastic sealing layer to the other side of the plastic sealing layer.

2. The high heat dissipation package according to claim 1, characterized in that: The plastic sealing layer comprises n layers of sub-plastic sealing layers, and the side of the i-th sub-plastic sealing layer away from the substrate has a first groove, wherein n≥2, 1≤i<n, and n and i are positive integers; The heat dissipation channel is located between the first groove and the (i+1)th sub-plastic packaging layer.

3. The high heat dissipation package according to claim 2, characterized in that: The side of the (i+1)th sub-molding layer close to the (i)th sub-molding layer has a second groove, and the orthographic projection of the second groove on the substrate overlaps with the orthographic projection of the first groove on the substrate; The heat dissipation channel is located between the first groove and the second groove.

4. The high heat dissipation package according to claim 3, characterized in that: The plastic sealing layer also includes: a first lining layer, covering an inner wall of the first groove; The second lining layer covers the inner wall of the second groove, and the heat dissipation channel is located between the first lining layer and the second lining layer.

5. The high heat dissipation package according to claim 2, characterized in that: The plastic sealing layer also includes: a first lining layer, covering an inner wall of the first groove; The first isolation film is located on a side of the first liner layer away from the substrate, and the heat dissipation channel is located between the first liner layer and the first isolation film in the first groove.

6. The high heat dissipation package according to claim 5, characterized in that: The plastic sealing layer also includes: A third groove, located at at least one side of the first groove, passes through the first isolation film and exposes a portion of the i-th sub-plastic sealing layer; The (i+1)th sub-molding layer fills the third groove and covers the (i)th sub-molding layer.

7. The high heat dissipation package according to claim 6, characterized in that: The plastic sealing layer further includes a fourth liner layer, and the fourth liner layer is located between the first isolation film and the (i+1)th sub-plastic sealing layer; The third groove passes through the fourth liner layer and the first isolation film.

8. The high heat dissipation package according to claim 6, characterized in that: The first liner layer also covers the surface of the i-th sub-molding layer outside the first groove and away from the substrate; The third groove passes through the first isolation film and the first liner layer.

9. The high heat dissipation package according to claim 1, characterized in that: The plastic sealing layer further includes a heat dissipation structure, and the heat dissipation structure is located in the heat dissipation channel; or, A carbon nanotube is arranged in the plastic sealing layer, and the carbon nanotube extends from one side of the plastic sealing layer to the other side of the plastic sealing layer, and the heat dissipation channel is located in the carbon nanotube.

10. A method for preparing a package with high heat dissipation performance, characterized in that: include: providing a substrate; forming a chip on one side of the substrate; Forming an i-th sub-plastic encapsulation layer on the side of the substrate where the chip is formed, wherein the i-th sub-plastic encapsulation layer has a first groove on a side away from the substrate; Forming the (i+1)th sub-plastic encapsulation layer on the (i)th sub-plastic encapsulation layer to form a heat dissipation channel between the first groove and the (i+1)th sub-plastic encapsulation layer, wherein 1≤i<n, n≥2, and n and i are positive integers; The thickness of the first sub-plastic encapsulation layer is less than the height of the chip. After the first sub-plastic encapsulation layer is formed, the method includes: A second isolation film is attached along the surface of the first sub-molding layer away from the substrate and the surface of the chip; Performing a reverse molding process on the second isolation film to form a first mold; Forming a second sub-molding layer based on the first mold, wherein the second sub-molding layer has a second groove; forming a first lining layer on the inner wall of the first groove of the first sub-molding layer; forming a second lining layer on the inner wall of the second groove of the second sub-molding layer; Inverting the second sub-molding layer onto the first sub-molding layer and compounding them; Alternatively, before forming the (i+1)th sub-plastic encapsulation layer on the (i)th sub-plastic encapsulation layer, the method comprises: forming a first liner layer on a side of the i-th sub-molding layer away from the substrate; forming a first isolation film on a side of the first liner layer away from the substrate, wherein the heat dissipation channel is located between the first liner layer and the first isolation film in the first groove; forming a fourth liner layer on a side of the first isolation film away from the substrate; At least one side of the first groove is etched to form a third groove that penetrates the fourth liner layer, the first isolation film, and the first liner layer and exposes a portion of the i-th sub-molding layer.

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