Hardware on-off circuit

Abstract

The invention provides a hardware startup and shutdown circuit. The startup and shutdown functions are achieved through the combination of a resistor, a capacitor, an N-MOS tube, a P-MOS tube, a PNP triode, a Schottky diode, a voltage stabilizing diode, a switch key and the like. According to the invention, the state of the output level signal is controlled through the key switch and two operations of short pressing and long pressing, and the enabling pin of the power supply module is controlled through the state of the output signal level, so that the functions of starting up through short pressing and shutdown through long pressing are realized.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a hardware switch circuit. Background Art

[0002] Computer hosts, smart phones and other electronic devices all need power-on and power-off circuits to shut down and restart the products. When a system or software application bug occurs in an electronic device, it can be restored by forced shutdown or restart, or in an environment where electronic products need to be shielded, the interference caused by electronic products can be shielded by shutting down. The power-on and power-off circuit is one of the core functions of electronic products. It provides portable control and the need for forced recovery of the system in emergency situations.

[0003] At present, the circuits that realize the effects of short-press shutdown and long-press startup are generally implemented by software control such as single-chip microcomputers. The corresponding power on and off circuits are executed by detecting the time of the level change when the button is pressed. This circuit design requires the corresponding program writing for the single-chip microcomputer to be implemented. The program writing work is complicated and tedious, and the overall efficiency is low. Summary of the invention

[0004] The invention provides a hardware on / off circuit.

[0005] The technical solution to achieve the purpose of the present invention is: a hardware switch circuit, comprising:

[0006] a first capacitor C1, a first resistor R1, a second resistor R2, a first transistor Q1, a first diode D1, a switch K1, a second diode D2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first MOS transistor Q2, a second MOS transistor Q3, a third MOS transistor Q4, a fourth MOS transistor Q5, a second capacitor C2, and a third capacitor C3, wherein the first transistor Q1 is a PNP transistor, and the first MOS transistor Q2, the second MOS transistor Q3, the third MOS transistor Q4, and the fourth MOS transistor Q5 are all M OS tube, one end of the first capacitor C1, the first resistor R1, and the second resistor R2 are all grounded, the other end of the first capacitor C1 is connected to one end of the second diode D2, the other end of the second diode D2 is connected to one end of the seventh resistor R7 and the gate of the first MOS tube Q2, the other end of the seventh resistor R7 and the source of the first MOS tube Q2 are grounded, the drain of the first MOS tube Q2 is connected to one end of the sixth resistor R6, the other end of the first resistor R1 is connected to the base of the first triode Q1 and one end of the first diode D1, the second resistor R2 The other end is connected to the collector of the first triode Q1, and the emitter of the first triode Q1 is connected to the other end of the first diode D1; one end of the first diode D1 is connected to one end of the switch K1, and the other end of the switch K1 is connected to one end of the third resistor R3 and the gate of the second MOS tube Q3, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and one end of the fifth resistor R5. At the same time, the other end of the third resistor R3 is led out as a signal input port, and the other end of the fourth resistor R4 is connected to the source of the second MOS tube Q3, the gate of the third MOS tube Q The drain of the fourth MOS tube Q5 is connected to the drain of the second MOS tube Q4 and the gate of the fourth MOS tube Q5, the drain of the second MOS tube Q3 is grounded, one end of the sixth resistor R6 is connected to the gate of the second MOS tube Q3, the other end of the sixth resistor R6 and the drain of the fourth triode Q5 are grounded, the gate of the third MOS tube Q4 is connected to the drain of the fourth MOS tube Q5, the drain of the fourth MOS tube Q5 is connected to one end of the second capacitor C2 and the third capacitor C3, the other ends of the second capacitor C2 and the third capacitor C3 are grounded, and one end of the second capacitor C2 and the third capacitor C3 are led out as signal output ports.

[0007] Compared with the prior art, the present invention has the following significant advantages:

[0008] The present invention realizes the design of pure hardware control button switch, reduces the application of single chip microcomputer, reduces the complicated and tedious work of programming, and realizes simple and efficient control.

[0009] The present invention realizes a universal hardware switch control circuit suitable for a variety of electronic products. Long pressing or short pressing of a button affects the state of an output signal, and the state switching can be applicable to other applications applicable to this scenario, such as short pressing to activate a function, long pressing to turn off a function, etc.

[0010] The present invention is described in further detail below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the use of the present invention.

[0012] Figure 2 The figure is a schematic diagram of a hardware power on / off circuit.

[0013] Figure 3 This is a pulse diagram when the switch is short pressed.

[0014] Figure 4 This is a schematic diagram of the output signal when the switch is long pressed. DETAILED DESCRIPTION

[0015] A hardware switch circuit realizes this function through a combination of resistors, capacitors, N-MOS tubes, P-MOS tubes, PNP transistors, Schottky diodes, voltage regulator diodes, switch buttons, etc. The essence of the present invention is to control the output level signal state through the key switch, short press and long press operations to realize the functions of short press to start and long press to shut down. It is necessary to control the enable pin of the power module through the state of the output signal level. The functional flow chart is as follows Figure 1 shown.

[0016] A hardware power on / off circuit, comprising:

[0017] a first capacitor C1, a first resistor R1, a second resistor R2, a first transistor Q1, a first diode D1, a switch K1, a second diode D2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first MOS transistor Q2, a second MOS transistor Q3, a third MOS transistor Q4, a fourth MOS transistor Q5, a second capacitor C2, and a third capacitor C3, wherein the first transistor Q1 is a PNP transistor, and the first MOS transistor Q2, the second MOS transistor Q3, the third MOS transistor Q4, and the fourth MOS transistor Q5 are all M OS tube, one end of the first capacitor C1, the first resistor R1, and the second resistor R2 are all grounded, the other end of the first capacitor C1 is connected to one end of the second diode D2, the other end of the second diode D2 is connected to one end of the seventh resistor R7 and the gate of the first MOS tube Q2, the other end of the seventh resistor R7 and the source of the first MOS tube Q2 are grounded, the drain of the first MOS tube Q2 is connected to one end of the sixth resistor R6, the other end of the first resistor R1 is connected to the base of the first triode Q1 and one end of the first diode D1, the second resistor R2 The other end is connected to the collector of the first triode Q1, and the emitter of the first triode Q1 is connected to the other end of the first diode D1; one end of the first diode D1 is connected to one end of the switch K1, and the other end of the switch K1 is connected to one end of the third resistor R3 and the gate of the second MOS tube Q3, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and one end of the fifth resistor R5. At the same time, the other end of the third resistor R3 is led out as a signal input port, and the other end of the fourth resistor R4 is connected to the source of the second MOS tube Q3, the gate of the third MOS tube Q The drain of the fourth MOS tube Q5 is connected to the drain of the second MOS tube Q4 and the gate of the fourth MOS tube Q5, the drain of the second MOS tube Q3 is grounded, one end of the sixth resistor R6 is connected to the gate of the second MOS tube Q3, the other end of the sixth resistor R6 and the drain of the fourth triode Q5 are grounded, the gate of the third MOS tube Q4 is connected to the drain of the fourth MOS tube Q5, the drain of the fourth MOS tube Q5 is connected to one end of the second capacitor C2 and the third capacitor C3, the other ends of the second capacitor C2 and the third capacitor C3 are grounded, and one end of the second capacitor C2 and the third capacitor C3 are led out as signal output ports.

[0018] The working principle of the present invention is:

[0019] 1. Switch not pressed: output signal level is 0.

[0020] 2. Short-press output state: Short-press switch K1. Due to the charge-discharge characteristic that the capacitor voltage of capacitor C1 cannot change suddenly, the instantaneous value of the level of pin 1 of diode D1 is GND, that is, the level is 0. At this time, R3, K1, and D1 form a loop. The conduction voltage drop of D1 makes the voltage of gate G of P-MOS tube about 0.3V. At this time, Q3 satisfies Vgs>Vth, the source and drain are turned on, and gate G of Q5 is pulled to GND. Q5 satisfies the conduction condition and turns on. At this time, the output signal is pulled high, and the output level is the high level of the input signal. In order to ensure that the output of the high-level signal can be maintained when the button is pressed, Q4 N-MOS tube is added to realize the positive feedback circuit. The high-level output will satisfy the conduction of Q4, so that the gate G of Q5 is always pulled low, and the output can maintain the high level of the input signal, and the system starts up.

[0021] 3. Long-press output state: Long-press switch K1. Due to the charging characteristics of capacitor C1, the voltage will slowly rise to the input signal - D1 level. When the gate voltage of Q2N-MOS tube Vg=1.5V, the MOS tube is turned on. Because the time for capacitor C1 to charge to 1.5V is very fast and cannot meet the long-press state, the voltage regulator diode D2 is required to clamp the charging voltage of capacitor C1 to 4.5V to turn on MOS tube Q2. The resistance value of resistor R3 and the capacitance of C1 will affect the charging speed of the capacitor, which can be calculated according to the capacitor charging and discharging time calculation formula t=-R*C*ln(1-Vc / V). Among them, t is the charging time of the capacitor, R is the overall equivalent resistance in the charging circuit, C is the capacitance of the capacitor, the unit is F, Vc is the voltage when the capacitor rises to a stable state, and V is the power supply voltage. Therefore, according to the capacitor charging time, when the capacitor is charged to the conduction voltage drop of MOS tube Q2 by long pressing the switch, Q2 is turned on, so that the output signal is pulled down to GND. At this time, Q4 is cut off, the positive feedback is turned off, the output is 0 low level, and the system is shut down. Among them, the transistor Q1, the resistor R1, and the resistor R2 form a discharge circuit, so that when the button is released after long pressing to shut down, the charge of capacitor C1 can be quickly discharged without affecting the next short press to start up.

[0022] The design ideas of the present invention are as follows:

[0023] Signal Description:

[0024] 1. Input signal: This signal is a voltage signal. The level standard refers to the level standard of the enable IO port of the back-end power module.

[0025] 2. Output signal: This signal is a voltage output signal. The high level is the input signal, and the low level is the reference ground GND. The high and low levels of this signal control the back-end power supply and the power on and off of the entire system. When the signal is pressed short, it outputs a high level, and when the signal is pressed long, it outputs a low level.

[0026] As an embodiment, when the input signal level is 5V, the specific selection of each component is as follows:

[0027] 1. Resistance: R1 is 150kΩ, R2 is 10Ω, R3 is 10kΩ, R4 is 10KΩ, R5 is 1kΩ, and R6 is 100kΩ.

[0028] 2. Capacitor: C1 is 100uf, C2 is 1uf, and C3 is 0.1uf.

[0029] 3. Diode: D1 is a Schottky diode with a smaller voltage drop. For reference, select MBR120VLSFT1G, with a forward voltage drop of 0.3V.

[0030] D2 is selected as a suitable voltage regulator diode to ensure that C1 can be charged to a certain voltage (ideally, input signal minus D1 voltage drop). For reference, BZT52C3V0S is selected, and the voltage regulation value is 3V.

[0031] 4. Transistor: Q1 is selected as a PNP transistor with relatively large on-current. For reference, the selected transistor is 2SB1690KT146, with a maximum on-current of 2A.

[0032] 5.MOS tube: Q2 and Q4 are selected as N-MOS, refer to AO3400A, Vgs (th) is 1.5V; Q3 and Q5 are selected as P-MOS, refer to AO3401A, Vgs (th) is 1.3V.

[0033] 6. Switch button: You can choose a non-self-locking switch suitable for the product, such as a touch switch.

[0034] When the present invention is pressed short, the simulation output signal within 1s is as follows Figure 3 As shown, the output level is high level; when long pressed, the simulated output signal within 5s is as follows Figure 4 As shown in the figure, the output level is pulled down at about 3s. The simulation meets the circuit design requirements.

[0035] After actual testing, the power on / off circuit of the present invention meets the functional requirements of short-press power on and long-press power off.

Claims

1. A hardware power on / off circuit, characterized in that: include: a first capacitor C1, a first resistor R1, a second resistor R2, a first transistor Q1, a first diode D1, a switch K1, a second diode D2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first MOS transistor Q2, a second MOS transistor Q3, a third MOS transistor Q4, a fourth MOS transistor Q5, a second capacitor C2, and a third capacitor C3, wherein the first transistor Q1 is a PNP transistor, and the first MOS transistor Q2, the second MOS transistor Q3, the third MOS transistor Q4, and the fourth MOS transistor Q5 are all M OS tube, one end of the first capacitor C1, the first resistor R1, and the second resistor R2 are all grounded, the other end of the first capacitor C1 is connected to one end of the second diode D2, the other end of the second diode D2 is connected to one end of the seventh resistor R7 and the gate of the first MOS tube Q2, the other end of the seventh resistor R7 and the source of the first MOS tube Q2 are grounded, the drain of the first MOS tube Q2 is connected to one end of the sixth resistor R6, the other end of the first resistor R1 is connected to the base of the first triode Q1 and one end of the first diode D1, the second resistor R2 The other end is connected to the collector of the first triode Q1, and the emitter of the first triode Q1 is connected to the other end of the first diode D1; one end of the first diode D1 is connected to one end of the switch K1, and the other end of the switch K1 is connected to one end of the third resistor R3 and the gate of the second MOS tube Q3, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and one end of the fifth resistor R5. At the same time, the other end of the third resistor R3 is led out as a signal input port, and the other end of the fourth resistor R4 is connected to the source of the second MOS tube Q3, the gate of the third MOS tube Q The drain of the fourth MOS tube Q5 is connected to the drain of the second MOS tube Q4 and the gate of the fourth MOS tube Q5, the drain of the second MOS tube Q3 is grounded, one end of the sixth resistor R6 is connected to the gate of the second MOS tube Q3, the other end of the sixth resistor R6 and the drain of the fourth triode Q5 are grounded, the gate of the third MOS tube Q4 is connected to the drain of the fourth MOS tube Q5, the drain of the fourth MOS tube Q5 is connected to one end of the second capacitor C2 and the third capacitor C3, the other ends of the second capacitor C2 and the third capacitor C3 are grounded, and one end of the second capacitor C2 and the third capacitor C3 are led out as signal output ports.

2. The hardware power on / off circuit according to claim 1, characterized in that: The switch K1 is a non-self-locking switch.

3. The hardware power on / off circuit according to claim 1, characterized in that: The first MOS transistor Q2 and the third MOS transistor Q4 are N-MOS transistors, and the second MOS transistor Q3 and the fourth MOS transistor Q5 are P-MOS transistors.

4. The hardware power on / off circuit according to claim 1, characterized in that: The resistance value of resistor R3 and the capacitance of C1 are calculated according to the capacitor charging and discharging time formula. The specific formula is: t=-R×C×ln(1-Vc / V) Where t is the charging time of the capacitor, R is the overall equivalent resistance in the charging circuit, C is the capacitance of the capacitor, Vc is the voltage when the capacitor rises to a stable state, and V is the power supply voltage.

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