Data access management method of memory device, memory controller of memory device, memory device and electronic device

Abstract

The invention relates to a method for performing data access management of a memory device in a predetermined communication architecture by means of multi-table checking, a memory controller of the memory device, the memory device and an electronic device. The method includes: using a memory controller to receive a first command from a host device, wherein the first command indicates that first data located at a first logical address is required to be read; checking at least one logical-to-physical address mapping table to generate a first checking result, starting to perform a first read operation according to the first checking result, and checking a temporary physical-to-logical address mapping table corresponding to a first active block to generate a second checking result, selectively performing a second read operation according to the second check result; and returning the first data to the host device, wherein the first data is read according to one of the first check result and the second check result.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a method and related device for managing data access of a memory device in a predetermined communication architecture by means of multi-table checking. Background Art

[0002] The memory device may include a flash memory for storing data, and the access management of the flash memory is quite complicated. For example, the memory device may be a memory card, a solid state drive (SSD), or an embedded storage device (e.g., an embedded storage device that complies with the universal flash storage (UFS) specification). The memory device can be used to store different files (e.g., system files and user files) in the file system of the host. Since some files may be frequently accessed, some data may become invalid data. When invalid data and some valid data are mixed in the same storage block in the memory device, a garbage collection (GC) operation is generally required to release more storage space for further use. In addition, during the access of the file, the internal management information may change accordingly. Since the access processing of a part of the internal management information may not be completed, before reading any data from the flash memory, the memory device must first perform a search operation, which increases the total processing time of the read operation. There is no proper way to deal with this in the prior art, and therefore, an innovative method and related architecture are highly needed to solve these problems without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to provide a method and related device for managing data access of a memory device in a predetermined communication architecture (eg, a universal flash storage communication architecture) by means of multi-table checking to solve the above-mentioned problem.

[0004] At least one embodiment of the present invention provides a method for managing data access of a memory device in a predetermined communication architecture by means of multi-table checking, wherein the method can be applied to a memory controller of the memory device, the memory device can include the memory controller and a non-volatile memory, the non-volatile memory can include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element can include a plurality of blocks. The method can include: using the memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller, wherein the first command indicates a request to read first data located at a first logical address; checking at least one logical to physical address mapping table to generate a first checking result, starting a first read operation according to the first checking result, and checking a temporary physical to logical address mapping table corresponding to a first active block to generate a second checking result for selectively performing a second read operation according to the second checking result; and returning the first data to the host device, wherein the first data is read according to a checking result between the first checking result and the second checking result.

[0005] In addition to the above method, the present invention also provides a memory controller of a memory device, wherein the memory device includes a memory controller and a non-volatile memory, the non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element may include multiple blocks. In addition, the memory controller includes a processing circuit, wherein the processing circuit is used to control the memory controller according to multiple host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, and to perform data access management of the memory device in a predetermined communication architecture by means of multi-table checks. The memory controller also includes a transmission interface circuit, wherein the transmission interface circuit is used to communicate with the host device. For example, a memory controller receives a first command from a host device through a transmission interface circuit of the memory controller, wherein the first command indicates a request to read first data located at a first logical address; the memory controller checks at least one logical-to-physical address mapping table to generate a first check result, starts a first read operation based on the first check result, and checks a temporary physical-to-logical address mapping table corresponding to a first active block to generate a second check result for selectively performing a second read operation based on the second check result; and the memory controller returns the first data to the host device, wherein the first data is read based on a check result between the first check result and the second check result.

[0006] In addition to the above method, the present invention also provides a memory device including the above memory controller, wherein the memory device includes: a non-volatile memory for storing information; and a memory controller coupled to the non-volatile memory and used to control the operation of the memory device.

[0007] In addition to the above method, the present invention also provides an electronic device including the above memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and used to provide power to the at least one processor and the memory device. In addition, the memory device provides storage space for the host device.

[0008] According to some embodiments, the device may include at least a portion (e.g., a portion or all) of an electronic device. For example, the device may include a memory controller in a memory device. For another example, the device may include a memory device. For another example, the device may include an electronic device.

[0009] According to some embodiments, a memory device may store data for a host device, wherein some of the stored data needs to be updated. To correct the problems of the prior art, the memory device may be operated according to at least one control scheme (e.g., one or more control schemes) of the method to perform relevant operations, in particular, attempting to access the stored data according to a first address mapping table of a first type among two different address mapping tables of different types, while attempting to access the stored data according to a second address mapping table of a second type among the two different address mapping tables, and only continuing to perform one of a first operation of attempting to access the stored data according to the first address mapping table and a second operation of attempting to access the stored data according to the second address mapping table, depending on which of the first operation and the second operation is correct, so as to obtain the stored data from a correct location in the non-volatile memory as quickly as possible.

[0010] The method and related apparatus of the present invention can ensure that the memory device can operate properly under different circumstances. For example, when a host command indicating a read request is received from a host device, the memory device can start to refer to two different address mapping tables belonging to different types for subsequent processing, so as to reduce the expected value of the total processing time of reading data from the non-volatile memory starting from the time of receiving the host command (e.g., the time point of receiving the host command), and thus increase the overall performance. For example, as time goes by, the memory device can perform multiple read operations for the host device respectively, and effectively complete most of the read operations among the multiple read operations, wherein the average processing time of the multiple read operations can be reduced. In addition, the method and related apparatus of the present invention can solve the problems encountered by the prior art without introducing side effects or in a manner that is unlikely to introduce side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 FIG. 4 is a schematic diagram of a first table processing control scheme according to an embodiment of the present invention.

[0013] Figure 3 The diagram is a schematic diagram of a search time hidden table processing control scheme of a method for managing data access to a memory device in a predetermined communication architecture by using multiple table checks according to an embodiment of the present invention.

[0014] Figure 4 FIG. 4 is a schematic diagram of a workflow of the method according to an embodiment of the present invention.

[0015] Figure 5 FIG. 4 is a schematic diagram of a block expansion control scheme of the method according to an embodiment of the present invention.

[0016]

Explanation of symbols

[0017] 10: Electronic devices

[0018] 50: Host device

[0019] 52: Processor

[0020] 54: Power supply circuit

[0021] 58,118: Transmission interface circuit

[0022] 100: memory device

[0023] 110: memory controller

[0024] 112: Microprocessor

[0025] 112C: Program code

[0026] 112M: Read-only memory

[0027] 114: Control logic circuit

[0028] 116: Random Access Memory

[0029] 116T: Temporary logical to physical address mapping table

[0030] 117T: Temporary physical to logical address mapping table

[0031] 118C: Universal Flash Storage Controller

[0032] 118U: Standardized communication protocol circuit

[0033] 118M:M physical layer circuit

[0034] 120: Non-volatile memory

[0035] 120T: Global logical to physical address mapping table

[0036] 122-1~122-N: Non-volatile memory element

[0037] 220: Active block

[0038] 227T: Physical to logical address mapping table

[0039] S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23: Steps

[0040] {PG(0)},{PG(1)}: Page

[0041] {BLK(0)},{BLK(1)}: Block

[0042] XPG(0),XPG(1):Superpage

[0043] XBLK(0),XBLK(1):Super Block DETAILED DESCRIPTION

[0044] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors; which may be collectively referred to as a processor 52), a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other through a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may be used to provide storage space for the host device 50, and may obtain one or more driving voltages from the host device 50 as a power supply for the memory device 100. Examples of the host device 50 may include, but are not limited to: a multi-function mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 may include, but are not limited to: portable memory devices (e.g., memory cards complying with SD / MMC, CF, MS, or XD specifications), solid state drives (SSDs), and different types of embedded memory devices (e.g., embedded memory devices complying with universal flash storage (UFS) specifications or embedded multi-media card (eMMC) specifications). According to the present embodiment, the memory device 100 may include a controller, such as a memory controller 110, and may further include a non-volatile (NV) memory 120 (for simplicity, in FIG. Figure 1 1, wherein the memory controller 110 is used to access the non-volatile memory 120, and the non-volatile memory 120 is used to store information. The non-volatile memory 120 may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), such as a plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N (for simplicity, the non-volatile memory elements 122-1, 122-2, ..., and 122-N are referred to as "NV memory" in FIG. 1 ). Figure 1 , respectively, as “NV memory elements” in the figure), where “N” may represent a positive integer greater than 1. For example, the non-volatile memory 120 may be a flash memory, and the plurality of non-volatile memory elements 122-1, 122-2, . . . , and 122-N may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto.

[0045] like Figure 1As shown, the memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M; for the sake of simplicity, it is marked as "ROM"), a control logic circuit 114, a random access memory 116 (random access memory, RAM; for the sake of simplicity, it is marked as "RAM", for example, it can be implemented by a static random access memory (SRAM), but the present invention is not limited thereto) and a transmission interface circuit 118, wherein at least a portion (e.g., a portion or all) of the above components can be coupled to each other through a bus. The random access memory 116 can be used to provide an internal storage space for the memory controller 110 (e.g., it can temporarily store information). In addition, the read-only memory 112M of this embodiment is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the non-volatile memory 120. It should be noted that the program code 112C can also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 can be used to control the non-volatile memory 120 and can include an error correction code (ECC) circuit (not shown). Figure 1), which can perform error correction code encoding and error correction code decoding to protect data and / or perform error correction. The transmission interface circuit 118 may include multiple sub-circuits, and the multiple sub-circuits may interact with each other to communicate. The transmission interface circuit 118 may comply with one or more communication specifications among different communication specifications (such as Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, embedded multimedia card specification or universal flash storage specification), and can be used for the memory device 100 to communicate with the host device 50 (or the transmission interface circuit 58 therein) according to the one or more communication specifications. Similarly, the transmission interface circuit 58 may comply with the one or more communication specifications, and can be used for the host device 50 to communicate with the memory device 100 (or the transmission interface circuit 118 therein) according to the one or more communication specifications. For example, the multiple sub-circuits of the transmission interface circuit 118 may include a universal flash storage controller 118C (labeled as a "UFS controller" for simplicity), a standardized communication protocol (Unified Protocol, commonly referred to as UniPro) circuit 118U (labeled as a "UniPro circuit" for simplicity), and a physical layer (physical layer, PHY) circuit (for example, an M physical layer (M-PHY) circuit 118M that complies with the relevant specifications of the MIPI Alliance), and the transmission interface circuit 58 can be implemented as having a circuit architecture similar to or the same as the circuit architecture of the transmission interface circuit 118 (for example, multiple corresponding sub-circuits), but the present invention is not limited to this.

[0046] In the present embodiment, the host device 50 can indirectly access the non-volatile memory 120 in the memory device 100 by transmitting a plurality of host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives the plurality of host commands and corresponding logical addresses, and converts the plurality of host commands into a plurality of memory operation commands (which may be referred to as operation commands), and then uses the plurality of operation commands to control the non-volatile memory 120 to read or write / program memory cells or data pages at specific physical addresses in the non-volatile memory 120, etc., wherein the physical address may be associated with the logical address. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical address and the logical address. The non-volatile memory 120 may store a global logical-to-physical address mapping table 120T for the memory controller 110 to control the memory device 100 to access the data in the non-volatile memory 120, but the present invention is not limited thereto. In addition, the memory controller 110 may generate or update at least one physical-to-logical (P2L) address mapping table (e.g., temporary P2L address mapping table 117T). For example, the memory controller 110 may refer to the temporary P2L address mapping table 117T to perform certain internal management operations (e.g., garbage collection (GC) operations) when necessary.

[0047] For better understanding, the global logical-to-physical address mapping table 120T may be located in a predetermined region (e.g., a system region) within the non-volatile memory element 122-1, but the present invention is not limited thereto. For example, the global logical-to-physical address mapping table 120T may be divided into a plurality of local logical-to-physical address mapping tables, and the plurality of local logical-to-physical address mapping tables may be stored in one or more non-volatile memory elements of the non-volatile memory elements 122-1, 122-2, and 122-N, and in particular, may be stored in the non-volatile memory elements 122-1, 122-2, and 122-N, respectively. When necessary, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global logical-to-physical address mapping table 120T into the random access memory 116 or other memory. For example, the memory controller 110 may load a local logical-to-physical address mapping table (e.g., a first local logical-to-physical address mapping table) from the multiple local logical-to-physical address mapping tables into the random access memory 116 as a temporary logical-to-physical address mapping table 116T for accessing data in the non-volatile memory 120 according to the local logical-to-physical address mapping table stored as the temporary logical-to-physical address mapping table 116T, but the present invention is not limited to this.

[0048] The memory area of ​​the random access memory 116 may include a plurality of sub-areas for temporarily storing different information (e.g., buffer data, a temporary logical-to-physical address mapping table 116T, and a temporary physical-to-logical address mapping table 117T), and at least a portion of the plurality of sub-areas of the memory area (e.g., a portion of the sub-areas or all of the sub-areas) may be considered as a data buffer. For example, the sub-area for temporarily storing buffer data may be considered as a data buffer, but the present invention is not limited thereto. According to some embodiments, the entire memory area (e.g., the plurality of sub-areas for storing buffer data, a temporary logical-to-physical address mapping table 116T, and a temporary physical-to-logical address mapping table 117T) may be considered as a data buffer.

[0049] In addition, the at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) may include a plurality of blocks, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the non-volatile memory 120 is a block, and the minimum unit for the memory controller 110 to perform a data write operation on the non-volatile memory 120 is a page, but the present invention is not limited thereto. For example, any non-volatile memory element 122-n (the symbol "n" may represent any integer in the interval [1, N]) among the non-volatile memory elements 122-1, 122-2, ..., and 122-N may include a plurality of blocks, and a block within the plurality of blocks may include and record a specific number of pages, wherein the memory controller 110 may access a certain page of a certain block within the plurality of blocks according to a block address and a page address.

[0050] According to some embodiments, the memory controller 110 may monitor the valid page counts of the plurality of blocks respectively for subsequent processing (e.g., garbage collection operation). For data reception, the memory controller 110 may configure at least one block (e.g., one or more blocks) among the plurality of blocks of at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) in the non-volatile memory 120 as at least one active block (e.g., one or more active blocks), and utilize the at least one active block to receive and store data (e.g., host-write data) from the host device 50. For example, the data (e.g., host write data, such as data to be written into the non-volatile memory 120) may include a plurality of sets of partial data, and the at least one active block may include a first active block, wherein the temporary physical-to-logical address mapping table 117T may correspond to the first active block, and in particular, the relevant mapping information may be stored for the first active block to indicate the physical-to-logical address mapping relationship. In addition, the memory controller 110 may maintain (e.g., generate or update) the temporary physical-to-logical address mapping table 117T for relevant internal management.

[0051] Figure 21 is a schematic diagram of a first table processing control scheme according to an embodiment of the present invention. During the period of receiving and storing the data (e.g., host write data, such as data to be written into the non-volatile memory 120) from the host device 80, the memory controller 110 may utilize a first active block (e.g., active block 220) to receive and store one or more sets of partial data among the plurality of sets of partial data, and record the relevant mapping information (e.g., physical to logical table entry) in a temporary physical to logical address mapping table 117T corresponding to the active block 220 (for simplicity, in Figure 2 The physical-to-logical table entry may be marked as "P2L table" in the table to indicate the physical-to-logical address mapping relationship for the active block 220. The physical-to-logical address mapping relationship indicated by the physical-to-logical table entry may include a physical-to-logical address mapping relationship between a logical address and a physical address, wherein the host device 50 writes the one or more sets of partial data to the logical address, and the physical address indicates the location where the one or more sets of partial data are stored in the active block 220. When a first predetermined standard is met (for example, the active block 220 is completely programmed), the memory controller 110 may perform a set of table processing operations, and the set of table processing operations may include:

[0052] (1) A first table processing operation: According to the temporary physical to logical address mapping table 117T corresponding to the active block 220 (for simplicity, in Figure 2 to update the global logical to physical address mapping table 120T (for brevity, in Figure 2 In particular, according to the physical to logical table entries in the temporary physical to logical address mapping table 117T (for simplicity, in Figure 2 to update certain logic-to-physical table entries in the global logic-to-physical address mapping table 120T (for brevity, in Figure 2 , marked as “L2P item” in the figure, for indicating the logical to physical address mapping relationship for the active block 220;

[0053] (2) A second table processing operation: storing the temporary physical-to-logical address mapping table 117T in the non-volatile memory 120 to generate or update a first physical-to-logical address mapping table (e.g., the physical-to-logical address mapping table 227T, for simplicity). Figure 2 , for example, by writing all physical-to-logical table entries recorded in the temporary physical-to-logical address mapping table 117T into the physical-to-logical address mapping table 227T to perform the above-mentioned subsequent processing, wherein the physical-to-logical address mapping table 227T can be regarded as a backup version of the temporary physical-to-logical address mapping table 117T; and

[0054] (3) A third table processing operation: after performing the first table processing operation (e.g., updating the global logical-to-physical address mapping table 120T according to the temporary physical-to-logical address mapping table 117T) and the second table processing operation (e.g., storing the temporary physical-to-logical address mapping table 117T in the non-volatile memory 120), clearing the temporary physical-to-logical address mapping table 117T (e.g., the physical-to-logical table entries therein) to reuse the corresponding storage space in the temporary physical-to-logical address mapping table 117T and / or the random access memory 116; however, the present invention is not limited to this. According to some embodiments, the first table processing operation may include loading a local logical-to-physical address mapping table (e.g., the first local logical-to-physical address mapping table) in the global logical-to-physical address mapping table 120T into the random access memory 116 as a temporary logical-to-physical address mapping table 116T, updating one or more logical-to-physical table entries in the temporary logical-to-physical address mapping table 116T to indicate one or more logical-to-physical address mapping relationships among a plurality of logical-to-physical address mapping relationships for the active block 220, and updating the global logical-to-physical address mapping table 120T (e.g., the local logical-to-physical address mapping table therein) according to the temporary logical-to-physical address mapping table 116T. According to some embodiments, the first predetermined criterion may be replaced by any one of a plurality of predetermined criteria to allow the memory controller 110 to perform the set of table processing operations when any of the above criteria is met. For example, the plurality of predetermined criteria may include:

[0055] (1) The first predetermined standard: the active block 220 is fully programmed; and

[0056] (2) a second predetermined criterion: the number of physical-to-logical table entries recorded in the temporary physical-to-logical address mapping table 117T reaches a predetermined entry count;

[0057] The predetermined entry count may represent a predetermined table size of the temporary physical-to-logical address mapping table 117. For example, when the active block 220 is completely programmed or the number of physical-to-logical table entries recorded in the temporary physical-to-logical address mapping table 117T reaches the predetermined entry count, the memory controller 110 may perform the table processing operation.

[0058] After any active block (e.g., active block 220) among the at least one active block is completely programmed, the memory device 100 (or the memory controller 110 therein) may close any of the active blocks to make any of the blocks become an inactive block, and select a blank block (e.g., an erased block) as a replacement for any of the active blocks for subsequent processing corresponding to any of the active blocks. In addition, the subsequent processing may include performing a garbage collection process to write valid data among all data in the inactive block into another blank block (e.g., another erased block), but the present invention is not limited thereto.

[0059] According to some embodiments, since the physical-to-logical address mapping relationship indicated by the physical-to-logical table entry in the at least one physical-to-logical address mapping table (e.g., the temporary physical-to-logical address mapping table 117T or the physical-to-logical address mapping table 227T) and the logical-to-physical address mapping relationship indicated by the corresponding logical-to-physical table entry in the global logical-to-physical address mapping table 120T should be inverse address mapping relationships, the memory controller 110 can determine the latest mapping information (e.g., the physical address) carried by the corresponding logical-to-physical table entry in the global logical-to-physical address mapping table 120T according to the latest mapping information (e.g., the logical address) carried by the physical-to-logical table entry in the at least one physical-to-logical address mapping table. In addition, the memory controller 110 can manage the relationship between the physical address and the logical address (e.g., the physical address indicating the location where the host write data is stored in the non-volatile memory 120 and the logical address where the host device 50 writes the host write data) using the plurality of local logical-to-physical address mapping tables. For example, the plurality of local logical-to-physical address mapping tables may be implemented as a series of local logical-to-physical address mapping tables {L2PT(1), L2PT(2), ..., L2PT(X)} corresponding to a series of logical address ranges {L_Addr_R(1), L_Addr_R(2), ..., L_Addr_R(R_CNT)}, respectively, and the series of logical address ranges {L_Addr_R(1), L_Addr_R(2), ..., L_Addr_R(R_CNT)} may be implemented as a series of consecutive logical A series of consecutive ranges of logical addresses {L_Addr(0), L_Addr(1), …, L_Addr((R_CNT*R_Size)-1)}, such as the range of R_CNT intervals [L_Addr(0), L_Addr(R_Size-1)], [L_Addr(R_Size), L_Addr((2*R_Size)-1)], … and [L_Addr((R_CNT-1)*R_Size), L_Addr((R_CNT*R_Size)-1)].

[0060] According to some embodiments, the memory device 100 (or the memory controller 110 therein) may update the global logical-to-physical address mapping table 120T according to the at least one physical-to-logical address mapping table (e.g., the temporary physical-to-logical address mapping table 117T or the physical-to-logical address mapping table 227T), wherein the address mapping relationship indicated by the at least one physical-to-logical address mapping table (e.g., the temporary physical-to-logical address mapping table 117T or the physical-to-logical address mapping table 227T) is usually newer than the address mapping relationship indicated by the global logical-to-physical address mapping table 120T. For example, in one embodiment, the memory device 100 (or the memory controller 110 therein) may operate according to a search and read control scheme, and in particular, may perform a search operation on the at least one physical-to-logical address mapping table (e.g., the temporary physical-to-logical address mapping table 117T or the physical-to-logical address mapping table 227T) before reading any data from the non-volatile memory 120, but the present invention is not limited thereto. For better understanding, it is assumed that regardless of whether the logical address L_Addr is searched in the temporary physical to logical address mapping table 117T, the expected value of the time for searching a target logical address (e.g., the logical address L_Addr) in the temporary physical to logical address mapping table 117T may be equal to a search time T_search (e.g., 15 microseconds (μs)), and the expected value of the time for reading any of the above data from the non-volatile memory 120 may be equal to a read time T_read, such as a busy time tR (e.g., 68 microseconds). Therefore, the memory device 100 (or the memory controller 110 therein) operated according to the search and read control scheme may require at least the search and read time (T_search+T_read) to prepare any of the above data in the memory controller 110 to be transmitted back to the host device 50. In some other embodiments, the memory device 100 (or the memory controller 110 therein) may be operated according to at least one other control scheme (eg, one or more other control schemes) to hide the search time T_search in the read time T_read to increase the overall performance.

[0061] Figure 3 FIG. 1 is a schematic diagram of a search-time-hidden table processing control scheme for a method of managing data access to a memory device in a predetermined communication architecture by using multiple table checks according to an embodiment of the present invention. The memory device 100 (or the memory controller 110 therein) may be configured to: Figure 3 The search time hidden table processing control scheme shown is used to operate.

[0062] In step S10 , the memory device 100 (or the memory controller 110 ) may receive a host command from the host device 50 among a plurality of host commands.

[0063] In step S11, the memory device 100 (or the memory controller 110) may check whether the host command (eg, the host command received from the host device 50 in step S10) is a first command (eg, a read command; for simplicity, Figure 3 In the example, the first command may carry first information associated with the first data to be written, and the first information may include a first logical address (e.g., logical address L_Addr), wherein the first command may indicate a request to read the first data from the logical address L_Addr, but the present invention is not limited thereto. In addition to the first logical address (e.g., logical address L_Addr), the first information may further include a first data length (e.g., length LENGTH) of the first data to indicate a first logical address region starting from the first logical address (e.g., logical address region L_Addr_Region starting from the logical address L_Addr and having a length LENGTH), wherein the first command may indicate a request to read the first data from the first logical address region (e.g., logical address region L_Addr_Region).

[0064] In step S12, the memory device 100 (or the memory controller 110) may perform a first logical-to-physical address mapping operation on the logical address L_Addr according to the global logical-to-physical address mapping table 120T (for simplicity, the first logical-to-physical address mapping operation is shown in FIG. Figure 3 ” (marked as “L2P mapping”) to obtain a first physical address P_Addr1 associated with the logical address L_Addr.

[0065] In step S13, the memory device 100 (or the memory controller 110) may utilize a first non-volatile read command (e.g., a flash read command) among the plurality of operation commands to trigger the non-volatile memory 120 to start reading at the first physical address P_Addr1 associated with the logical address L_Addr (e.g., reading data stored at the first physical address P_Addr1 from the non-volatile memory 120), and in the temporary physical-to-logical address mapping table 117T corresponding to the active block 220 (for simplicity, in Figure 3 The same logical address L_Addr is searched in the temporary physical-to-logical address mapping table 117T to try to obtain any physical address (eg, a second physical address P_Addr2) associated with the logical address L_Addr according to the temporary physical-to-logical address mapping table 117T.

[0066] In step S14, the memory device 100 (or the memory controller 110) may check whether the logical address L_Addr is found in the temporary physical to logical address mapping table 117T (for better understanding, in Figure 3 If yes (for example, the first logical address is found in the temporary entity-to-logical address mapping table 117T), go to step S15; if no (for example, the first logical address is not found in the temporary entity-to-logical address mapping table 117T), go to step S17.

[0067] In step S15, the memory device 100 (or the memory controller 110) may utilize a second non-volatile read command (e.g., another flash read command) among the plurality of operation commands to trigger the non-volatile memory 120 to start reading at the second physical address P_Addr2 associated with the logical address L_Addr (e.g., reading data stored at the second physical address P_Addr2 from the non-volatile memory 120).

[0068] In step S16 , the memory device 100 (or the memory controller 110 ) may transmit the data read at the second physical address P_Addr2 back to the host device 50 as the first data.

[0069] In step S17 , the memory device 100 (or the memory controller 110 ) may transmit the data read at the first physical address P_Addr1 back to the host device 50 as the first data.

[0070] In step S18, the memory device 100 (or the memory controller 110) may check whether there is any new host-side event (eg, any new command; for simplicity, in Figure 3 In particular, wait for any of the above new host-side events until a predetermined waiting time expires, if yes (for example, before the predetermined waiting time expires, the memory controller 110 detects any of the above new host-side events), enter step S10; if no (for example, before the predetermined waiting time expires, the memory controller 110 does not detect the new host-side event), then Figure 3 The workflow shown ends.

[0071] In step S19 , the memory device 100 (or the memory controller 110 ) may perform other processing according to the host command (eg, the host command received from the host device 50 in step S10 ).

[0072] The memory device 100 (or the memory controller 110 therein) can perform the operation of step S12 very quickly, and then can use the first non-volatile read command to trigger the non-volatile memory 120 and start searching the logical address L_Addr in the temporary physical-to-logical address mapping table 117T simultaneously (or nearly simultaneously) in step S13, so as to hide the search time T_search (e.g., 15 microseconds) in the read time T_read (e.g., 68 microseconds), thereby increasing the overall performance. Assume that the hit rate of the search operation in step S13 is equal to P%, where "P" can represent a positive value in the interval [0,100]. The expected value of the time for the memory device 100 (or the memory controller 110 therein) to respond to the first command (e.g., a read command) so that the first data in the memory controller 110 is ready to be transmitted back to the host device 50 may be equal to the total processing time T_total as follows: T_total=((100-P)%*T_read)+(P%*(2*T_read));

[0073] The hit rate P% will be very low. For example, P=1, and the total processing time T_total can be rewritten as follows: T_total=(99%*T_read)+(1%*(2*T_read))=(1.01*T_read);

[0074] The total processing time T_total (eg, 68.68 microseconds) is substantially equal to the read time T_read (eg, 68 microseconds).

[0075] For a better understanding, this method can be Figure 3 The process is illustrated in the flowchart, but the present invention is not limited thereto. According to some embodiments, one or more steps may be performed in Figure 3 Add, delete or modify the workflow shown.

[0076] Figure 4 FIG. 1 is a schematic diagram of a working process of the method according to an embodiment of the present invention. The memory device 100 (or the memory controller 110 therein) may be configured to: Figure 4 Follow the workflow shown.

[0077] In step S20 , the memory device 100 (or the memory controller 110 ) may receive a first command from the host device 50 through the transmission interface circuit 118 of the memory controller 110 , wherein the first command may indicate a request to read first data at a first logical address (eg, logical address L_Addr).

[0078] In step S21, the memory device 100 (or the memory controller 110) may check the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) to generate a first check result, start a first read operation according to the first check result, and check the temporary physical-to-logical address mapping table 117T corresponding to the active block 220 to generate a second check result, so as to selectively perform a second read operation according to the second check result. For example, the operation of step S21 may include:

[0079] (1) The memory device 100 (or the memory controller 110) may perform the operation of step S12 to check the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) to obtain the first physical address P_Addr1 associated with the logical address L_Addr from the global logical-to-physical address mapping table 120T as a first checking result, wherein the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) may be used to map the logical address L_Addr to the first physical address P_Addr1 to allow the memory controller 110 to perform a first read operation according to the first physical address P_Addr1, in particular, in step S13, the flash memory 120 is triggered by a first non-volatile read command (e.g., a flash read command) to start reading at the first physical address P_Addr1 associated with the logical address L_Addr; and

[0080] (2) The memory device 100 (or the memory controller 110) may search the logical address L_Addr in the temporary physical-to-logical address mapping table 117T as mentioned in step S13 to check the temporary physical-to-logical address mapping table 117T corresponding to the active block 220, so as to try to obtain any of the physical addresses (e.g., the second physical address P_Addr2) associated with the logical address L_Addr according to the temporary physical-to-logical address mapping table 117T as the second checking result;

[0081] Whether to perform the second read operation may depend on whether the logical address L_Addr is found in the temporary physical-to-logical address mapping table 117T.

[0082] For example, if the logical address L_Addr is found in the temporary physical-to-logical address mapping table 117T (e.g., the determination result of step S14 is “yes”), the memory controller 110 may be used to perform a second read operation according to any of the physical addresses (e.g., the second physical address P_Addr2) associated with the logical address L_Addr, and in particular, trigger the flash memory 120 with a second non-volatile read command (e.g., other flash read commands) to start reading at the second physical address P_Addr2 associated with the logical address L_Addr (step S15); otherwise (e.g., the determination result of step S14 is “no”), the memory controller 110 may be used to prevent the second read operation from being performed. In addition, the second check result may indicate whether the logical address L_Addr is found in the temporary physical-to-logical address mapping table 117T, so as to determine whether to perform the second read operation, but the present invention is not limited thereto. According to certain embodiments, if the logical address L_Addr is searched in the temporary physical-to-logical address mapping table 117T (for example, the judgment result of step S14 is "yes"), the memory controller can be used to judge any of the above-mentioned physical addresses associated with the logical address L_Addr (for example, the second physical address P_Addr2) as the second check result; otherwise (for example, the judgment result of step S14 is "no"), the memory controller 110 can be used to judge a null physical address P_Addr_Null that is not associated with the logical address as the second check result, wherein the null physical address P_Addr_Null can represent an invalid physical address (for example, a null value) and will not be associated with any logical address. For example, the memory controller 110 may call a search function among the plurality of functions of the memory controller 110 to search for the logical address L_Addr in the temporary physical-to-logical address mapping table 117T (step S13), and the search function may return a second check result (eg, the second physical address P_Addr2 or a null physical address P_Addr_Null).

[0083] In step S22 , the memory device 100 (or the memory controller 110 ) may transmit the first data back to the host device 50 , wherein the first data may be read according to a check result between the first check result and the second check result. For example, if the logical address L_Addr is found in the temporary physical-to-logical address mapping table 117T (e.g., the determination result of step S14 is “yes”), the memory controller 110 may be used to obtain a second check result (e.g., the second physical address P_Addr2) and perform a second read operation according to the second physical address P_Addr2. In particular, a second non-volatile read command (e.g., other flash read commands) may be used to trigger the non-volatile memory 120 to start reading at the second physical address P_Addr2 associated with the logical address L_Addr (step S15), and the data read at the second physical address P_Addr2 is returned to the host device 50 as the first data (step S16); otherwise (e.g., the determination result of step S14 is “no”), the memory controller 110 may be used to return the data read at the first physical address P_Addr1 to the host device 50 as the first data (step S17).

[0084] In step S23, the memory device 100 (or the memory controller 110) may determine whether to perform the next operation according to whether there is any new host-side event (e.g., any new host-side event of step S18, such as any new command described above). If yes (e.g., before the predetermined waiting time expires, the memory controller 110 detects any new host-side event described above), the process proceeds to step S20; if no (e.g., before the predetermined waiting time expires, the memory controller 110 does not detect any host-side event), the process proceeds to step S21. Figure 4 The illustrated workflow ends. For example, the operation of step S23 is similar to or the same as the operation of step S18.

[0085] For example, a first time period T1 (t11, t12) (e.g., read time T_read, such as 68 microseconds) between a first starting time point t11 ​​at which the memory controller 110 starts to check at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) and a first ending time point t12 at which the memory controller 110 completes a first read operation is usually greater than a second time period T2 (t21, t22) (e.g., search time T_search, such as 15 microseconds) between a second starting time point t21 at which the memory controller 110 starts to check the temporary physical-to-logical address mapping table 117T and a second ending time point t22 at which the memory controller 110 completes checking the temporary physical-to-logical address mapping table 117T. The memory controller 110 may be used to control the second starting time point t21 to be equal to or later than the first starting time point t11, so as to hide the second time period T2 (t21, t22) in the first time period T1 (t11, t12) for checking the temporary physical-to-logical address mapping table 117T. In addition, the first time period T1 (t11, t12) for checking the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T) and for performing the first read operation may include the second time period T2 (t21, t22) for checking the temporary physical-to-logical address mapping table 117T. For the sake of brevity, similar contents of this embodiment will not be described in detail again.

[0086] For a better understanding, this method can be Figure 4 The process is illustrated in the flowchart, but the present invention is not limited thereto. According to some embodiments, one or more steps may be performed in Figure 4 Add, delete or modify the workflow shown.

[0087] According to some embodiments, the first check result may represent the first physical address P_Addr1 associated with the logical address L_Addr indicated by the at least one logical-to-physical address mapping table (e.g., the global logical-to-physical address mapping table 120T). In addition, according to whether the logical address L_Addr is found in the temporary physical-to-logical address mapping table 117T, the memory controller 110 may be used to determine a selected physical address from at least one candidate physical address (e.g., one or more candidate physical addresses) for reading data at the selected physical address as the first data, wherein the selected physical address may be selected from the at least one candidate physical address, and the at least one candidate physical address may include the first physical address P_Addr1. For example, if the logical address L_Addr is found in the temporary physical-to-logical address mapping table 117T, the second check result may represent the second physical address P_Addr2 associated with the logical address L_Addr indicated by the temporary physical-to-logical address mapping table 117T, wherein the at least one candidate physical address may further include the second physical address P_Addr2; otherwise, the at least one candidate physical address may only include the first physical address P_Addr1. For the sake of brevity, similar contents of these embodiments are not repeatedly described in detail.

[0088] Figure 5 Schematic diagram of a block expansion control scheme of the method according to an embodiment of the present invention. For example, the plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N may be implemented as a plurality of flash memory chips (e.g., chip #0 and chip #1) or a plurality of flash memory bare die (e.g., bare die #0 and bare die #1), wherein the plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N may include at least two memory elements 122-1 and 122-2 (e.g., chip #0 and chip #1, or bare die #0 and bare die #1; for simplicity, in Figure 5 In some embodiments, the wafer count of the plurality of flash memory wafers or the die count of the plurality of flash memory dies may vary.

[0089] Any non-volatile memory element 122-n (e.g., any one of chip #0 and chip #1, or any one of die #0 and die #1) among the plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N may include a plurality of planes (e.g., plane #0 and plane #1), wherein any one of plane #0 and plane #1 of any non-volatile memory element 122-n (e.g., any one of chip #0 and chip #1, or any one of die #0 and die #1) may include its own block {BLK}, such as block {BLK(0), BLK(1), ...}. Under the control of the memory controller 110, the memory device 100 may combine a set of first corresponding blocks {BLK(0)} in all planes (e.g., plane #0 and plane #1) of all non-volatile memory elements (e.g., chip #0 and chip #1, or die #0 and die #1) into a first super block XBLK(0), but the present invention is not limited thereto. For example, the memory device 100 may combine a plurality of sets of corresponding blocks {BLK} (e.g., blocks {{BLK(0)}, {BLK(1)}, ...}) in all planes (e.g., plane #0 and plane #1) of all non-volatile memory elements (e.g., chip #0 and chip #1, or die #0 and die #1) into a plurality of super blocks {XBLK} (e.g., super blocks {XBLK(0), XBLK(1), ...}). In addition, the memory controller 110 may access (e.g., read or write) a plurality of corresponding blocks {BLK} (e.g., blocks {{BLK(0)}, {BLK(1)}, ...}) in the super blocks {XBLK(0), XBLK(1), ...} according to a plurality of physical block addresses (PBA) {XBlk} (e.g., physical block addresses {XBlk(0), XBlk(1), ...}), and in particular, may access (e.g., read or write) a corresponding page {PG} (e.g., page {PG(0), PG(1), ...}) in the super blocks {XBLK(0), XBLK(1), ...} according to a plurality of physical block addresses (PBA) {XBlk} (e.g., physical block addresses {XBlk(0), XBlk(1), ...}). For better understanding, it is assumed that "r0" and "r1" may be non-negative integers. Figure 5The blocks {BLK(r0)} in the same row (e.g., the blocks {BLK(0)} in the first row and the blocks {BLK(1)} in the second row) can represent a group of corresponding blocks {BLK(r0)} accessed by the same physical block address XBlk(r0), and in particular, can be a super block XBLK(r0) among the multiple super blocks {XBLK}. Figure 5 The pages {PG(r1)} in the same row shown (for example, the pages {PG(0)} in the first row and the pages {PG(1)} in the second row) can represent a group of corresponding pages {PG(r1)} accessed by the same physical page address XPg(r1), and in particular, can be a super page XPG(r1) among multiple super pages {XPG} (for example, super pages {XPG(0), XPG(1),…}).

[0090] Table 1

[0091] Logical address Physical Address LBA0 XBlk(5),XPg(0) LBA1 XBlk(5),XPg(1) LBA2 XBlk(5),XPg(2) LBA3 XBlk(5),XPg(3) LBA4 XBlk(5),XPg(4) LBA5 XBlk(5),XPg(5) LBA6 XBlk(5),XPg(6) LBA7 XBlk(5),XPg(7) LBA8 XBlk(6),XPg(19) LBA9 XBlk(5),XPg(9) LBA10 XBlk(14),XPg(17) LBA11 XBlk(5),XPg(11) LBA12 XBlk(5),XPg(12) LBA13 XBlk(5),XPg(13) LBA14 XBlk(5),XPg(14) LBA15 XBlk(5),XPg(15) … …

[0092] Table 2

[0093]

[0094]

[0095] Table 1 shows an example of a local logical-to-physical address mapping table (e.g., the first local logical-to-physical address mapping table, which may correspond to a logical address range) within the global logical-to-physical address mapping table 120T, and Table 2 shows an example of a temporary physical-to-logical address mapping table 117T, wherein the symbol "..." may indicate that some table contents may be deleted, but the present invention is not limited thereto. According to some embodiments, the contents, format, etc. of the local logical-to-physical address mapping table shown in Table 1 and / or the contents, format, etc. of the temporary physical-to-logical address mapping table 117T shown in Table 2 may be changed. For example, since the order and / or arrangement of the table contents in Table 1 may correspond to logical addresses {LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6, LBA7, LBA8, LBA9, LBA10, LBA11, LBA12, LBA13, LBA14, LBA15, …} (for example, logical block addresses (LBA) {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, …}), the field “Logical Address” in Table 1 may be deleted. For another example, since the sorting and / or arrangement of the table contents in Table 2 may correspond to physical addresses XPg(0), XPg(1), XPg(2), XPg(3), XPg(4), XPg(5), XPg(6), XPg(7), XPg(8), …} (for example, physical page addresses {0, 1, 2, 3, 4, 5, 6, 7, 8, …}), the field “Physical Address” in Table 2 may be deleted.

[0096] Based on the block expansion control scheme, the memory device 100 (or the memory controller 110 therein) can access the multiple super blocks {XBLK} (e.g., their super pages {XPG}) to access the corresponding blocks {BLK} (e.g., their corresponding pages). In particular, the host device 50 can store data in one or more super blocks {XBLK} (e.g., their super pages {XPG}) among the multiple super blocks {XBLK}, and read the stored data from the one or more super blocks {XBLK} (e.g., their super pages {XPG}) for transmission back to the host device 50. For example, L_Addr=LBA13, and the first command mentioned in step S20 may indicate a request to read the first data located at the logical address L_Addr (for example, the logical address LBA13), the memory device 100 (or the memory controller 110 therein) may check the above-mentioned at least one logical to physical address mapping table (for example, the local logical to physical address mapping table shown in Table 1) to generate a first check result, and start to perform a first read operation according to the first check result (step S21). In addition, the memory device 100 (or the memory controller 110 therein) may check the temporary physical-to-logical address mapping table 117T (e.g., the temporary physical-to-logical address mapping table 117T shown in Table 2) corresponding to a certain active super block (e.g., active super block #18) to generate a second check result for selectively performing a second read operation (step S21) based on the second check result, wherein the at least one active block (e.g., active block 220) may be implemented by at least one super block (e.g., active super block XBLK(18) at physical block address XBlk(18)).

[0097] Since the logical address L_Addr (e.g., logical address LBA13) is searched in the temporary physical-to-logical address mapping table 117T shown in Table 2, the latest address mapping relationship for the logical address L_Addr (e.g., logical address LBA13) is indicated by the physical-to-logical item (6, LBA13) in the temporary physical-to-logical address mapping table 117T shown in Table 2 (e.g., the temporary physical-to-logical address mapping table 117T corresponding to the active super block #18), rather than by the logical-to-physical item (LBA13, (XBlk(5), XPg(13))) in the local logical-to-physical address mapping table shown in Table 1. Therefore, the memory device 100 (or the memory controller 110 therein) can obtain the second physical address P_Addr2 (e.g., the physical address (XBlk(18), XPg(6)), which can include the physical block address XBlk(18) and the physical page address XPg(6)) and perform a second read operation according to the second physical address P_Addr2 (e.g., the physical address (XBlk(18), XPg(6))). In particular, the non-volatile memory 120 can be triggered by a second non-volatile read command (e.g., other flash read commands) to start reading at the physical address (XBlk(18), XPg(6)) and transmit the data read at the physical address (XBlk(18), XPg(6)) back to the host device 50 as the first data. For the sake of brevity, similar contents of this embodiment will not be described in detail again.

[0098] According to some embodiments, since the memory controller 110 may load the local logical-to-physical address mapping table (e.g., the first local logical-to-physical address mapping table) in the global logical-to-physical address mapping table 120T into the random access memory 116 as the temporary logical-to-physical address mapping table 116T, the temporary logical-to-physical address mapping table 116T may be implemented as the local logical-to-physical address mapping table shown in Table 1. For the sake of brevity, similar contents of these embodiments will not be described in detail again.

[0099] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for managing data access of a memory device in a predetermined communication architecture by means of multi-table checking, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the method comprising: Using the memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller, wherein the first command indicates a request to read first data located at a first logical address; Checking at least one logical-to-physical address mapping table to generate a first check result, starting a first read operation based on the first check result, and checking a temporary physical-to-logical address mapping table corresponding to a first active block to generate a second check result for selectively performing a second read operation based on the second check result; and The first data is transmitted back to the host device, wherein the first data is read according to an inspection result of the first inspection result and the second inspection result.

2. The method according to claim 1, characterized in that The step of checking the at least one logical to physical address mapping table to generate the first checking result comprises: Check the at least one logical-to-physical address mapping table to obtain a first physical address associated with the first logical address from the at least one logical-to-physical address mapping table as the first check result, wherein the at least one logical-to-physical address mapping table is used to map the first logical address to the first physical address.

3. The method according to claim 1, characterized in that The step of checking the temporary physical-to-logical address mapping table corresponding to the first active block to generate the second checking result comprises: checking the temporary physical-to-logical address mapping table corresponding to the first active block by searching the first logical address in the temporary physical-to-logical address mapping table, so as to try to obtain any physical address associated with the first logical address according to the temporary physical-to-logical address mapping table as the second checking result; Whether to perform the second read operation depends on whether the first logical address is found in the temporary physical-to-logical address mapping table.

4. The method according to claim 3, characterized in that If the first logical address is found in the temporary physical-to-logical address mapping table, the memory controller is used to perform the second read operation according to the any physical address associated with the first logical address; Otherwise, the memory controller is configured to prevent the second read operation from being performed.

5. The method according to claim 3, characterized in that The second checking result indicates whether the first logical address is found in the temporary physical-to-logical address mapping table, so as to determine whether to perform the second reading operation.

6. The method according to claim 3, characterized in that If the first logical address is found in the temporary physical-to-logical address mapping table, the memory controller is used to determine any physical address associated with the first logical address as the second inspection result; otherwise, the memory controller is used to determine an empty physical address not associated with a logical address as the second inspection result.

7. The method according to claim 1, characterized in that The first check result represents a first physical address associated with the first logical address indicated by the at least one logical-to-physical address mapping table; and based on whether the first logical address is searched in the temporary physical-to-logical address mapping table, the memory controller is used to determine a selected physical address from at least one candidate physical address for reading data at the selected physical address as the first data, wherein the selected physical address is selected from the at least one candidate physical address, and the at least one candidate physical address includes the first physical address.

8. The method according to claim 7, characterized in that If the first logical address is found in the temporary physical-to-logical address mapping table, the second check result represents a second physical address associated with the first logical address indicated by the temporary physical-to-logical address mapping table, wherein the at least one candidate physical address also includes the second physical address; otherwise, the at least one candidate physical address only includes the first physical address.

9. The method according to claim 1, characterized in that A first time period between a first starting time point at which the memory controller starts checking the at least one logical-to-physical address mapping table and a first ending time point at which the memory controller completes the first read operation is greater than a second time period between a second starting time point at which the memory controller starts checking the temporary physical-to-logical address mapping table and a second ending time point at which the memory controller completes checking the temporary physical-to-logical address mapping table, wherein the memory controller is used to control the second starting time point to be equal to or later than the first starting time point so as to hide the second time period in the first time period for checking the temporary physical-to-logical address mapping table.

10. The method according to claim 1, characterized in that A first time period between a first starting time point at which the memory controller starts checking the at least one logical-to-physical address mapping table and a first ending time point at which the memory controller completes the first read operation is greater than a second time period between a second starting time point at which the memory controller starts checking the temporary physical-to-logical address mapping table and a second ending time point at which the memory controller completes checking the temporary physical-to-logical address mapping table, wherein the first time period used to check the at least one logical-to-physical address mapping table and to perform the first read operation includes the second time period used to check the temporary physical-to-logical address mapping table.

11. A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the memory controller comprising: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is used to perform data access management of the memory device in a predetermined communication architecture by means of multi-table checking; as well as a transmission interface circuit for communicating with the host device; in: The memory controller receives a first command from the host device through the transmission interface circuit of the memory controller, wherein the first command indicates a request to read first data located at a first logical address; The memory controller checks at least one logical-to-physical address mapping table to generate a first check result, starts a first read operation according to the first check result, and checks a temporary physical-to-logical address mapping table corresponding to a first active block to generate a second check result for selectively performing a second read operation according to the second check result; and The memory controller returns the first data to the host device, wherein the first data is read according to a check result of the first check result and the second check result.

12. A memory device comprising the memory controller according to claim 11, wherein the memory device comprises: The non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

13. An electronic device comprising the memory device of claim 12, and further comprising: The host device is coupled to the memory device, wherein the host device includes: at least one processor for controlling the operation of the host device; as well as a power supply circuit coupled to the at least one processor and configured to provide power to the at least one processor and the memory device; The memory device provides storage space for the host device.

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