Data format adjustable cordic algorithm circuit implementation method

Abstract

The invention relates to a cordic algorithm circuit implementation method with an adjustable data format, which comprises the following steps: a data type selection circuit outputs an iteration array with a q1.31 data format or a q1.15 data format to an iteration circuit unit according to a data selection signal datasel; and the iterative circuit unit is used for realizing calculation of a cordic algorithm according to the iterative array in the q1.31 data format or the q1.15 data format. The invention provides a CORDIC algorithm circuit capable of selecting a data format bit q1.31 or q1.15, the use selectivity is improved, and when the CORDIC algorithm circuit is made of the CORDIC algorithm circuit, the implementation of an algorithm is not single, the application of the algorithm is not single, the implementation of the algorithm is more diversified, and the practicability of a user is improved.

Description

Technical Field

[0001] The invention belongs to the field of digital circuits, in particular to a method for realizing a cordic algorithm circuit with adjustable data format. Background Art

[0002] With the continuous improvement of integrated circuit technology, the integration of chips has been greatly improved. The application of high-performance embedded microprocessors is becoming more and more extensive, and the requirements for their processing capabilities are becoming higher and higher. At the same time, more and more algorithm circuits are used in today's chips, and the requirements for their performance are very strict. Therefore, in order to meet the application needs of embedded microprocessors, it is necessary to find ways to study the feasibility of algorithm circuits.

[0003] In applications such as image processing, electronic compass, and navigation control systems, a large number of function calculations are frequently used, especially the application of CORDIC algorithms. In embedded systems with large computing requirements, traditional implementation methods generally only support one of the two data formats, q1.31 and q1.15, and the selectivity is not fully utilized. Different modules or systems are required for different data formats, and the support for data formats is very limited, and it is impossible to support the operation of multiple data. Summary of the invention

[0004] The content of the present invention is to provide an algorithm circuit that supports both the q1.31 data structure and the q1.15 data structure. The present invention is used to make the algorithm circuit, so that the configuration of the algorithm circuit is diversified, and the user's choice is more diverse, and it is no longer limited to a circuit structure that only supports one data structure.

[0005] The technical solution adopted by the present invention to achieve the above-mentioned purpose is: a cordic algorithm circuit with adjustable data format, comprising:

[0006] A data type selection circuit, used for outputting an iteration array in a q1.31 data format or a q1.15 data format to an iteration circuit unit according to a data selection signal data_sel;

[0007] The iterative circuit unit is used to implement the calculation of the Cordic algorithm according to the iterative array in the Q1.31 data format or the Q1.15 data format.

[0008] The data type selection circuit adopts a selector, and the selector selects the iteration array of 32-bit q1.31 data format or the iteration array of 16-bit q1.15 data format to the iteration circuit unit according to the selection signal data_sel of the data 1-bit data format control bit;

[0009] The 32-bit q1.31 data format iteration array is used to store the 32-bit θ n =tan -1 (d n 2 -n ) value, the 16-bit q1.15 data format iteration array is used to store the 16-bit θ n =tan -1 (d n 2 -n ) value; θ n Represents the rotation angle in the algorithm, d n It indicates the direction of rotation in the algorithm, and n indicates the number of rotations in the algorithm.

[0010] The iterative array of the q1.31 data format or q1.15 data format is represented as follows:

[0011] arctan(2 -i ),i=0,1,2,3......15

[0012] Here, i is the number of iterations.

[0013] The iterative circuit unit is implemented by a hardware description language, and the multiplication and division operations in the cordic algorithm are implemented by shift operations, the multiplication operation is implemented by left shift, and the division operation is implemented by right shift;

[0014] The iterative circuit unit includes multiple stages of operation units connected in sequence, and the first stage operation unit inputs the parameters in the cordic algorithm;

[0015] The i-th level operation unit is used to receive the output of the previous level operation unit, implement a shift operation according to the iteration array of the i-th iteration in the iteration array, and then output the result to the next level operation unit;

[0016] The final operation unit outputs the result of the cordic algorithm.

[0017] A method for realizing a cordic algorithm circuit with adjustable data format comprises the following steps:

[0018] The data type selection circuit outputs an iteration array in a q1.31 data format or a q1.15 data format to the iteration circuit unit according to a data selection signal data_sel;

[0019] The iterative circuit unit implements the calculation of the Cordic algorithm according to the iterative array in the Q1.31 data format or the Q1.15 data format.

[0020] The data selection signal data_sel is at a low level, and the iterative circuit unit performs calculations in the q1.31 data format, and the calculation result is 32 bits; the data selection signal data_sel is at a high level, and the iterative circuit unit performs calculations in the q1.15 data format, and the calculation result is 16 bits;

[0021] In the q1.31 data format, the iteration array consists of a sign bit and 31 decimal places, and the data range is -1 (0x80000000) to 1-2 -31 (0x7FFFFFF);

[0022] In the q1.15 data format, the iteration array consists of a sign bit and 15 decimal places, and the data range is -1 (0x8000) to 1-2 -15 (0x7FFF).

[0023] The present invention has the following beneficial effects and advantages:

[0024] 1. Based on the CORDIC algorithm principle, the present invention can design RTL codes of other trigonometric functions through formula deformation, and integrate them into MCU to solve the problem that most CPUs lack hardware support for trigonometric functions, and also solve the problem that pure software implementation of the algorithm occupies a large amount of CPU resources. It can be applied to embedded systems with large computing requirements and has high practical value.

[0025] 2. The present invention provides a CORDIC algorithm circuit that can select the data format bit q1.31 or q1.15, thereby improving the selectivity of use. The present invention is used to make a CORDIC algorithm circuit, so that the implementation of the algorithm is no longer single, the application of the algorithm is no longer single, and the algorithm implementation is more diversified, thereby improving the practicality of users.

[0026] 3. In embedded systems with high computing requirements, no redundant modules or systems are required for different data formats, and operations on multiple data are supported. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The algorithm circuit structure diagram for q1.31 and q1.15 data formats;

[0028] Figure 2 This is a block diagram for algorithm circuit application. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0030] The present invention discloses a method for realizing a Cordic algorithm circuit with adjustable data format. The adjustable data format means that the algorithm supports Q1.15 data format calculation and also supports Q1.31 data format through configuration. The algorithm is realized by using a 1-bit configuration bit. When the bit is 0, the algorithm is configured with Q1.31 data format. When the bit is 1, the algorithm is configured with Q1.15 data format. This implementation method makes the algorithm more diversified and enriches its practicality.

[0031] 1. The data format adjustable cordic algorithm circuit includes: configuration signal interface, 1-bit data format control bit data_sel, clock signal clk, 32-bit iteration array, 16-bit iteration array. These two arrays are used to store θ n =tan -1 (d n 2 -n ), an array for the θ in q1.15 data format n =tan -1 (d n 2 -n ) to store the values, and another array for θ in q1.31 data format n =tan -1 (d n 2 -n )'s storage value.

[0032] 2. The algorithm involves many multiplication and division operations, which are implemented in the code using shift operations. Multiplication operations are implemented using left shifts, and division operations are implemented using right shifts.

[0033] 3. This algorithm is designed to use fixed-point signed integer input and output. The input and output results can be in q1.15 or q1.31 data format. In the q1.15 data format, the data consists of a sign bit and 31 decimal places (binary decimals), so the data range is -1 (0x80000000) to 1-2 -31 (0x7FFFFFF). In the q1.15 data format, the data consists of a sign bit and 15 decimal places (binary decimals), so the data range is -1 (0x8000) to 1-2 -15 (0x7FFF). It is controlled by a 1-bit signal line. When the signal line is low, the code performs calculations in the q1.31 data format and the result is 32 bits. When the signal line is high, the code performs calculations in the q1.15 data format and the result is 16 bits.

[0034] 4. The so-called q1.15 data format is to compensate the precision of a decimal, that is, to expand it by 2. ^15 times, calculate the obtained data, and the final result is scaled by 2 ^15The result is the required calculation result. Similarly, the q1.31 data format also performs the same processing on the data, but the scaling or enlargement multiples are different. The scaling or enlargement multiple of the q1.31 data format is 2 ^31 times.

[0035] As shown in Table 1, the array required for the implementation of the q1.31 and q1.15 data formats of the present invention is shown. The elements in the array are arctan(2 -i ), i = 0, 1, 2, 3... 15. These values ​​are used as iteration factors in the algorithm iteration process according to the specific principles of the algorithm.

[0036] Table 1q1.31 and q1.15 data format array

[0037] i <![CDATA[arctan(2 -i )]]> q1.31 q1.15 0 45° 0x20000000 0x2000 1 26.56505118° 0x12E4 051D 0x12E4 2 14.03624347° 0x9FB 385B 0x09FB 3 7.125016349° 0x511 11D4 0x0511 4 3.576334375° 0x28B 0D43 0x028B 5 1.789910608° 0x145 D7E1 0x0145 6 0.8951737102° 0xA2 F61E 0x00A2 7 0.4476141709° 0x51 7C55 0x0051 8 0.2238105004° 0x28 BE53 0x0028 9 0.1119056771° 0x14 5F2E 0x0014 10 0.05595289189° 0xA 2F98 0x000A 11 0.02797645262° 0x5 17CC 0x0005 12 0.01398822714° 0x2 8BE6 0x0002 13 0.006994113675° 0x1 45F3 0x0001 14 0.003497956851° 0xA304 0x0000 15 0.001748528427° 0x517C 0x0000

[0038] The q1.31 and q1.15 data in Table 1 are calculated by arctan(2 -i ) is divided by 180° and then multiplied by 2 ^31 Get the q1.31 data format. Similarly, the q1.15 data format is multiplied by 2. ^15 get.

[0039] First, when designing the RTL code, the array structure supporting the two data structures described in Table 1 is integrated into the design using the hardware description language to prepare for subsequent design. Figure 1 As shown, the algorithm circuit structure supports the q1.31 and q1.15 data formats.

[0040] like Figure 1 As shown, the dashed box is the iteration circuit, and the dashed box is the data type selection circuit. When the data type selection circuit data_sel is 0, the selector whose selection end is connected to the data_sel selection signal outputs the iteration factor of the q1.31 data format. When the data type selection circuit data_sel signal is 1, the selector whose selection end is connected to the data_sel selection signal outputs the iteration factor of the q1.15 data format, which is the array element mentioned in Table 1. At the same time, if the q1.31 or q1.15 data format is selected, the data calculated by the algorithm iteration must also be converted into the q1.31 or q1.15 data format.

[0041] like Figure 2As shown, the algorithm circuit structure diagram includes two parts: the configuration circuit (config) and the algorithm circuit (cordic). The main function of the configuration circuit is to write the data in_data calculated by the algorithm iteration to the algorithm circuit. in_data can be 32-bit q1.31 data format data or 16-bit q1.15 data format data. The data format of in_data determines whether the data_sel signal output by the module to the algorithm circuit is 0 or 1. When the signal is 0, it indicates that the data in_data iterated by the algorithm is in the 32-bit q1.31 data format. When the signal is 1, it indicates that the data in_data iterated by the algorithm is in the 16-bit q1.15 data format. These signals are passed to the algorithm circuit. The algorithm circuit will take out the corresponding iteration factor from the data format array according to whether the input signal data_sel is 0 or 1, as shown below. Figure 1 The process shown performs iterative calculations on the data and finally outputs the correct results.

Claims

1. A cordic algorithm circuit with adjustable data format, characterized in that: include: A data type selection circuit, used for outputting an iteration array in a q1.31 data format or a q1.15 data format to an iteration circuit unit according to a data selection signal data_sel; The iterative circuit unit is used to implement the calculation of the Cordic algorithm according to the iterative array in the Q1.31 data format or the Q1.15 data format.

2. A cordic algorithm circuit with adjustable data format according to claim 1, characterized in that: The data type selection circuit adopts a selector, and the selector selects the iteration array of 32-bit q1.31 data format or the iteration array of 16-bit q1.15 data format to the iteration circuit unit according to the selection signal data_sel of the data 1-bit data format control bit; The 32-bit q1.31 data format iteration array is used to store the 32-bit θ n =tan -1 (d n 2 -n ) value, the 16-bit q1.15 data format iteration array is used to store the 16-bit θ n =tan -1 (d n 2 -n ) value; θ n Represents the rotation angle in the algorithm, d n It indicates the direction of rotation in the algorithm, and n indicates the number of rotations in the algorithm.

3. A cordic algorithm circuit with adjustable data format according to claim 2, characterized in that: The iterative array of the q1.31 data format or q1.15 data format is represented as follows: arctan(2 -i ),i=0,1,2,3......15 Here, i is the number of iterations.

4. The cordic algorithm circuit with adjustable data format according to claim 1, characterized in that: The iterative circuit unit is implemented by a hardware description language, and the multiplication and division operations in the cordic algorithm are implemented by shift operations, the multiplication operation is implemented by left shift, and the division operation is implemented by right shift; The iterative circuit unit includes multiple stages of operation units connected in sequence, and the first stage operation unit inputs the parameters in the cordic algorithm; The i-th level operation unit is used to receive the output of the previous level operation unit, implement a shift operation according to the iteration array of the i-th iteration in the iteration array, and then output the result to the next level operation unit; The final operation unit outputs the result of the cordic algorithm.

5. A method for implementing a cordic algorithm circuit with adjustable data format, characterized in that: The following steps are involved: The data type selection circuit outputs an iteration array in a q1.31 data format or a q1.15 data format to the iteration circuit unit according to a data selection signal data_sel; The iterative circuit unit implements the calculation of the Cordic algorithm according to the iterative array in the Q1.31 data format or the Q1.15 data format.

6. The method for implementing a cordic algorithm circuit with adjustable data format according to claim 5, characterized in that: The data selection signal data_sel is at a low level, and the iterative circuit unit performs calculations in the q1.31 data format, and the calculation result is 32 bits; the data selection signal data_sel is at a high level, and the iterative circuit unit performs calculations in the q1.15 data format, and the calculation result is 16 bits; In the q1.31 data format, the iteration array consists of a sign bit and 31 decimal places, and the data range is -1 (0x80000000) to 1-2 -31 (0x7FFFFFF); In the q1.15 data format, the iteration array consists of a sign bit and 15 decimal places, and the data range is -1 (0x8000) to 1-2- 15 (0x7FFF).

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