Core particle integration system
By designing clock detection and repair circuits in the core-grain integrated system, the problem of poor or disconnection of the accompanying clock port between core-grain is solved, and the reliability and performance improvement of the high-speed interconnection interface between core-grain is achieved.
Patent Information
- Application Number
- CN202411334399.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-02-25
AI Technical Summary
In the core-grain integrated system, poor connection or disconnection between the accompanying clock ports between the cores will cause the high-speed interface to fail to work properly, affecting the yield and performance of the entire system.
A clock detection and repair circuit is designed, including a clock detection signal generator and a detection logic processor, which can accurately detect the connection status of the clock port and repair it in case of abnormalities to ensure the communication quality between core particles.
Through clock detection and repair circuits, the failure rate of the core-particle integrated system can be effectively reduced, and the performance of the high-speed interconnection interface between core-particle and the yield of the entire system can be improved.
Smart Images
Figure CN119513030A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip communication, and in particular relates to a chip-grain integration system. Background Art
[0002] As the requirements for computing power in high-performance computing continue to increase, it is increasingly difficult for a single-chip system to meet the performance requirements of high-performance computing. At the same time, the area of a single computing chip that can provide greater computing power is getting larger and larger, posing a greater challenge to the chip yield.
[0003] In this case, adopting a chiplet integrated system solution to meet the challenges of high-performance computing becomes an important means to solve the above problems. Different chiplets need to interact with each other frequently to complete related calculations. Therefore, the high-speed interconnect interface used for data transmission between chiplets becomes one of the most important components of the chiplet integrated system.
[0004] Among them, the physical layer of the high-speed interconnect directly processes high-speed data, and its performance directly affects the data transmission efficiency of the high-speed interconnect. The physical layer of the high-speed interconnect interface between chiplets usually adopts a source synchronization solution, that is, the accompanying clock and data synchronized with the data are sent at the same time at the transmitting end, and the accompanying clock is used to complete the data sampling at the receiving end. Therefore, the quality of the accompanying clock is a key factor in the implementation of the high-speed interface. If the accompanying clock port between chiplets is poorly connected or even disconnected during the assembly process of the chiplets, the entire high-speed interface will not work properly.
[0005] Since the yield of the chip assembly process is difficult to improve significantly in the short term, the design of the high-speed interface between chiplets needs to improve the quality of the accompanying clock from the perspective of circuit and system design and ensure its reliability, thereby improving the performance of the high-speed interconnection interface between chiplets and the yield of the entire chiplet integration system. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a clock detection and repair circuit suitable for a chiplet integrated system, which can more accurately detect poor connection or disconnection of the clock port and perform repairs to ensure the communication quality between chiplets.
[0007] To achieve the above-mentioned purpose and other related purposes, the present invention provides a chip integration system, including: a plurality of chiplets, and the chiplets are communicatively connected to each other to perform data receiving and sending operations; wherein each chiplet for receiving data is configured with a clock detection and repair circuit, and the clock detection and repair circuit includes: a clock detection signal generator, used to sample the original clock input by the chiplet according to a sampling clock of a first phase and a sampling clock of a second phase, respectively, and output corresponding first clock detection signals and second clock detection signals; the first phase and the second phase differ by 180 degrees, and the frequency of the sampling clock is consistent with the original clock; a detection logic processor, used to determine whether the original clock is abnormal based on the first clock detection signal and the second clock detection signal output by the clock detection signal generator, and repair it when it is abnormal.
[0008] According to a specific embodiment of the present invention, the clock detection and repair circuit also includes: a clock receiver, which is used to access the original clock and the repair clock input by the chiplet, and select the original clock or the repair clock to generate a receiving clock according to the clock selection signal output by the detection logic processor; wherein, when one chiplet performs data transmission and reception operations with another chiplet, the chiplet used to send data outputs the original clock and the repair clock to the chiplet used to receive data respectively.
[0009] According to a specific embodiment of the present invention, when the original clock is a differential clock signal, the clock receiver is used to select the repair clock to replace one or more abnormal channels in the original clock based on the clock selection signal output by the detection logic processor, so as to generate a received clock based on the original clock and the repair clock.
[0010] According to a specific embodiment of the present invention, the detection logic processor is used to compare whether the first clock detection signal and the second clock detection signal are both kept constant and have opposite polarities: if so, the original clock is considered normal, and a first clock selection signal is output to enable the clock receiver to select the original clock to generate a receiving clock; if not, the original clock is considered abnormal, and a second clock selection signal is output to enable the clock receiver to select the repair clock to generate a receiving clock, or to select the original clock and the repair clock to generate a receiving clock.
[0011] According to a specific embodiment of the present invention, the detection logic processor is used to detect pulse fluctuations in the first clock detection signal / second clock detection signal, and when the number of pulse fluctuations exceeds a preset threshold within a preset time, the original clock is considered to be abnormal, and a second clock selection signal is output to enable the clock receiver to select the repair clock to generate a receiving clock, or to select the original clock and the repair clock to generate a receiving clock.
[0012] According to a specific embodiment of the present invention, the chiplet for sending data continues to output a repair clock to the chiplet for receiving data until the data sending and receiving operation is completed.
[0013] According to a specific embodiment of the present invention, the chip for sending data outputs a repair clock after receiving a notification from the chip for receiving data until the data sending and receiving operation is completed; wherein, when the detection logic processor determines that the original clock is abnormal, the chip for receiving data initiates a notification to the chip for sending data.
[0014] According to a specific embodiment of the present invention, the clock receiver includes: at least two multiplexers, one of which is connected to one of the original clocks and the repaired clock respectively, and allows one of the original clocks / repaired clock to be output according to the clock selection signal output by the detection logic processor; a clock amplifier, which is used to amplify one of the original clocks and / or the repaired clock output by all multiplexers, and output the corresponding received clock; wherein the clock amplifier is also used to operate in differential mode or single-ended mode according to the clock selection signal output by the detection logic processor.
[0015] According to a specific embodiment of the present invention, when the clock selection signal output by the detection logic processor causes all multiplexers to output the repair clock, the clock amplifier is switched to a single-ended mode.
[0016] According to a specific embodiment of the present invention, the clock detection signal generator includes: at least one clock amplifier, which is used to access the original clock input by the core grain and amplify it; a reference level generator, which is used to provide a reference potential for the clock amplifier; at least one sampling circuit, which is set in a one-to-one correspondence with the clock amplifier, and the sampling circuit samples the amplified original clock according to the sampling clock of the first phase and the sampling clock of the second phase, and outputs the corresponding first clock detection signal and second clock detection signal; a phase shift circuit, which is used to access the sampling clock provided by the core grain, and adjust the initial phase of the sampling clock under the control of the detection logic processor to output the sampling clock of the first phase and the sampling clock of the second phase; a multiplexer, which is used to access the sampling clock of the first phase and the sampling clock of the second phase output by the phase shift circuit, and output them to the sampling circuit in sequence; wherein the sampling clock provided by the detection logic processor comes from the functional module inside the core grain.
[0017] The present invention provides a clock detection and repair circuit for a core-grain integrated system, which can fully detect the clock quality and the frequency stability of the clock, and replace the accompanying clock in an abnormal situation to complete the clock repair, thereby effectively reducing the system failure rate caused by assembly problems.
[0018] Different from the counter solution, the present invention does not need to count the high-frequency clock, but only samples the high-frequency clock, which greatly simplifies the logic processing in the high-frequency clock domain and optimizes the power consumption of the circuit. In addition, it can fully utilize the performance advantages of the differential clock and improve the quality of the received clock.
[0019] Part of the clock detection and repair circuit provided by the present invention can reuse relevant modules in the high-speed interconnect interface data receiving path, which is beneficial to reducing design complexity and shortening the research and development cycle.
[0020] The clock detection and repair circuit proposed in the present invention is mainly used in the physical layer implementation of the high-speed data transmission interface between chips, and can also be used in other circuits and systems requiring this function. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 A structural block diagram of a specific embodiment of a chip integration system provided by the present invention; Figure 2 A structural block diagram of a specific embodiment of a clock detection and repair circuit in a chip integrated system provided by the present invention; Figure 3 A waveform diagram of a specific embodiment of the clock signal provided by the present invention in a normal state; Figure 4 A waveform diagram of a specific embodiment of the clock signal disconnected state provided by the present invention; Figure 5 A waveform diagram of a specific embodiment of the clock signal poor connection state provided by the present invention; Figure 6 This is a structural block diagram of a specific embodiment of the clock receiver and clock detection signal generator provided by the present invention. DETAILED DESCRIPTION
[0022] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0024] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
[0025] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.
[0026] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.
[0027] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.
[0028] See also Figure 1 The chiplet integration system shown includes: a plurality of chiplets 10, and communication connections can be established between the chiplets to perform data transmission and reception operations. There are no requirements or restrictions on the model, quantity, size, etc. of the chiplets, and they can be configured according to the actual computing power requirements and space resource limitations. The challenge of high-performance computing can be achieved through high-frequency data interaction between different chiplets.
[0029] Specifically, different chiplets perform data transmission and reception operations through corresponding high-speed interconnect interfaces, but the traditional design scheme is not equipped with clock detection and repair circuits. When performing data transmission and reception operations, if the clock signal is disconnected or poorly connected, the entire interface will not work properly, thereby affecting the working state of the chiplet integrated system.
[0030] In this regard, in the present embodiment, the high-speed interconnection interface of each core particle is configured with a clock detection and repair circuit 20 to ensure the stable data interaction between different core particles. It can be understood here that the high-speed interconnection interface of the core particle includes a data transmission channel and / or a data receiving channel, as well as a clock transmission channel and / or a clock receiving channel. Since not every core particle needs to send and receive data, for example, the core particle has the ability to send and receive data, and can simultaneously have a data transmission channel and a data receiving channel, as well as a corresponding clock transmission channel and a clock receiving channel, or the core particle only has the ability to send data, and correspondingly only has a data transmission channel and a corresponding clock transmission channel, or the core particle only has the ability to receive data, and correspondingly only has a data receiving channel and a corresponding clock receiving channel. Therefore, it is only necessary to configure the clock detection and repair circuit 20 in the clock receiving channel of the core particle used to receive data.
[0031] Specifically, Figure 2 As shown, the clock detection and repair circuit 20 includes a clock receiver 21, a clock detection signal generator 22, and a detection logic processor 23. The clock receiver 21 takes the original clock and the repaired clock as input, selects the original or repaired clock, or the combination of the original clock and the repaired clock based on the clock selection signal provided by the detection logic processor 23, receives and processes the selected clock signal, generates a received clock and outputs it to the functional module inside the core particle. The clock detection signal generator 22 uses the local sampling clock to sample the original clock, generates a clock detection signal and sends it to the detection logic processor 23, and the detection logic processor 23 performs a logical operation according to the state of the clock detection signal to determine whether the quality of the original clock meets the communication quality requirements, and generates a clock selection signal and sends it to the clock receiver 21 to select the input clock signal.
[0032] It can be understood here that when a core particle exchanges data with another core particle, the core particle used to send data needs to write data to the core particle used to perform data read operations, so the accompanying clock signal is output by the core particle used to send data, and the core particle used to receive data reads data according to the clock signal provided by the core particle used to send data. It can also be understood that the accompanying clock signal mentioned above is the original clock output by the core particle used to send data, and the corresponding repair clock also needs to be provided and output by the core particle used to send data, so that the repair clock can be used to read data when the original clock is abnormal, thereby ensuring that the data exchange between the two core particles can proceed normally and maintain stable data transmission efficiency.
[0033] It should also be noted that both the original clock and the repair clock come from outside the core, while the sampling clock is provided by the corresponding functional module inside the core. In addition, in order to ensure that the original clock can be collected, the frequency of the sampling clock needs to be consistent with the original clock.
[0034] It can be seen that by configuring a clock detection and repair circuit 20 at the clock receiving channel of each chip used to receive data, the quality and stability of the accompanying clock signal can be effectively monitored, and repair can be performed when an abnormality occurs, thereby maintaining the normal data transmission and reception operations, greatly reducing the failure rate of the chip integrated system.
[0035] In a specific embodiment, the working states of the chiplet 10 and its corresponding clock detection and repair circuit 20 are as follows: When one chip starts to interact with another chip, chip A, as the chip for sending data, provides and outputs the digital electrical signal of the relevant data and the accompanying original clock, while chip B, as the chip for receiving data, reads the digital electrical signal of the relevant data based on the original clock. Therefore, chip B needs to be configured with a clock detection and repair circuit 20, and start working in this case to detect the quality and stability of the original clock.
[0036] Under normal working conditions, the original clock is used as the input clock signal, and the clock detection signal generator 22 first receives the original clock, and then uses the local sampling clock to sample the received clock. During the sampling process, the clock detection signal generator 22 can generate a sampling clock of the first phase and a sampling clock of the second phase according to the sampling clock provided by the internal functional module of the core particle under the control of the detection logic processor 23, and sample the original clock respectively. The clock detection signal generator 22 can also adjust the initial phases of the sampling clock of the first phase and the sampling clock of the second phase under the control of the detection logic processor 23, so that the sampling clock is in an appropriate sampling interval. Among them, the first phase and the second phase can differ by 180 degrees, for example, it can be a sampling clock with a phase of 0° and a sampling clock with a phase of 180°, or others, there are no excessive restrictions on this, and in this embodiment, the sampling clock with a phase of 0° and the sampling clock with a phase of 180° are taken as an example. For details, please refer to Figure 3As shown, CK_R is the original clock received by the clock detection signal generator 22, CK_S is the sampling clock, and the CK_S shown in the figure is a sampling clock with a 0° phase, which adopts rising edge sampling, while the sampling edge of the sampling clock with a 180° phase can be at the falling edge of the 0° phase sampling clock. CK_D is the clock detection signal obtained by sampling. Since the sampling clock with a 0° phase and the sampling clock with a 180° phase are respectively used for sampling, the first clock detection signal of CK_D (0°) and the second clock detection signal of CK_D (180°) can be obtained accordingly. In addition, it can be seen from the figure that when the original clock is normal, the clock detection signal remains constant and has opposite polarities in both sampling phases. In this state, since the original clock is normal, the repair clock does not need to participate in the work, and there can be no signal input (maintained at 0 or other constant levels). Therefore, the detection logic processor 23 can output the corresponding clock selection signal, that is, the first clock selection signal, so that the clock receiver 21 receives the original clock and generates a receiving clock.
[0037] It can be understood here that the detection logic processor 23 can perform logical calculations based on this characteristic of the clock detection signal obtained under two sampling phases to determine whether the original clock performance is normal, and give a corresponding clock selection signal to the clock receiver 21 to receive and process the original clock or the repaired clock.
[0038] Furthermore, when the original clock is disconnected or has other major problems, there is no signal input to the clock receiving channel of the core B. At this time, the clock detection signal generator 22 can still perform sampling according to the sampling clock with a 0° phase and the sampling clock with a 180° phase, and the result of the clock detection signal is as follows: Figure 4As shown, the first clock detection signal of CK_D (0°) and the second clock detection signal of CK_D (180°) remain constant but have the same polarity, which does not meet the condition that the two clock detection signals remain constant and have opposite polarities under normal conditions. Therefore, the detection logic processor 23 determines that the original clock signal is lost, and outputs the corresponding clock selection signal, that is, the second clock selection signal, so that the clock receiver 21 receives the repair clock and generates a receiving clock. It should be added here that the repair clock can be outputted constantly or only when the original clock is abnormal. There are no excessive restrictions on this, and it can be configured according to actual needs. For example, core A can continuously output the original clock and the repair clock, so that when the original clock is abnormal, the clock detection and repair circuit 20 of core B can use the repair clock to maintain the normal data transmission and reception operation. Alternatively, when the detection logic processor 23 recognizes that the original clock is abnormal, it will notify or enable the corresponding hardware module or software function inside core B accordingly, and then core B will notify core A to provide a repair clock to replace the original clock. Without departing from the spirit of the present invention, modifications and improvements made to the embodiments of the present invention by those skilled in the art will still fall within the scope of the invention application of the present invention.
[0039] When the original clock has other problems such as poor connection, due to the poor signal quality of the original clock, the original clock received by the clock detection signal generator 22 may have large jitter, unstable frequency or even pulse loss. All these clock waveform quality degradations will cause the sampled clock detection signal to have pulse fluctuations. Figure 5 As shown, a negative pulse can be observed on the first clock detection signal of CK_D (0°). It can be understood that when the original clock has the above-mentioned waveform quality degradation phenomenon, the sampling phase of the pulse and the way the pulse appears are not fixed, but pulse fluctuations will definitely occur. Figure 5For example, no excessive restrictions are imposed on this. Therefore, the detection logic processor 23 can determine that the original clock quality is poor based on this characteristic, and output a corresponding clock selection signal, i.e., a second clock selection signal, so that the clock receiver 21 receives the repair clock and generates a receiving clock. It should be noted here that if the connection between the clock transmission channel and the clock receiving channel between the core A and the core B is poor and thus affects the transmitted clock signal, as long as the observation time is long enough, pulse fluctuations will definitely appear on the clock detection signal obtained by sampling the original clock. Therefore, in actual applications, it is not simply determined that the original clock quality is poor when pulse fluctuations are detected, but the observation time and threshold are set in the detection logic processor 23. Only when the number of pulse fluctuations within the preset time reaches the preset threshold, the original clock quality is determined to be poor. For sporadic pulse fluctuations, it is not considered that there is a problem in the communication connection between the clock transmission channel and the clock receiving channel between the core A and the core B.
[0040] It can be seen that the monitoring and repair of the original clock can effectively ensure that the data interaction between coreparticle A and coreparticle B can be carried out stably and reliably.
[0041] In addition, the original clock mentioned in this embodiment can be a differential clock signal or a single-ended clock signal. When the original clock is a single-ended clock signal, the clock receiver 21 can generate a receiving clock by selecting the original clock or the repair clock according to the clock selection signal provided by the detection logic processor 23 as described above; when the original clock is a differential clock signal, the clock receiver 21 selects the repair clock to replace the abnormal one or more channels in the original clock according to the clock selection signal provided by the detection logic processor 23, that is, the receiving clock is generated according to the normal one or more channels in the original clock and the repair clock.
[0042] In this regard, in a specific embodiment, taking the special scenario of differential clock signal as an example, Figure 6As shown, the clock receiver 21 is composed of two multiplexers and a clock amplifier. Since the differential clock signal is two-way, one of the multiplexers can select the original clock CKP or the repair clock CK_RPR under the control of the clock selection signal CKP_SEL, and the other multiplexer can select the original clock CKN or the repair clock CK_RPR under the control of the clock selection signal CKN_SEL. In this configuration, the repair clock can be used to replace any one of the original clocks, and even when CKP and CKN have problems at the same time, they can be replaced with the repair clock CK_RPR. The clock signal output by the multiplexer is amplified by the clock amplifier, so that the rail-to-rail receiving clock CK_OUT is output. Among them, the clock amplifier can work in different modes under the control of the clock selection signals CKP_SEL and CKN_SEL. Generally, it works in differential mode, that is, one multiplexer outputs the original clock CKP / CKN, and the other multiplexer outputs the repair clock CK_RPR. It works in single-ended mode only when both multiplexers select the repair clock CK_RPR output, and a reference level generator is usually integrated inside the clock amplifier that supports this mode. It can be seen that this clock receiver structure fully utilizes the performance advantages of differential clocks while ensuring the flexibility of clock selection.
[0043] The clock detection signal generator 22 is composed of two clock amplifiers, two sampling circuits, a phase shift circuit, a multiplexer and a reference level generator. The clock amplifiers usually adopt a differential structure, one of which is the original clock input and the other is the reference potential VREF generated by the reference level generator. The two clock amplifiers complete the receiving processing of the two paths of the original clock respectively, and generate two clock signals CKP_R and CKN_R. The two sampling circuits sample the two clock signals CKP_R and CKN_R based on the sampling clock CK_S respectively, and obtain the sampling results CKP_D and CKN_D, which are the first clock detection signal and the second clock detection signal output to the detection logic processor 23. Among them, the sampling clock CK_S is generated by the local sampling clock CK_INT through the phase shift circuit and the multiplexer. First, the sampling clock CK_INT is provided by the functional module inside the core particle, and the phase shift circuit adjusts the initial phase of CK_INT under the phase control signal given by the detection logic processor 23, and performs a single-ended to differential operation to generate 0° phase and 180° phase sampling clocks CK_INTP and CK_INTN. The multiplexer supplies the two sampling clocks to the sampling circuit for sampling in sequence under the phase selection signal given by the detection logic processor 23, that is, the 0° phase and 180° phase sampling clocks CK_INTP and CK_INTN are supplied to one sampling circuit for sampling in sequence to determine whether the redirected original clock is abnormal, and are synchronously supplied to another sampling circuit for sampling to determine whether the other original clock is abnormal, thereby completing the diagnosis and repair of the two original clocks. Finally, the sampling results CKP_D and CKN_D output by the sampling circuit are used by the detection logic processor 23 to determine whether the original clock is disconnected or poorly connected, and output a corresponding clock selection signal to the clock receiver 21 .
[0044] It should be noted that, although the above implementation is presented in the form of a differential clock signal, it can also be used to detect and repair a single-ended original clock, which can be achieved by merging two differential clocks into one single-ended clock in the circuit. In addition, the clock signal is not limited to only two differential clock signals. When the original clock contains multiple channels, the clock receiver 21 can be provided with a corresponding number of multiplexers, and the clock detection signal generator 22 can be provided with a corresponding number of clock amplifiers and sampling circuits. There are no excessive restrictions on this. Without departing from the spirit of the present invention, the modifications and embellishments made to the embodiments of the present invention by those skilled in the art still fall within the scope of the invention application of the present invention.
[0045] In summary, the present invention provides a clock detection and repair circuit for a chip integrated system, which can fully detect the clock quality and frequency stability of the clock, and replace the accompanying clock when an abnormality occurs to complete the clock repair, effectively reducing the system failure rate caused by assembly problems.
[0046] Different from the counter solution, the present invention does not need to count the high-frequency clock, but only samples the high-frequency clock, which greatly simplifies the logic processing in the high-frequency clock domain and optimizes the power consumption of the circuit. In addition, it can fully utilize the performance advantages of the differential clock and improve the quality of the received clock.
[0047] Part of the clock detection and repair circuit provided by the present invention can reuse relevant modules in the high-speed interconnect interface data receiving path, which is beneficial to reducing design complexity and shortening the research and development cycle.
[0048] The clock detection and repair circuit proposed in the present invention is mainly used in the physical layer implementation of the high-speed data transmission interface between chips, and can also be used in other circuits and systems requiring this function.
[0049] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
[0050] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0051] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
Claims
1. A core particle integration system, characterized in that: include: A plurality of core particles, and the core particles are connected to each other for data transmission and reception operations; Each chiplet for receiving data is equipped with a clock detection and repair circuit, and the clock detection and repair circuit includes: A clock detection signal generator, used to sample the original clock input by the chip according to the sampling clock of the first phase and the sampling clock of the second phase, and output the corresponding first clock detection signal and second clock detection signal; the first phase and the second phase differ by 180 degrees, and the frequency of the sampling clock is consistent with the original clock; The detection logic processor is used to determine whether the original clock is abnormal according to the first clock detection signal and the second clock detection signal output by the clock detection signal generator, and to repair the original clock if it is abnormal.
2. The chip integration system according to claim 1, characterized in that: The clock detection and repair circuit also includes: A clock receiver, used for receiving the original clock and the repair clock input by the chiplet, and selecting the original clock or the repair clock to generate a receiving clock according to the clock selection signal output by the detection logic processor; When one chiplet performs data transmission and reception operations with another chiplet, the chiplet for transmitting data outputs an original clock and a repair clock to the chiplet for receiving data.
3. The chip integration system according to claim 2, characterized in that: When the original clock is a differential clock signal, the clock receiver is used to select the repair clock to replace one or more abnormal channels in the original clock according to the clock selection signal output by the detection logic processor, so as to generate a receiving clock according to the original clock and the repair clock.
4. The chip integration system according to claim 3, characterized in that: The detection logic processor is used to compare whether the first clock detection signal and the second clock detection signal are both kept constant and have opposite polarities: If yes, it is considered that the original clock is normal, and a first clock selection signal is outputted to enable the clock receiver to select the original clock to generate a receiving clock; If not, the original clock is considered abnormal, and a second clock selection signal is output to enable the clock receiver to select the repair clock to generate a receiving clock, or to select the original clock and the repair clock to generate a receiving clock.
5. The chip integration system according to claim 3, characterized in that: The detection logic processor is used to detect pulse fluctuations in the first clock detection signal / second clock detection signal, and when the number of pulse fluctuations exceeds a preset threshold within a preset time, the original clock is considered to be abnormal, and a second clock selection signal is output to enable the clock receiver to select the repair clock to generate a receiving clock, or to select the original clock and the repair clock to generate a receiving clock.
6. The chip integration system according to claim 2, characterized in that: The chip used for sending data continues to output the repair clock to the chip used for receiving data until the data sending and receiving operation is completed.
7. The chip integration system according to claim 2, characterized in that: The chiplet for sending data outputs a repair clock after receiving a notification from the chiplet for receiving data until the data sending and receiving operation is completed; When the detection logic processor determines that the original clock is abnormal, the chiplet for receiving data initiates a notification to the chiplet for sending data.
8. The chip integration system according to claim 3, characterized in that: The clock receiver comprises: At least two multiplexers, one of which is connected to one of the original clocks and the repaired clock respectively, and allows one of the original clocks / repaired clock to be output according to a clock selection signal output by the detection logic processor; A clock amplifier, used for amplifying one of the original clocks output by all the multiplexers and / or the repaired clocks, and outputting a corresponding received clock; The clock amplifier is further configured to operate in a differential mode or a single-ended mode according to a clock selection signal output by the detection logic processor.
9. The chip integration system according to claim 8, characterized in that: When the clock selection signal output by the detection logic processor causes all multiplexers to output the repair clock, the clock amplifier switches to a single-ended mode.
10. The chip integration system according to claim 1, characterized in that: The clock detection signal generator comprises: At least one clock amplifier, the clock amplifier is used to access the original clock input by the core grain and amplify it; A reference level generator, used for providing a reference potential for the clock amplifier; At least one sampling circuit is arranged in one-to-one correspondence with the clock amplifier, the sampling circuit samples the amplified original clock according to the sampling clock of the first phase and the sampling clock of the second phase, and outputs the corresponding first clock detection signal and the second clock detection signal; A phase shift circuit, used for accessing the sampling clock provided by the chiplet and adjusting the initial phase of the sampling clock under the control of the detection logic processor to output a sampling clock of a first phase and a sampling clock of a second phase; A multiplexer, used for accessing the sampling clock of the first phase and the sampling clock of the second phase output by the phase shift circuit, and outputting them to the sampling circuit in sequence; The sampling clock provided by the detection logic processor comes from a functional module inside the chip.