Microcontroller, safety system and protection method
By designing secure and non-secure areas in the microcontroller, and using key management devices and decryption circuits to protect data, the problem of data being easily stolen after being stored in memory in the prior art is solved, and higher data security is achieved.
Patent Information
- Application Number
- CN202410473074.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-22
- Filing Date
- 2024-04-19
- Publication Date
- 2025-02-25
AI Technical Summary
The prior art is difficult to effectively protect data from illegal theft and interception, especially after data is stored in memory.
A microcontroller is designed, including a secure area and a non-secure area. The secure area is equipped with a key management device, a decryption circuit and a memory to store and decrypt the encryption model to ensure that data cannot be illegally obtained outside the non-secure area.
By setting up a security zone in the microcontroller, the key and decryption model can be effectively protected, prevent data from being stolen, and improve data security.
Smart Images
Figure CN119513831A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a microcontroller, in particular to a microcontroller with high security. Background Art
[0002] As technology develops, data security issues are also increasing. Data may be intercepted by illegal users before being stored in memory. Even if stored in memory, it may still be stolen by illegal users. Summary of the invention
[0003] An embodiment of the present invention provides a microcontroller, including a secure area, a non-secure area, and a processing circuit. The secure area includes a key management device, a decryption circuit, and a first memory. The key management device stores a secure key. The decryption circuit uses the key to decrypt an encryption model to generate a decryption model. The first memory stores the decryption model. The non-secure area includes a second memory and a third memory. The second memory stores the encryption model. The third memory stores an inference result. The processing circuit provides an input data to the decryption model. The decryption model generates an inference result based on the input data.
[0004] The present invention further provides a security system, including a microcontroller and an offline tool. The microcontroller includes a secure area, a non-secure area and a processing circuit. The secure area includes a key management device, a decryption circuit and a first memory. The key management device stores a key. The decryption circuit uses the key to decrypt an encryption model to generate a decryption model. The first memory stores the decryption model. The non-secure area includes a second memory and a third memory. The second memory stores the encryption model. The third memory stores an inference result. The processing circuit provides an input data to the decryption model. The decryption model generates an inference result based on the input data. The processing circuit stores the inference result in the third memory. The offline tool includes an encryption circuit. The encryption circuit encrypts a network model with a key to generate an encryption model, and stores the encryption model in the second memory.
[0005] The present invention further provides a protection method, which is applicable to a processing circuit and includes: in a non-secure mode: reading an encryption model of a non-secure area; calling a software function of a secure area; switching to a secure mode. In the secure mode: executing the software function to read a key of the secure area; using the key to decrypt the encryption model to generate a decryption model; and running the decryption model to obtain an inference result.
[0006] The protection method of the present invention can be implemented through the microcontroller and processing circuit of the present invention, which are hardware or firmware that can perform specific functions, or can be recorded in a recording medium in the form of a program and implemented in combination with specific hardware. When the program is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a microcontroller and processing circuit for implementing the present invention.
[0007] The present invention can improve data security and prevent data from being stolen. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 Schematic diagram of the safety system of the present invention.
[0009] Figure 2 Schematic diagram of a microcontroller of the present invention.
[0010] Figure 3 It is a schematic diagram of the protection method of the present invention.
[0011] Description of Figure Numbers:
[0012] 100: Security System
[0013] 110: Offline Tools
[0014] 111: Encryption Circuit
[0015] 112: Injection Circuit
[0016] 120: Microcontroller
[0017] 121: Unsafe Zone
[0018] 122: Bus
[0019] 123: Safe Zone
[0020] SK: Key
[0021] PM: Network Model
[0022] CM: Encrypted Model
[0023] 211: Transmission interface
[0024] 212, 213, 223: Memory
[0025] IFR: Inference Results
[0026] 221: Key management device
[0027] 222: Decryption Circuit
[0028] 224: Neural Network Computing Accelerator
[0029] 225: Processing circuit
[0030] DM: Decryption Model
[0031] S311~S317: Steps DETAILED DESCRIPTION
[0032] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the following embodiments are specifically cited and described in detail with the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the embodiments are for the purpose of simplifying the description and do not mean the correlation between different embodiments.
[0033] Figure 1 FIG. 1 is a schematic diagram of the safety system of the present invention. Figure 1 As shown, the security system 100 includes an offline tool 110 and a microcontroller 120. The offline tool 110 includes an encryption circuit 111 and an injection circuit 112. The encryption circuit 111 performs an encryption operation on a network model PM with a key SK to generate an encryption model CM. In one possible embodiment, the encryption operation performed by the encryption circuit 111 is a symmetric encryption operation (symmetric encryption), such as the AES algorithm. The present invention does not limit the architecture of the encryption circuit 111. Any circuit with encryption function can be used as the encryption circuit 111. In some embodiments, the network model PM is a type of neural network model (artificial neural network model). In one possible embodiment, the file name extension (Filename Extension) of the network model PM is .tflite. In other embodiments, the file name extension of the encryption model CM is .encrypt.
[0034] The injection circuit 112 uses a secure key provision process to inject the key SK into the secure area 123 of the microcontroller 120. The present invention does not limit the architecture of the injection circuit 112. Any circuit that can securely transmit the key SK can be used as the injection circuit 112. In one possible embodiment, the injection circuit 112 is independent of the offline tool 110. In another possible embodiment, the key SK is injected into the secure area 123 of the microcontroller 120 via a network interface (not shown).
[0035] In other embodiments, the encryption circuit 111 may encrypt the key SK and then provide the encrypted result to the injection circuit 112. The injection circuit 112 injects the encrypted key into the secure area 123. The present invention does not limit how the encryption circuit 111 encrypts the key SK. In one embodiment, the encryption circuit 111 encrypts the key SK using an asymmetric encryption algorithm (such as an ECC algorithm or an RSA algorithm).
[0036] In this embodiment, the offline tool 110 is independent of the microcontroller 120. When the offline tool 110 is not yet connected to the microcontroller 120, the offline tool 110 may generate the encryption model CM in advance. In this example, after the offline tool 110 is connected to the microcontroller 120, the offline tool 110 immediately provides the encryption model CM and the key SK to the microcontroller 120. After the microcontroller 120 receives the encryption model CM and the key SK, even if the offline tool 110 is no longer connected to the microcontroller 120, the microcontroller 120 can still operate normally. In a possible embodiment, the offline tool 110 transmits the encryption model CM to the microcontroller 120 through an unsecured channel (such as an Internet connection). Since the key SK is stored in the security area 123 of the microcontroller 120, even if an illegal person obtains the encryption model CM, he cannot successfully decrypt the encryption model CM.
[0037] The microcontroller 120 includes a non-secure world 121, a bus 122, and a secure world 123. In one possible embodiment, the microcontroller 120 uses the Arm Trustzone technology to plan the non-secure world 121 and the secure world 123. The non-secure world 121 stores the encryption model CM, and the secure world 123 stores the key SK. The bus 122 is coupled between the non-secure world 121 and the secure world 123 to transmit data from the non-secure world 121 to the secure world 123, or to transmit data from the secure world 123 to the non-secure world 121.
[0038] In some embodiments, the microcontroller 120 is disposed in a terminal device of an Internet of Things (IoT). Although the encryption model CM is stored in the non-secure area 121 of the microcontroller 120, the encryption model CM is protected by encryption, so the security can be improved. Even if an illegal user steals the encryption model CM of the microcontroller 120, the network model PM cannot be obtained.
[0039] Figure 21 is a schematic diagram of the microcontroller 120 of the present invention. The non-secure area 121 includes a transmission interface 211 and memories 212 and 213. The transmission interface 211 is used to receive the encryption model CM. The transmission interface 211 may store the encryption model CM in the memory 212 through the bus 122. The present invention does not limit the type of the transmission interface 211. In a possible embodiment, the transmission interface 211 is an Internet interface.
[0040] The memory 212 stores the encryption model CM. The memory 213 stores an inference result IFR. In some embodiments, the memory 212 is a non-volatile memory (NVM), such as a read-only memory (ROM). The memory 213 may be a volatile memory, such as a random access memory (RAM).
[0041] The security zone 123 includes a key management device 221, a decryption circuit 222, and a memory 223. The key management device 221 stores a key SK. The key management device 221 outputs the key SK according to a request issued by a specific circuit. For example, it is assumed that the encryption circuit 111 uses the AES algorithm to encrypt the network model PM. In this example, when a hardware device that complies with the AES algorithm (such as the decryption circuit 222) issues a request, the key management device 221 outputs the key SK to the bus 122. When the request received by the key management device 221 is not from a hardware device that complies with the AES algorithm, the key management device 221 does not output the key SK. In one possible embodiment, the key management device 221 is a keystore.
[0042] The decryption circuit 222 reads the key management device 221 to obtain the key SK, and uses the key SK to perform a decryption operation on the encryption model CM to generate a decryption model DM. In one possible embodiment, the decryption circuit 222 uses a symmetric decryption operation to process the encryption model CM. The type of decryption operation used by the decryption circuit 222 is the same as the type of encryption operation used by the encryption circuit 111. Therefore, the decryption model DM is the same as the network model PM. In addition, since the type of decryption operation used by the decryption circuit 222 (such as the AES algorithm) is the same as the type of encryption operation used by the encryption circuit 111 (such as the AES algorithm), the key management device 221 only accepts access instructions from the decryption circuit 222. In other embodiments, the key SK of the key management device 221 may be an encryption key. In this example, the decryption circuit 222 first decrypts the key SK of the key management device 221, and then uses the decrypted key to process the encryption model CM.
[0043] The present invention does not limit how the decryption circuit 222 accesses the key management device 221 and the memory 212. In one embodiment, the decryption circuit 222 accesses the key management device 221 and the memory 212 through the bus 122 to obtain the key SK and the encryption model CM. In some embodiments, the decryption circuit 222 is a crypto decryption accelerator.
[0044] The memory 223 stores the decryption model DM. In one possible embodiment, the memory 223 receives the decryption model DM generated by the decryption circuit 222 through the bus 122. The present invention does not limit the type of the memory 223. In one possible embodiment, the memory 223 is a volatile memory. Since the decryption model DM is stored in the security area 123, illegal personnel cannot steal the decryption model DM.
[0045] In other embodiments, the microcontroller 120 further includes a processing circuit 225. In one possible embodiment, the processing circuit 225 supports a secure mode and a non-secure mode of the Trustzone. When the processing circuit 225 operates in a non-secure mode, the processing circuit 225 operates in the non-secure zone 121. When the processing circuit 225 operates in a secure mode, the processing circuit 225 operates in the secure zone 123.
[0046] In non-secure mode, the processing circuit 225 reads information of the encryption model CM of the non-secure area 121, such as the memory address of the encryption model CM and the size of the encryption model CM. The processing circuit 225 calls a software function of the secure area 123. In one possible embodiment, the processing circuit 225 provides the encryption model CM, the input data of the encryption model CM, and the inference result IFR stored at the memory address of the memory 213 to a software function. In one possible embodiment, the software function is a non-secure callable secure function. For example, the software function is a trusted machine learning execution application programming interface.
[0047] Then, the processing circuit 225 switches to a safe mode. In the safe mode, the processing circuit 225 executes the software function. In the safe mode, the processing circuit 225 commands the decryption circuit 222 to access the key SK located in the key management device 221. Then, the processing circuit 225 requires the decryption circuit 222 to use the key SK to decrypt the encryption model CM. After the decryption operation, the decryption circuit 222 generates a decryption model DM. In one possible embodiment, the processing circuit 225 has a software execution environment of TensorFlow Lite and a program (TensorFlow Lite Library). The processing circuit 225 runs the TensorFlow LiteLibrary program to interpret the decryption model DM. In this example, the decryption model DM generates an inference result IFR based on the input data. The processing circuit 225 outputs the inference result IFR to the non-safe area 121. Then, the processing circuit 225 switches to the non-safe mode. In the non-safe mode, the processing circuit 225 reads the inference result IFR of the non-safe area 121. The present invention does not limit the architecture of the processing circuit 225. In one possible embodiment, the processing circuit 225 has a general-purpose processor, such as a central processing unit (CPU).
[0048] In other embodiments, the microcontroller 120 further includes a neural network operation accelerator (NN operation accelerator) 224. The neural network operation accelerator 224 is located in the secure area 123. After the decryption circuit 222 generates the decryption model DM, the neural network operation accelerator 224 may read the decryption model DM in the memory 223 through the bus 122. The neural network operation accelerator 224 provides an input data to the decryption model DM. After the decryption model DM generates the inference result IFR, the processing circuit 225 stores the inference result IFR in the non-secure area 121.
[0049] Figure 3 Schematic diagram of the protection method of the present invention. The protection method of the present invention can be implemented by a program. When the program is loaded and executed by a machine, the machine becomes a processing circuit and a microcontroller for implementing the present invention.
[0050] First, the information of the encryption model CM in the non-secure area 121 is read (step S311). In one embodiment, the processing circuit 225 reads the information of the encryption model CM in the non-secure mode, such as the address where the encryption model CM is stored in the memory 212 and the size of the encryption model CM.
[0051] Next, a software function is called (step S312). In one possible embodiment, the processing circuit 225 runs in a non-secure mode and calls a software function stored in the secure area 123. In some embodiments, the software function is a non-secure area callable secure area software function. The processing circuit 225 may provide the encryption model CM, an input data, and a memory address where the inference result is stored to the software function.
[0052] Then, the software function is executed (step S313). In one possible embodiment, the processing circuit 225 switches to the safe mode first, and then executes the software function. The function of the software function includes steps S314 to S317. In the safe mode, the processing circuit 225 operates the decryption circuit 222 to read the key SK stored in the key management device 221 (step S314). In one possible embodiment, the processing circuit 225 instructs the decryption circuit 222 to access the key management device 221 through the bus 122. In this example, the decryption circuit 222 reads the key SK of the key management device 221 through the bus 122.
[0053] In the security mode, the processing circuit 225 requires the decryption circuit 222 to use the key SK to decrypt the encrypted model CM to generate the decrypted model DM (step S315 ). In one embodiment, the processing circuit 225 stores the decrypted model DM in the secure area 123 .
[0054] In the security mode, the processing circuit 225 interprets the decryption model DM to generate an inference result (step S316). In one possible embodiment, the processing circuit 225 may provide an input data to the decryption model DM. The decryption model DM processes the input data to generate an inference result IFR. In other examples, the processing circuit 225 runs the TensorFlow LiteLibrary program to interpret the decryption model DM so that the decryption model DM performs an inference operation.
[0055] In the secure mode, the processing circuit 225 outputs the inference result IFR generated by the decryption model DM to the memory 213 of the non-secure area 121 (step S317 ). In one embodiment, the processing circuit 225 stores the inference result IFR to the non-secure area 121 via the bus 122 .
[0056] Then, the processing circuit 225 switches to the non-secure mode (step S318). In the non-secure mode, the processing circuit 225 reads the inference result IFR of the non-secure area 121. In one possible embodiment, the processing circuit 225 operates in the non-secure mode when executing steps S311, S312 and S318. In this example, the processing circuit 225 operates in the secure mode when executing steps S313 to S317.
[0057] Since the security zone 123 of the microcontroller 120 provides a trusted operation environment, the security of the key SK can be improved. Furthermore, by encrypting the network model PM, the confidentiality of the network model PM is improved and can be prevented from being stolen. In addition, when the microcontroller 120 is applied to an IoT terminal device, since the microcontroller 120 uses the security zone 123 to protect the key SK, it can prevent illegal users outside the security zone from obtaining the key SK.
[0058] The protection method of the present invention, or a specific form or part thereof, may exist in the form of program code. The program may be stored in a physical medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product not limited to an external form, wherein when the program code is loaded and executed by a machine, such as a computer, the machine becomes a processing circuit and microcontroller for participating in the present invention. The program code may also be transmitted through some transmission media, such as wires or cables, optical fibers, or any transmission mode, wherein when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes a processing circuit and microcontroller for participating in the present invention. When implemented in a general-purpose processing unit, the program code combines with the processing unit to provide a unique device that operates similarly to an application-specific logic circuit.
[0059] Unless otherwise defined, all terms (including technical and scientific terms) herein are generally understood by those skilled in the art to which the present invention belongs. In addition, unless expressly indicated, the definitions of terms in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant technical field, and should not be interpreted as ideal or overly formal. Although the terms "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.
[0060] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be subject to the claims.
Claims
1. A microcontroller, characterized in that: include: A safety zone, including: a key management device storing a key; a decryption circuit, using the key to decrypt an encrypted model to generate a decrypted model; a first memory storing the decryption model; 1. Non-safety areas, including: a second memory for storing the encryption model; a third memory for storing an inference result; A processing circuit provides an input data to the decryption model, and the decryption model generates the inference result according to the input data.
2. The microcontroller according to claim 1, wherein: In a non-secure mode, the processing circuit reads the encryption model stored in the second memory and calls a software function.
3. The microcontroller according to claim 2, characterized in that The software function is stored in the secure area.
4. The microcontroller according to claim 3, characterized in that The processing circuit provides the encryption model, an input data and the address where the inference result is stored to the software function.
5. The microcontroller according to claim 4, characterized in that The processing circuit enters a safe mode and executes the software function.
6. The microcontroller according to claim 5, characterized in that In the safe mode, the processing circuit executes the software function to perform the following steps: commanding the decryption circuit to read the key stored in the key management device; commanding the decryption circuit to decrypt the encrypted model using the key to generate the decrypted model; as well as The decryption model is stored in the first memory.
7. A security system, characterized in that: include: A microcontroller, comprising: A safety zone, including: a key management device storing a key; a decryption circuit, using the key to decrypt an encrypted model to generate a decrypted model; a first memory storing the decryption model; 1. Non-safety areas, including: a second memory for storing the encryption model; a third memory storing an inference result; a processing circuit, providing an input data to the decryption model, the decryption model generates the inference result according to the input data, and the processing circuit stores the inference result in the third memory; and An offline tool, including: An encryption circuit encrypts a network model using the key to generate the encrypted model, and stores the encrypted model in the second memory.
8. The security system according to claim 7, characterized in that The offline tool also includes: An injection circuit injects the key into the key management device.
9. A protection method, characterized in that: Suitable for a processing circuit, and comprising: In a non-secure mode: Reading an encrypted model of a non-secure area; Calling a software function in a security zone; Switching to a safe mode; and In this safe mode: Execute the software function to perform the following steps: Reading a key of the security zone; decrypting the encrypted model using the key to generate a decrypted model; and The decryption model is run to obtain an inference result.
10. The protection method according to claim 9, characterized in that: Also includes: In the secure mode, storing the inference result in the non-secure area; and In the non-secure mode, the inference result of the non-secure area is read.