Method and device for adjusting impedance of signal line in integrated circuit layout

Abstract

The invention discloses a method for adjusting impedance of a signal line in an integrated circuit layout, aiming at the problem of large error caused by roughly calculating the impedance of the signal line by manually measuring the length and the width in the prior art, after the integrated circuit layout is preliminarily completed, generating a GDSII file of the signal line according to the name of the signal line in the circuit diagram; obtaining coordinate information of all metal wires and through holes in the signal wires from a GDSII file, and calculating a total impedance value of the signal wires by combining unit impedance of each layer of metal wires and through holes; comparing the total impedance value of the signal line with a preset maximum impedance value, and if the total impedance value does not exceed the maximum impedance value, determining that the integrated circuit layout meets the requirement; and if the total impedance value is greater than the maximum impedance value, modifying the integrated circuit layout, and recalculating the impedance of the signal line. Therefore, the accuracy of impedance calculation of the signal line is improved, and the working efficiency of integrated circuit layout design is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and in particular relates to a method and device for adjusting the impedance of a signal line in an integrated circuit layout. Background Art

[0002] In the chip design process, there is a problem of excessive signal impedance value, which has no effect in design and production, but in the use of the chip, excessive signal impedance value will cause signal attenuation, thereby reducing the quality of signal transmission, affecting the stability of the circuit system and the performance of the entire chip. Therefore, in order to ensure the normal function of the chip during the chip design process, circuit engineers will put forward impedance requirements for certain signals, especially important analog signals.

[0003] In the prior art, after the integrated circuit layout is completed, the impedance extraction and analysis of the module-level and chiplet-level signals can be performed through the integrated circuit post-simulation software. However, as the chip area becomes larger and the integration becomes higher, the integrated circuit post-simulation software is no longer able to simulate and analyze the chip-level signal lines. It can only be roughly calculated by manually measuring the length and width of the signal line and based on the unit impedance of the metal line. The impedance calculation formula of the metal line is: R=Rs(L / W), where L is the length of the metal line, W is the width of the metal line, and Rs is the unit impedance of the metal line.

[0004] Disadvantages of manual measurement and calculation: Manual measurements are inherently prone to all kinds of uncertainties; As chip area increases, metal layers increase, and routing becomes more complex and diverse, manual measurement becomes increasingly difficult, and the errors generated by manual measurement also become larger. Summary of the invention

[0005] The purpose of the present invention is to provide a method for adjusting the impedance of a signal line in an integrated circuit layout, which can intuitively and accurately view the impedance value of the entire signal line.

[0006] To solve the above problems, the technical solution of the present invention is: A method for adjusting the impedance of a signal line in an integrated circuit layout, comprising: After the integrated circuit layout is initially completed, the GDSII file of the signal line is generated according to the name of the signal line in the circuit diagram; Obtain the coordinate information of all metal lines and through holes in the signal line from the GDSII file, determine the series and parallel relationship of all metal lines, and the length and width of the metal lines according to the coordinate information of the metal lines; calculate the total impedance value of the signal line by combining the unit impedance of the metal lines of each layer; Compare the total impedance value of the signal line with the preset maximum impedance value. If the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements; if the total impedance value is greater than the maximum impedance value, modify the integrated circuit layout and recalculate the signal line impedance.

[0007] According to an embodiment of the present invention, the impedance value of the metal line is calculated according to the formula R=Rs(L / W), where L is the length of the metal line, W is the width of the metal line, and Rs is the unit impedance of the metal line.

[0008] According to an embodiment of the present invention, determining the series-parallel relationship of all metal wires and the length and width of the metal wires according to the coordinate information of the metal wires further includes: Use SKILL or TCL language to divide the metal wire into several line segments with preset distances, and use LENGTH and WIDTH to obtain the length and width of each line segment; Determine whether two line segments have a common starting point and a common end point. If so, the two line segments are parallel; Determine whether two line segments are connected end to end. If so, the two line segments are connected in series.

[0009] According to an embodiment of the present invention, the impedance of the series line segment is calculated by the following formula: R=Rs1*(L1 / W1)+Rs2*(L2 / W2)+Rs3*(L3 / W3)+…+Rsn*(Ln / Wn) Among them, the lengths of the n line segments are L1, L2, L3...Ln, and the widths are W1, W2, W3...Wn, respectively. The unit impedance of the metal wires of the n line segments is Rs1, Rs2, Rs3,...Rsn.

[0010] According to an embodiment of the present invention, the impedance of the parallel line segment is calculated by the following formula: R = (R1*R2*R3*…*Rn) / (R1+R2+R3+…+Rn) Where, R1=Rs1*(L1 / W1) R2=Rs2*(L2 / W2) Rn=Rsn*(Ln / Wn) The lengths of the n line segments are L1, L2, L3...Ln, and the widths are W1, W2, W3...Wn, respectively. The unit impedance of the metal wires of the n line segments is Rs1, Rs2, Rs3,...Rsn.

[0011] According to an embodiment of the present invention, the preset distance does not exceed the minimum grid point of the integrated circuit layout design software to ensure that the metal line is divided into integer parts.

[0012] According to one embodiment of the present invention, when modifying the integrated circuit layout, according to the calculation formula of the metal line impedance: R = Rs*(L / W), where Rs is the unit impedance of the metal line, L is the length of the metal line, and W is the width of the metal line, the unit impedance Rs of the metal line is reduced, or the length L of the metal line is reduced, or the width W of the metal line is increased.

[0013] According to an embodiment of the present invention, when reducing the unit impedance of the metal line to reduce the total impedance value of the signal line, the metal line with the minimum unit impedance is selected, and other metal lines are adjusted to the metal line with the minimum unit impedance.

[0014] According to an embodiment of the present invention, when increasing the width of the metal line to reduce the total impedance of the signal line, a metal layer is superimposed on the basis of the current metal line while ensuring that the metal line has no short circuit and meets the layout design rules.

[0015] A device for adjusting the impedance of a signal line in an integrated circuit layout, comprising: The signal line extraction module is configured to generate a GDSII file of the signal line according to the name of the signal line in the circuit diagram after the integrated circuit layout is preliminarily completed; The impedance calculation module is configured to obtain the coordinate information of all metal lines and through holes in the signal line from the GDSII file, determine the series and parallel relationship of all metal lines and the length and width of the metal lines according to the coordinate information of the metal lines, and calculate the total impedance value of the signal line in combination with the unit impedance of the metal lines of each layer; The impedance correction module is configured to compare the total impedance value of the signal line with a preset maximum impedance value. If the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements; if the total impedance value is greater than the maximum impedance value, the integrated circuit layout is modified and the signal line impedance is recalculated.

[0016] According to an embodiment of the present invention, the impedance calculation module includes a data processing unit and a calculation unit; The data processing unit is configured to divide the metal wire into a number of line segments of preset distances through SKILL or TCL language, and obtain the length and width of each line segment through LENGTH and WIDTH; determine whether two line segments have a common starting point and a common end point, if so, the two line segments are in parallel; determine whether the two line segments are connected end to end, if so, the two line segments are in series; The calculation unit calculates the impedance value of the metal line according to the formula R=Rs(L / W), where L is the length of the metal line, W is the width of the metal line, and Rs is the unit impedance of the metal line.

[0017] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: In an embodiment of the present invention, a method for adjusting the impedance of a signal line in an integrated circuit layout aims at the problem that the impedance of an existing signal line is roughly calculated by manually measuring the length and width, and the error is large. After the integrated circuit layout is initially completed, a GDSII file of the signal line is generated according to the name of the signal line in the circuit diagram; the coordinate information of all metal lines and through holes in the signal line is obtained from the GDSII file, and the total impedance value of the signal line is calculated in combination with the unit impedance of each layer of metal lines and through holes; the total impedance value of the signal line is compared with the preset maximum impedance value. If the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements; if the total impedance value is greater than the maximum impedance value, the integrated circuit layout is modified and the signal line impedance is recalculated. This improves the accuracy of the impedance calculation of the signal line, and further improves the work efficiency of the integrated circuit layout design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A flow chart of a method for adjusting impedance of a signal line in an integrated circuit layout in one embodiment of the present invention; Figure 2 is a schematic diagram of a signal line in one embodiment of the present invention; Figure 3 is an equivalent schematic diagram of a signal line in one embodiment of the present invention; Figure 4 This is a schematic diagram of the first modification of the signal line in one embodiment of the present invention; Figure 5 This is a schematic diagram of a second modification of a signal line in an embodiment of the present invention; Figure 6 FIG. 4 is a block diagram of a device for adjusting the impedance of a signal line in an integrated circuit layout according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following is a further detailed description of a signal line impedance adjustment method and device in an integrated circuit layout proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims.

[0020] Please see Figure 1 This embodiment provides a method for adjusting the impedance of a signal line in an integrated circuit layout, the method comprising the following steps: After the integrated circuit layout is initially completed, the GDSII file of the signal line is generated according to the name of the signal line in the circuit diagram; Obtain the coordinate information of all metal lines and through-holes in the signal line from the GDSII file, and calculate the total impedance value of the signal line by combining the unit impedance of the metal lines and through-holes of each layer; Compare the total impedance value of the signal line with the preset maximum impedance value. If the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements; if the total impedance value is greater than the maximum impedance value, modify the integrated circuit layout and recalculate the signal line impedance.

[0021] Specifically, when designing the integrated circuit layout, it can be achieved through layout design software such as Virtuoso, ICC, Encounter, etc. The devices and signal lines correspond one-to-one on the circuit diagram and the layout. Therefore, it is possible to find the corresponding metal wires and through holes in the layout according to the names of the signal lines in the circuit diagram.

[0022] Extract the GDSII file containing all metal lines and vias in the signal line. You can use the export function in the virtuoso software to extract the GDSII file corresponding to the layout. The GDSII file is a binary file that contains the coordinate information of all layers corresponding to the graphics in the integrated circuit layout.

[0023] Get the coordinate information of all vias and all metal lines in the entire GDSII file. Usually, two metal layers on a circuit board need to be connected by through holes. If the same signal line is composed of different metal layers, it is believed that filling the through holes will not increase the impedance of the signal line. On the contrary, it is believed that the impedance of the metal line will increase. Therefore, when calculating the impedance of the signal line, in addition to obtaining the coordinate information of all metal lines, it is also necessary to obtain the coordinate information of all through holes.

[0024] Determine the length and width of the metal line according to the coordinate information of the metal line, and determine the series and parallel relationship of the metal line according to the coordinate information of the through hole. According to the unit impedance information of different metal lines in the foundry factory and the maximum impedance value A required by the circuit engineer, the impedance value of the signal line is calculated by the formula R=Rs(L / W), and the total resistance value B of all metal lines is output. Among them, L is the length of the metal line, W is the width of the metal line, and Rs is the unit impedance of the metal line. Compare A and B. If A is greater than or equal to B, the signal line design is fine. If A is less than B, the layout needs to be modified. After the layout modification is completed, repeat the above operation until the signal line impedance meets the requirements.

[0025] The following is an example of an embodiment to illustrate the method for adjusting the impedance of the signal line in the integrated circuit layout.

[0026] Please see Figure 2 The signal line in the figure is composed of five layers of metal wires. The unit impedance of the first layer of metal wires (M1) is 0.18Ω, the unit impedance of the second to fourth layers of metal wires (M2~M4) is 0.16Ω, and the unit impedance of the fifth layer of metal wires (M5) is 0.022Ω. Circuit engineers require that the entire connection impedance of the signal be less than 0.5Ω.

[0027] First, you need to calculate the impedance R1 of the second layer of metal (M2) between points AB, the impedance R2 of the first layer of metal (M1) between points BC, the impedance R3 of the third layer of metal (M3) between points CD, the impedance R4 of the fifth layer of metal (M5) between points DE, the impedance R5 of the fourth layer of metal (M4) between points EF, the impedance R6 of the second layer of metal (M2) between points BF, and the impedance R7 of the second layer of metal (M2) between points FG.

[0028] According to the calculation formula of metal line impedance series and parallel: The lengths of the n line segments are L1, L2, L3, ... Ln, and the widths are W1, W2, W3, ... Wn. The unit impedance of the metal wires of the n line segments is Rs1, Rs2, Rs3, ... Rsn. Series connection: R=Rs1*(L1 / W1)+Rs2*(L2 / W2)+Rs3*(L3 / W3)+…+Rsn*(Ln / Wn) Parallel connection: R1=Rs1*(L1 / W1) R2=Rs2*(L2 / W2) Rn=Rsn*(Ln / Wn) R = (R1*R2*R3*…*Rn) / (R1+R2+R3+…+Rn) It can be concluded that the connection impedance of the entire signal line is: R = R1+ R7+(R2+R3+R4+R5)* R6 / (R2+R3+R4+R5+R6) It can be seen from the above calculation formula that manual measurement and calculation are very difficult, and the errors caused by manual measurement and calculation are very large.

[0029] In order to avoid the above problems, this embodiment uses languages ​​such as SKILL or TCL to divide the metal wires into small metal wires according to the minimum grid point (GRID) of the project, so as to ensure that the number of parts of the entire metal wire is an integer. The minimum grid point (GRID) of this project is 0.1, so the metal wire of the signal is divided into metal wires with a length of 0.1 micron, and each metal wire is equivalent to a small resistor. Please refer to Figure 3 , because there are too many segmented segments, Figure 3 Just a simple gesture.

[0030] Then, according to the detection rule that resistors with the same starting point and end point are in parallel, and those connected end to end are in series, the series-parallel relationship of the resistors is judged, and then the total resistance, that is, impedance R, is calculated according to the series-parallel formula. Among them, when calculating the resistance of a resistor, its length and width can be obtained through the LENGTH and WIDTH functions.

[0031] According to the above method, the total impedance R of the signal line is 1.2Ω, which is greater than the required 0.5Ω. Therefore, the line design does not meet the requirements and the layout needs to be modified. According to the calculation formula of metal line impedance: R = Rs*(L / W), where Rs is the unit impedance of the metal line, L is the length of the metal line, and W is the width of the metal line, it can be seen that there are three ways to reduce the impedance: 1. Reduce the unit impedance Rs of the metal wire. If conditions permit, replace it with a metal with a smaller unit impedance; 2. Reduce the length L of the metal wire; 3. Increase the width W of the metal wire.

[0032] Which of these three methods to use or the combination of the three methods should be analyzed and used according to the actual situation of the project.

[0033] In this embodiment, the fifth metal layer (M5) is the highest metal layer and has the smallest unit impedance. The metal lines should be replaced with the fifth metal layer (M5) as much as possible. When ensuring that the metal lines are not short-circuited and meet the layout design rules, replace the metal lines of other layers with the fifth metal layer (M5). Please refer to Figure 4 .

[0034] The impedance value R is calculated again using languages ​​such as SKILL or TCL, and is 0.6Ω, which is still greater than the required 0.5Ω. The layout needs to be modified further. Due to the influence of the underlying devices, the length of the metal line cannot be shortened. This time, we tried the third solution, which is to superimpose a metal layer on the original metal line while ensuring that the metal line is not short-circuited and meets the layout design rules.

[0035] Please see Figure 5 , stack the fourth metal layer on the fifth metal layer, and stack the third metal layer on the second metal layer. Recalculate the impedance value R as 0.43Ω using languages ​​such as SKILL or TCL. This time, by increasing the width of the metal line, the layout design meets the impedance requirements.

[0036] Through the above method, the impedance value of the entire signal line can be viewed intuitively and accurately, greatly improving the calculation accuracy and efficiency of the signal line impedance.

[0037] Based on the same concept, this embodiment also provides a device for adjusting the impedance of a signal line in an integrated circuit layout, which implements the above-mentioned method for adjusting the impedance of a signal line in an integrated circuit layout. Figure 6 , the device comprises: The signal line extraction module 1 is configured to generate a GDSII file of the signal line according to the name of the signal line in the circuit diagram after the integrated circuit layout is preliminarily completed; The impedance calculation module 2 is configured to obtain the coordinate information of all metal lines and through holes in the signal line from the GDSII file, determine the series-parallel relationship of all metal lines and the length and width of the metal lines according to the coordinate information of the metal lines, and calculate the total impedance value of the signal line in combination with the unit impedance of the metal lines of each layer; The impedance correction module 3 is configured to compare the total impedance value of the signal line with the preset maximum impedance value. If the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements; if the total impedance value is greater than the maximum impedance value, the integrated circuit layout is modified and the signal line impedance is recalculated.

[0038] The impedance calculation module 2 includes a data processing unit and a calculation unit; wherein the data processing unit is configured to divide the metal line into several line segments of preset distances through SKILL or TCL language, obtain the length and width of each line segment through LENGTH and WIDTH; determine whether two line segments have a common starting point and a common end point, if so, the two line segments are in parallel; determine whether the two line segments are connected end to end, if so, the two line segments are in series. The preset distance does not exceed the minimum grid point of the integrated circuit layout design software to ensure that the metal line is divided into integer parts.

[0039] The calculation unit calculates the impedance value of the metal line according to the formula R=Rs(L / W), where L is the length of the metal line, W is the width of the metal line, and Rs is the unit impedance of the metal line. Specifically, the calculation unit calculates the impedance of the series line segment by the following formula: R=Rs1*(L1 / W1)+Rs2*(L2 / W2)+Rs3*(L3 / W3)+…+Rsn*(Ln / Wn) The impedance of the parallel line segments is calculated using the following formula: R = (R1*R2*R3*…*Rn) / (R1+R2+R3+…+Rn) Where, R1=Rs1*(L1 / W1) R2=Rs2*(L2 / W2) Rn=Rsn*(Ln / Wn) The lengths of the n line segments are L1, L2, L3...Ln, and the widths are W1, W2, W3...Wn, respectively. The unit impedance of the metal wires of the n line segments is Rs1, Rs2, Rs3,...Rsn.

[0040] The device is used to implement the above-mentioned method for adjusting the impedance of the signal line in the integrated circuit layout. The implementation method thereof is similar and will not be described in detail here.

[0041] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the protection scope of the present invention.

Claims

1. A method for adjusting the impedance of a signal line in an integrated circuit layout, characterized in that: include: After the integrated circuit layout is initially completed, the GDSII file of the signal line is generated according to the name of the signal line in the circuit diagram; Obtain the coordinate information of all metal lines and through holes in the signal line from the GDSII file, determine the series and parallel relationship of all metal lines, and the length and width of the metal lines according to the coordinate information of the metal lines; calculate the total impedance value of the signal line by combining the unit impedance of the metal lines of each layer; Compare the total impedance value of the signal line with the preset maximum impedance value. If the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements; if the total impedance value is greater than the maximum impedance value, modify the integrated circuit layout and recalculate the signal line impedance.

2. The method for adjusting the impedance of a signal line in an integrated circuit layout according to claim 1, wherein: The impedance value of the metal line is calculated according to the formula R=Rs(L / W), where L is the length of the metal line, W is the width of the metal line, and Rs is the unit impedance of the metal line.

3. The method for adjusting the impedance of a signal line in an integrated circuit layout according to claim 1, wherein: Determining the series-parallel relationship of all metal wires and the length and width of the metal wires according to the coordinate information of the metal wires further includes: Use SKILL or TCL language to divide the metal wire into several line segments with preset distances, and use LENGTH and WIDTH to obtain the length and width of each line segment; Determine whether two line segments have a common starting point and a common end point. If so, the two line segments are parallel; Determine whether two line segments are connected end to end. If so, the two line segments are connected in series.

4. The method for adjusting the impedance of a signal line in an integrated circuit layout according to claim 3, wherein: The impedance of the series line segment is calculated using the following formula: R=Rs1*(L1 / W1)+Rs2*(L2 / W2)+Rs3*(L3 / W3)+…+Rsn*(Ln / Wn) Among them, the lengths of the n line segments are L1, L2, L3...Ln, and the widths are W1, W2, W3...Wn, respectively. The unit impedances of the metal lines of the n line segments are Rs1, Rs2, Rs3, and Rsn.

5. The method for adjusting the impedance of a signal line in an integrated circuit layout as claimed in claim 3, wherein: The impedance of the parallel line segments is calculated using the following formula: R = (R1*R2*R3*…*Rn) / (R1+R2+R3+…+Rn) Where, R1=Rs1*(L1 / W1) R2=Rs2*(L2 / W2) Rn=Rsn*(Ln / Wn) The lengths of the n line segments are L1, L2, L3...Ln, and the widths are W1, W2, W3...Wn, respectively. The unit impedance of the metal wires of the n line segments is Rs1, Rs2, Rs3,...Rsn.

6. The method for adjusting the impedance of a signal line in an integrated circuit layout as claimed in claim 3, wherein: The preset distance does not exceed the minimum grid point of the integrated circuit layout design software to ensure that the metal line is divided into integer parts.

7. The method for adjusting the impedance of a signal line in an integrated circuit layout according to claim 1, wherein: When modifying the integrated circuit layout, according to the calculation formula of the metal line impedance: R = Rs*(L / W), where Rs is the unit impedance of the metal line, L is the length of the metal line, and W is the width of the metal line, the unit impedance Rs of the metal line can be reduced, or the length L of the metal line can be reduced, or the width W of the metal line can be increased.

8. The method for adjusting the impedance of a signal line in an integrated circuit layout as claimed in claim 7, wherein: When reducing the unit impedance of the metal wire to reduce the total impedance value of the signal wire, the metal wire with the minimum unit impedance is selected, and the other metal wires are adjusted to the metal wire with the minimum unit impedance.

9. The method for adjusting the impedance of a signal line in an integrated circuit layout according to claim 7, wherein: When increasing the width of the metal line to reduce the total impedance of the signal line, a metal layer is superimposed on the basis of the current metal line while ensuring that the metal line is not short-circuited and meets the layout design rules.

10. A device for adjusting the impedance of a signal line in an integrated circuit layout, characterized in that: include: The signal line extraction module is configured to generate a GDSII file of the signal line according to the name of the signal line in the circuit diagram after the integrated circuit layout is preliminarily completed; The impedance calculation module is configured to obtain the coordinate information of all metal lines and through holes in the signal line from the GDSII file, determine the series and parallel relationship of all metal lines and the length and width of the metal lines according to the coordinate information of the metal lines, and calculate the total impedance value of the signal line in combination with the unit impedance of the metal lines of each layer; The impedance correction module is configured to compare the total impedance value of the signal line with a preset maximum impedance value. If the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements; If the total impedance value is greater than the maximum impedance value, modify the integrated circuit layout and recalculate the signal line impedance.

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