Backboard indicator light control method and device, product and medium

Abstract

The invention discloses a backboard indicator light control method and device, a product and a medium, and relates to the technical field of computers, and the method comprises the steps: determining that a first connector of a mainboard controller is connected with a second connector of a backboard controller; selecting a pin at the side band part of the first connector; the unibus signal is transmitted to a backboard controller through the selected pin, so that the backboard controller controls a corresponding backboard indicating lamp according to the unibus signal, and the unibus signal at least comprises a CPU number, a virtual pin address and an indicating lamp control signal. Compared with the prior art, the single-bus signal transmission mode is adopted, the single-bus signal containing various information such as the CPU serial number, the virtual pin address and the indicator light control signal is transmitted from the mainboard controller to the backboard controller through one pin, and therefore the number of the pins is reduced, and the wiring complexity is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, product and medium for controlling a backplane indicator light. Background Art

[0002] In the current server market, servers, as core equipment in data centers, have extremely high requirements for maintainability, stability, and status indication. In order to meet these requirements, the backplane end used to plug in the Non-Volatile Memory Express (NVME) solid state drive (SSD) usually needs to display the working status of the NVME solid state drive on the corresponding interface through an LED indicator, so that operation and maintenance personnel can quickly understand the working status and fault conditions of the hard drive.

[0003] When controlling the backplane LED indicator display, the mainboard CPU end is mainly connected to the complex programmable logic device (CPLD) chip on the backplane through a two-wire virtual pin (Virtual Pin Port, VPP) bus. The CPLD chip on the backplane receives the indicator light information sent by the mainboard CPU, and controls the lighting of the corresponding indicator according to the indicator light information.

[0004] In a multi-CPU application environment, since the VPP addresses of different CPUs may be the same, additional pins need to be added to distinguish different CPUs. The CPLD chip on the backplane can determine the VPP address and CPU number of the CPU by reading the pin status, and can correctly identify which CPU sends the indicator light information based on the VPP address and CPU number, and control the lighting of the corresponding indicator according to the indicator light information. However, as the number of CPUs increases, the existing method requires more pins to distinguish different CPUs, resulting in excessive pin occupancy and increased wiring complexity. Summary of the invention

[0005] In view of this, the present application provides a control method, device, product and medium for a backplane indicator light, the main purpose of which is to solve the technical problem that additional pins need to be added to distinguish different CPUs. As the number of CPUs increases, the pins will be occupied too much, increasing the complexity of wiring.

[0006] According to a first aspect of the present application, a method for controlling a backplane indicator light is provided, which is executed by a mainboard controller, and includes: Determine that the first connector of the mainboard controller is connected to the second connector of the backplane controller; selecting a pin on a side band portion of the first connector; The single bus signal is transmitted to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes a CPU number, a virtual pin address and an indicator light control signal.

[0007] According to a second aspect of the present application, a method for controlling a backplane indicator light is provided, which is executed by a backplane controller, and includes: Receiving a single bus signal sent by a mainboard controller through a pin, wherein the single bus signal includes at least a CPU number, a virtual pin address and an indicator light control signal; The corresponding backplane indicator light is controlled according to the single bus signal.

[0008] According to a third aspect of the present application, a control device for a backplane indicator light is provided, which is applied to a mainboard controller end and includes: A first determining module, used for determining that a first connector of a mainboard controller is connected to a second connector of a backplane controller; A selection module, used for selecting a pin on the side band portion of the first connector; A transmission module is used to transmit a single bus signal to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes a CPU number, a virtual pin address and an indicator light control signal.

[0009] According to a fourth aspect of the present application, a control device for a backplane indicator light is provided, which is applied to a backplane controller, and includes: A second receiving module, used for receiving a single bus signal sent by a mainboard controller through a pin, wherein the single bus signal at least includes a CPU number, a virtual pin address and an indicator light control signal; The control module is used to control the corresponding backplane indicator light according to the single bus signal.

[0010] According to the fifth aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the control method of the backplane indicator light described in the first aspect, or when executed, it implements the control method of the backplane indicator light described in the second aspect.

[0011] According to the sixth aspect of the present application, an electronic device is provided, comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein when the processor executes the computer program, the method for controlling the backplane indicator light described in the first aspect is implemented, or the method for controlling the backplane indicator light described in the second aspect is implemented.

[0012] According to the seventh aspect of the present application, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the method for controlling the backplane indicator light described in the first aspect, or implements the method for controlling the backplane indicator light described in the second aspect.

[0013] By means of the above technical solution, the present application provides a method, device, product and medium for controlling a backplane indicator light, which can determine that the first connector of the mainboard controller is connected to the second connector of the backplane controller; select a pin in the side band portion of the first connector; transmit a single bus signal to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes the CPU number, the virtual pin address and the indicator light control signal. Compared with the current prior art, the present application adopts a single bus signal transmission method, and transmits a single bus signal containing multiple information such as the CPU number, the virtual pin address and the indicator light control signal from the mainboard controller to the backplane controller through one pin, thereby reducing the number of pins and reducing the complexity of wiring.

[0014] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. Figure 1 A schematic diagram of a flow chart of a method for controlling a back panel indicator light provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of a single bus design provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of a flow chart of a method for controlling a back panel indicator light provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of a single bus code stream provided in an embodiment of the present disclosure; Figure 5 A schematic diagram of an 8-bit lighting information register provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of a flow chart of a method for controlling a back panel indicator light provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of a flow chart of a method for controlling a back panel indicator light provided in an embodiment of the present disclosure; Figure 8A schematic diagram of the structure of a control device for a back panel indicator light provided in an embodiment of the present disclosure; Fig. 9 A schematic diagram of the structure of a control device for a back panel indicator light provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, and they should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description. It should be noted that the embodiments of the present disclosure and the features therein may be combined with each other without conflict.

[0017] The following describes the control method, device, product and medium of the backplane indicator light according to the embodiments of the present disclosure with reference to the accompanying drawings.

[0018] In order to solve the problem that additional pins need to be added to distinguish different CPUs, as the number of CPUs increases, the pins will be occupied too much and the wiring complexity will increase. This embodiment provides a control method for a backplane indicator light, such as Figure 1 As shown, the method is executed by the mainboard controller, and includes: Step 101: Determine that a first connector of a mainboard controller is connected to a second connector of a backplane controller.

[0019] Among them, the motherboard controller can be a complex programmable logic device (CPLD) chip on the motherboard side; the connector can be a slimline connector, a multi-channel input / output (MultiChannel I / O, MCIO) connector, etc., and there is no specific limitation on this.

[0020] There is a dedicated pin in the connector for transmitting the presence signal, which is used to indicate whether the connector is connected to a cable. The presence signal pin of the second connector (i.e., the backplane connector) is grounded by default, and the presence signal pin of the first connector (i.e., the motherboard connector) is connected to the power supply through a pull-up resistor. At the same time, the presence signal pin of the first connector is also connected to the motherboard controller, and the motherboard controller can read the status of the presence signal pin.

[0021] For the embodiments of the present disclosure, Figure 2 As shown, when the first connector (i.e. Figure 2When there is no cable connected to the Slimline / MCIO connector at the MB end, the level of the first connector in-position signal is pulled high due to the pull-up resistor, so the motherboard controller (i.e. Figure 2 The level state of the first connector in-position signal detected by the CPLD at the MB end is a high level state, and the first connector and the second connector (i.e. Figure 2 If the Slimline / MCIO connector at the NVME BP end is not connected, the motherboard controller will not generate a single bus signal for this line, thus saving motherboard controller resources.

[0022] When the first connector is connected to a cable, the mechanical structure inside the first connector connects the in-position signal pin to the ground, thereby pulling down the level, so that the level state of the first connector in-position signal detected by the motherboard controller is a low level state, thereby determining that the first connector and the second connector are connected, and at this time the motherboard controller generates a single bus signal of the line. The cable can be a high-speed cable.

[0023] Step 102: Select a pin on the side band portion of the first connector.

[0024] For the embodiments of the present disclosure, in order to reduce the pin occupancy of the connector and avoid insufficient pin number, as a possible implementation method, the present application may adopt a single pin to transmit a single bus signal method, and may select a pin in the side band portion of each connector to transmit the single bus signal generated by the motherboard controller through the pin, wherein the side band portion may be the edge portion of the connector, and the single bus signal may be a mechanism for transmitting data through one pin, which may include a CPU number, a virtual pin address, and an indicator light control signal.

[0025] Step 103: Transmitting the single bus signal to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes a CPU number, a virtual pin address and an indicator light control signal.

[0026] For the disclosed embodiment, at the mainboard end, one end of the single bus can be connected to a pin (such as pin B9) of the first connector, at the backplane end, one end of the single bus can be connected to a pin (such as pin A9) of the corresponding second connector, and the other end of the single bus can be connected to the backplane controller. The first connector at the mainboard end and the second connector at the backplane end can be connected via a high-speed cable to ensure that the single bus signal can be quickly and reliably transmitted between the two connectors.

[0027] Therefore, the single bus signal can be transmitted to the corresponding second connector pin at the backplane end through the selected one pin, so as to transmit the single bus signal to the backplane controller through the second connector pin.

[0028] The present application transmits virtual pin addresses through a single bus signal, which can save the dedicated virtual pin signal line between the mainboard and the backplane, not only saving more pins, but also simplifying the complexity of cables and routing. In addition, a broadcast transmission mode can be implemented on each first connector on the mainboard, that is, the mainboard controller sends the same single bus signal to all first connectors, and the backplane controller can directly identify and respond to these signals without manual intervention, thereby improving the automation of the system and reducing the complexity of operation.

[0029] In summary, according to a control method of a backplane indicator light disclosed in the present invention, it is possible to determine that the first connector of the mainboard controller is connected to the second connector of the backplane controller; select a pin in the side band portion of the first connector; transmit a single bus signal to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes the CPU number, the virtual pin address and the indicator light control signal. Compared with the current prior art, the present application adopts a single bus signal transmission method, and transmits a single bus signal containing multiple information such as the CPU number, the virtual pin address and the indicator light control signal from the mainboard controller to the backplane controller through one pin, thereby reducing the number of pins and reducing the complexity of wiring.

[0030] Further, as a refinement and expansion of the above embodiment, in order to fully illustrate the specific implementation process of the disclosed method, the present disclosure provides the following Figure 3 The specific method shown includes: Step 201, receiving an in-place status signal sent by a backplane controller; in response to the in-place status signal, determining that a first connector of a mainboard controller is connected to a second connector of the backplane controller.

[0031] Among them, the in-place status signal can be used to indicate that the target solid-state drive has been inserted into the backplane interface and is correctly identified by the system. The target solid-state drive can be a non-volatile memory host controller interface specification (NVME, Non-Volatile Memory Express) solid-state drive.

[0032] For the embodiment of the present disclosure, after receiving the in-place status signal sent by the backplane controller, the mainboard controller can first determine whether the first connector of the mainboard controller is connected to the second connector of the backplane controller. If the first connector is connected to the second connector of the backplane controller, a pin can be selected in the side band portion of the first connector, and a single bus signal can be transmitted to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal.

[0033] Step 202: Initialize the target register to determine a corresponding table, where the corresponding table at least includes a motherboard controller interface and a corresponding virtual pin address; determine the corresponding virtual pin address of the motherboard controller interface based on the corresponding table.

[0034] The target register may be a VPP_INDEX register.

[0035] For the disclosed embodiment, in the Intel Whitley server platform, the target register can be initialized through the Basic Input / Output System (BIOS) program to configure the virtual pin address corresponding to the motherboard controller interface and generate a corresponding table, wherein the motherboard controller interface can be a PCIE interface, and the corresponding table is shown in Table 1 below.

[0036]

[0037] Table 1 After determining the corresponding virtual pin address of the mainboard controller interface based on the corresponding table, the mainboard controller can encode the CPU number, virtual pin address and indicator light control signal through a single bus protocol to transmit this information to the backplane controller through a single bus signal.

[0038] The single bus signal can be transmitted at a rate of 115200 bits per second (bit / s), with one bit transmitted each time. The backplane controller (operating at 25MHz) can use its own clock to parse the signal.

[0039] like Figure 4 As shown, two different time lengths are shown, namely 1 microsecond (us) and 5 microseconds (us). Different time lengths can be used to represent different signal states, that is, 1 microsecond can be used to represent write data, and 5 microseconds can be used to represent read data.

[0040] When the line is in a low-level state, different types of signals will have different durations. When the motherboard controller needs to write data to the backplane controller, it can send a low-level pulse with a duration of 1 microsecond. During this period, the data is written to the backplane controller. When the motherboard controller needs to read data from the backplane controller, it can wait for a low-level pulse of 5 microseconds. During this period, the motherboard controller can receive the indicator light control signal sent by the backplane controller, which can be used for hot plugging of NVME solid-state drives. Hot plugging can be inserting or removing NVME solid-state drives without turning off the power without affecting the normal operation of the system.

[0041] Figure 4The CPU Reg in may include 0x00 and 0x01. When the value of CPU Reg is 0x00, it may indicate that the information of CPU0 is currently being processed; and when the value of CPU Reg is 0x01, it may indicate that the information of CPU1 is currently being processed.

[0042] Figure 4 The VPP address Reg in may represent the VPP address (ie, virtual pin address) in Table 1, and each PCIE interface corresponds to a different VPP address.

[0043] Figure 4 The lighting information (i.e. indicator light control signal) in the VPP may include data defined by VPP. Figure 5 As shown in FIG. 1 , if the blue backplane indicator light needs to be turned on, the corresponding bit (bit1) can be set to 1; similarly, if the red backplane indicator light needs to be turned on, another bit (bit0) can be set to 1. These lighting information can be transmitted from the mainboard controller to the backplane controller via a single bus protocol, thereby realizing the control of the backplane indicator light.

[0044] Figure 4 The least significant 8 bits (bits) in are used as a cyclic redundancy check (CRC), for example, using the commonly used CRC-8 check method, to ensure the integrity and correctness of the transmitted data. For the specific check process, please refer to the following embodiment steps.

[0045] Step 203, perform cyclic redundancy processing on the data carried by the single bus signal to generate a first cyclic redundancy check code; send the first cyclic redundancy check code to the backplane controller so that the backplane controller performs cyclic redundancy processing on the data carried by the single bus signal to generate a second cyclic redundancy check code, and when the first cyclic redundancy check code is consistent with the second cyclic redundancy check code, control the corresponding backplane indicator light according to the single bus signal.

[0046] For the embodiments of the present disclosure, the mainboard controller can perform cyclic redundancy processing on the data carried by the single bus signal, generate a first cyclic redundancy check code, and send the first cyclic redundancy check code to the backplane controller, so that the backplane controller performs cyclic redundancy processing on the data carried by the single bus signal, generates a second cyclic redundancy check code, and when the first cyclic redundancy check code is consistent with the second cyclic redundancy check code, controls the corresponding backplane indicator light according to the single bus signal to ensure the integrity and correctness of the transmitted data.

[0047] In summary, according to a control method of a backplane indicator light disclosed in the present invention, it is possible to determine that the first connector of the mainboard controller is connected to the second connector of the backplane controller; select a pin in the side band portion of the first connector; transmit a single bus signal to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes the CPU number, the virtual pin address and the indicator light control signal. Compared with the current prior art, the present application adopts a single bus signal transmission method, and transmits a single bus signal containing multiple information such as the CPU number, the virtual pin address and the indicator light control signal from the mainboard controller to the backplane controller through one pin, thereby reducing the number of pins and reducing the complexity of wiring.

[0048] The above embodiment is a control process of the backplane indicator light described on the mainboard controller side. Further, in order to fully illustrate the implementation of this embodiment, this embodiment also provides another method for controlling the backplane indicator light, which is executed by the backplane controller side. Figure 6 As shown, the method includes: Step 301: Receive a single bus signal sent by a mainboard controller through a pin, where the single bus signal at least includes a CPU number, a virtual pin address, and an indicator light control signal.

[0049] The backplane controller may be a complex programmable logic device (CPLD) chip on the backplane side.

[0050] According to the embodiment of the present disclosure, when a single bus signal is transmitted to the backplane end through a selected pin, the backplane end may receive the transmitted single bus signal through a corresponding second connector pin.

[0051] Step 302: Control the corresponding backplane indicator light according to the single bus signal.

[0052] According to the disclosed embodiment, after the backplane controller receives the single bus signal sent by the mainboard controller, it can parse the CPU number, virtual pin address and indicator light control signal from the single bus signal according to the single bus protocol requirements.

[0053] As a possible implementation method, the backplane controller can identify the mainboard CPU that needs to control the backplane indicator light according to the CPU number to control the indicator light of the corresponding backplane. The backplane controller can determine the corresponding backplane indicator light according to the backplane indicator light address identified by the virtual pin address. The backplane controller can execute corresponding commands on the backplane indicator light according to the indicator light control signal, such as controlling the backplane indicator light to turn on or off to indicate the working status of the NVME solid-state drive (such as active status, positioning status or error status), so that technicians can quickly find the target solid-state drive that needs to be checked or replaced.

[0054] In summary, according to a control method of a backplane indicator light disclosed in the present invention, it is possible to determine that the first connector of the mainboard controller is connected to the second connector of the backplane controller; select a pin in the side band portion of the first connector; transmit a single bus signal to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes the CPU number, the virtual pin address and the indicator light control signal. Compared with the current prior art, the present application adopts a single bus signal transmission method, and transmits a single bus signal containing multiple information such as the CPU number, the virtual pin address and the indicator light control signal from the mainboard controller to the backplane controller through one pin, thereby reducing the number of pins and reducing the complexity of wiring.

[0055] Further, as a refinement and expansion of the above embodiment, in order to fully illustrate the specific implementation process of the disclosed method, the present disclosure provides the following Figure 7 The specific method shown includes: Step 401, check whether the target solid state drive has been inserted into the backplane interface; if the target solid state drive has been inserted into the backplane interface, send an in-place status signal to the mainboard controller, so that the mainboard controller responds to the in-place status signal and determines that the first connector of the mainboard controller is connected to the second connector of the backplane controller.

[0056] For the disclosed embodiment, before the backplane end receives the single bus signal transmitted by the mainboard end through a selected pin through the corresponding second connector pin, it can first be checked whether the target solid-state hard disk has been inserted into the backplane interface. When the target solid-state hard disk has been inserted into the backplane interface and is correctly identified by the system, the backplane controller can send an in-place status signal to the mainboard CPU to indicate that the target solid-state hard disk has been inserted into the backplane interface and is correctly identified by the system, so that after receiving the in-place status signal sent by the backplane controller, the mainboard controller responds to the in-place status signal to determine whether the first connector of the mainboard controller is connected to the second connector of the backplane controller. Among them, the backplane interface can be a PCIE interface. The target solid-state hard disk can be a non-volatile memory host controller interface specification (NVME, Non-Volatile Memory Express) solid-state hard disk.

[0057] Step 402, receiving a first cyclic redundancy check code sent by the mainboard controller; performing cyclic redundancy processing on the data carried by the single bus signal to generate a second cyclic redundancy check code; if the first cyclic redundancy check code is consistent with the second cyclic redundancy check code, controlling the corresponding backplane indicator light according to the single bus signal.

[0058] For the embodiments of the present disclosure, in order to ensure the integrity and correctness of the transmitted data, the backplane controller can perform cyclic redundancy processing on the data carried by the received single bus signal (i.e., the CPU number, the virtual pin address, and the indicator light control signal), generate a second cyclic redundancy check code, and compare the second cyclic redundancy check code with the first cyclic redundancy check code sent by the mainboard controller. If the first cyclic redundancy check code is consistent with the second cyclic redundancy check code, it means that no error occurred during the data transmission process, and the corresponding backplane indicator light can be controlled according to the single bus signal; if the first cyclic redundancy check code is inconsistent with the second cyclic redundancy check code, it means that the data may have been interfered with or damaged during the transmission process, and the corresponding backplane indicator light cannot be controlled according to the single bus signal.

[0059] In summary, according to a control method of a backplane indicator light disclosed in the present invention, it is possible to determine that the first connector of the mainboard controller is connected to the second connector of the backplane controller; select a pin in the side band portion of the first connector; transmit a single bus signal to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes the CPU number, the virtual pin address and the indicator light control signal. Compared with the current prior art, the present application adopts a single bus signal transmission method, and transmits a single bus signal containing multiple information such as the CPU number, the virtual pin address and the indicator light control signal from the mainboard controller to the backplane controller through one pin, thereby reducing the number of pins and reducing the complexity of wiring.

[0060] Based on the above Figure 1 and Figure 3 The specific implementation of the method shown in the embodiment provides a control device for the back panel indicator light which can be applied to the mainboard controller end, such as Figure 8 As shown, the device includes: a first determination module 31, a selection module 32, and a transmission module 33; A first determining module 31, used for determining that the first connector of the mainboard controller is connected to the second connector of the backplane controller; A selection module 32, configured to select a pin on a side band portion of the first connector; The transmission module 33 is used to transmit the single bus signal to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes a CPU number, a virtual pin address and an indicator light control signal.

[0061] In a specific application scenario, the first determination module 31 may be used to determine that the first connector is connected to the second connector if the level state of the first connector presence signal is in a low level state.

[0062] In a specific application scenario, the device further includes: a second determination module 34; The second determination module 34 is configured to determine that the first connector is not connected to the second connector if the level state of the first connector presence signal is in a high level state, and then not generate the single bus signal.

[0063] In a specific application scenario, the transmission module 33 may be used to transmit the single bus signal to the corresponding second connector pin of the backplane through the selected pin, so as to transmit the single bus signal to the backplane controller through the second connector pin.

[0064] In a specific application scenario, the device further includes: a third determination module 35, a fourth determination module 36; A third determination module 35, for initializing a target register determination correspondence table, wherein the correspondence table at least includes a motherboard controller interface and a corresponding virtual pin address; The fourth determination module 36 is used to determine the corresponding virtual pin address of the mainboard controller interface based on the corresponding table.

[0065] In a specific application scenario, the device further includes: a first receiving module 37; The first receiving module 37 is used to receive the in-place status signal sent by the backplane controller.

[0066] In a specific application scenario, the first determination module 31 may be used to determine, in response to the in-place status signal, that the first connector of the mainboard controller is connected to the second connector of the backplane controller.

[0067] In a specific application scenario, the device further includes: a first processing module 38, a first sending module 39; A first processing module 38, configured to perform cyclic redundancy processing on the data carried by the single bus signal to generate a first cyclic redundancy check code; The first sending module 39 is used to send the first cyclic redundancy check code to the backplane controller so that the backplane controller performs cyclic redundancy processing on the data carried by the single bus signal to generate a second cyclic redundancy check code, and when the first cyclic redundancy check code is consistent with the second cyclic redundancy check code, the corresponding backplane indicator light is controlled according to the single bus signal.

[0068] It should be noted that the other corresponding descriptions of the functional units involved in the control device for the back panel indicator light on the mainboard controller side provided in this embodiment can be referred to in Figure 1 and Figure 2 The corresponding description of the method in will not be repeated here.

[0069] Further, as Figure 6and Figure 7 The specific implementation of the method shown in the embodiment provides a control device for a backplane indicator light that can be applied to a backplane controller end, such as Fig. 9 As shown, the device includes: a second receiving module 41, a control module 42; A second receiving module 41 is used to receive a single bus signal sent by a mainboard controller through a pin, wherein the single bus signal at least includes a CPU number, a virtual pin address and an indicator light control signal; The control module 42 is used to control the corresponding backplane indicator light according to the single bus signal.

[0070] In a specific application scenario, the second receiving module 41 can be used to receive the single bus signal sent by the mainboard controller through a pin through the corresponding connector pin of the backplane.

[0071] In a specific application scenario, the device further includes: a checking module 43, a second sending module 44; A checking module 43 is used to check whether the target solid state drive has been inserted into the backplane interface; The second sending module 44 is used to send an in-place status signal to the mainboard controller if the target solid state hard disk has been inserted into the backplane interface, so that the mainboard controller responds to the in-place status signal and determines that the first connector of the mainboard controller is connected to the second connector of the backplane controller.

[0072] In a specific application scenario, the device further includes: a third receiving module 45, a second processing module 46, A third receiving module 45, used for receiving a first cyclic redundancy check code sent by the mainboard controller; The second processing module 46 is used to perform cyclic redundancy processing on the data carried by the single bus signal to generate a second cyclic redundancy check code.

[0073] In a specific application scenario, the control module 42 may be used to control a corresponding backplane indicator light according to the single bus signal if the first cyclic redundancy check code is consistent with the second cyclic redundancy check code.

[0074] In a specific application scenario, the control module 42 may be used to determine the corresponding mainboard CPU according to the CPU number; Determine a corresponding backplane indicator light according to the virtual pin address; The back panel indicator light is turned on or off according to the indicator light control signal.

[0075] It should be noted that for other corresponding descriptions of the functional units involved in the control device for the backplane indicator light provided in this embodiment and applicable to the backplane controller side, reference can be made to Figure 5 and Figure 6 The corresponding description of the method in will not be repeated here.

[0076] Based on the above Figure 1 , Figure 3 , Figure 6 and Figure 7 The method shown in the present disclosure, accordingly, also provides a computer-readable storage medium having a computer program stored thereon, which implements the above-mentioned Figure 1 , Figure 3 , Figure 6 and Figure 7 The method shown.

[0077] Based on this understanding, the technical solution of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of various implementation scenarios of the present disclosure.

[0078] Based on the above Figure 1 , Figure 3 , Figure 6 and Figure 7 The method shown, and Figure 8 and Fig. 9 In order to achieve the above-mentioned purpose, the embodiment of the present disclosure also provides an electronic device, which includes a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to achieve the above-mentioned Figure 1 , Figure 3 , Figure 6 and Figure 7 The method shown.

[0079] Optionally, the above-mentioned physical device may also include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a WI-FI module, etc. The user interface may include a display, an input unit such as a keyboard, etc., and the optional user interface may also include a USB interface, a card reader interface, etc. The network interface may optionally include a standard wired interface, a wireless interface (such as a WI-FI interface), etc.

[0080] Those skilled in the art will appreciate that the above-mentioned physical device structure provided by the present disclosure does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different arrangements of components.

[0081] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the above-mentioned physical device, and supports the operation of the information processing program and other software and / or programs. The network communication module is used to realize the communication between the components inside the storage medium, and the communication with other hardware and software in the information processing physical device.

[0082] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present disclosure can be implemented by means of software plus the necessary general hardware platform, or by hardware. Compared with the prior art, the control method, device, product and medium of the backplane indicator light provided by the present disclosure are as follows: the first connector of the motherboard controller is connected to the second connector of the backplane controller; a pin is selected in the side band part of the first connector; a single bus signal is transmitted to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes the CPU number, the virtual pin address and the indicator light control signal. Compared with the current prior art, the present application adopts a single bus signal transmission method, and transmits a single bus signal containing multiple information such as the CPU number, the virtual pin address and the indicator light control signal from the motherboard controller to the backplane controller through one pin, thereby reducing the number of pins and reducing the wiring complexity.

[0083] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0084] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but will conform to the widest scope consistent with the principles and novel features applied for herein.

Claims

1. A method for controlling a back panel indicator light, characterized in that: Executed by the mainboard controller, including: Determine that the first connector of the mainboard controller is connected to the second connector of the backplane controller; selecting a pin on a side band portion of the first connector; The single bus signal is transmitted to the backplane controller through the selected pin, so that the backplane controller controls the corresponding backplane indicator light according to the single bus signal, wherein the single bus signal at least includes a CPU number, a virtual pin address and an indicator light control signal.

2. The method according to claim 1, characterized in that The step of determining that the first connector of the mainboard controller is connected to the second connector of the backplane controller comprises: If the level state of the first connector presence signal is in a low level state, it is determined that the first connector is connected to the second connector.

3. The method according to claim 2, characterized in that The method further comprises: If the level state of the first connector presence signal is in a high level state, it is determined that the first connector is not connected to the second connector, and the single bus signal is not generated.

4. The method according to claim 1, characterized in that: The method of transmitting the single bus signal to the backplane controller through the selected pin comprises: The single bus signal is transmitted to the corresponding second connector pin of the backplane through the selected pin, so as to transmit the single bus signal to the backplane controller through the second connector pin.

5. The method according to claim 1, characterized in that The method further comprises: Initialize the target register to determine a corresponding table, the corresponding table at least including a mainboard controller interface and a corresponding virtual pin address; The corresponding virtual pin address of the mainboard controller interface is determined based on the corresponding table.

6. The method according to claim 1, characterized in that The method further comprises: Receive the in-position status signal sent by the backplane controller; The step of determining that the first connector of the mainboard controller is connected to the second connector of the backplane controller comprises: In response to the in-position status signal, it is determined that the first connector of the mainboard controller is connected to the second connector of the backplane controller.

7. The method according to claim 1, characterized in that The method further comprises: Performing cyclic redundancy processing on the data carried by the single bus signal to generate a first cyclic redundancy check code; The first cyclic redundancy check code is sent to the backplane controller so that the backplane controller performs cyclic redundancy processing on the data carried by the single bus signal to generate a second cyclic redundancy check code, and when the first cyclic redundancy check code is consistent with the second cyclic redundancy check code, the corresponding backplane indicator light is controlled according to the single bus signal.

8. A method for controlling a back panel indicator light, characterized in that: Executed by the backplane controller, the method includes: Receiving a single bus signal sent by a mainboard controller through a pin, wherein the single bus signal includes at least a CPU number, a virtual pin address and an indicator light control signal; The corresponding backplane indicator light is controlled according to the single bus signal.

9. The method according to claim 8, characterized in that The receiving method includes: The single bus signal sent by the mainboard controller through one pin is received through the corresponding connector pin of the backplane.

10. The method according to claim 8, characterized in that The method further comprises: Check whether the target SSD has been inserted into the backplane interface; If the target solid state drive has been inserted into the backplane interface, an in-place status signal is sent to the mainboard controller, so that the mainboard controller responds to the in-place status signal and determines that the first connector of the mainboard controller is connected to the second connector of the backplane controller.

11. The method according to claim 8, characterized in that The method further comprises: Receiving a first cyclic redundancy check code sent by the mainboard controller; Performing cyclic redundancy processing on the data carried by the single bus signal to generate a second cyclic redundancy check code; The controlling of the corresponding backplane indicator light according to the single bus signal comprises: If the first cyclic redundancy check code is consistent with the second cyclic redundancy check code, the corresponding backplane indicator light is controlled according to the single bus signal.

12. The method according to claim 8, characterized in that The controlling of the corresponding backplane indicator light according to the single bus signal comprises: Determine the corresponding motherboard CPU according to the CPU number; Determine a corresponding backplane indicator light according to the virtual pin address; The back panel indicator light is turned on or off according to the indicator light control signal.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 or the method according to any one of claims 8 to 12 is implemented.

14. An electronic device comprising a storage medium, a processor, and a computer program stored in the storage medium and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 or the method according to any one of claims 8 to 12 is implemented.

15. A computer program product, characterized in that The method comprises a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 7, or the method according to any one of claims 8 to 12.

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