Processor and pixel degradation compensation method thereof

Abstract

The invention provides a processor and a pixel degradation compensation method thereof. The processor includes a processing circuit and a pixel degradation compensation circuit. The pixel degradation compensation circuit generates a current degradation value based on the current sub-pixel data, wherein the current degradation value represents a degradation effect of the current sub-pixel data on a corresponding sub-pixel in the display module. The pixel degradation compensation circuit may adjust the current degradation value to generate an adjusted degradation value corresponding to the current sub-pixel data. The adjusted degradation value is accumulated to a total degradation value corresponding to the current sub-pixel data. The pixel degradation compensation circuit compensates the current sub-pixel data based on the total degradation value corresponding to the current sub-pixel data so as to generate compensated current sub-pixel data for the display module.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a processor and a pixel degradation compensation method thereof. Background Art

[0002] For Organic Light-Emitting Diode (OLED) displays, pixel degradation (or burn-in) is one of the many technical issues. Different operating temperatures, OLED materials and driving currents will cause sub-pixels to suffer different degradation effects. A lookup table (LUT) for decay factor (DF) accumulation and data compensation based on optical measurement can overcome this problem. In the case where the brightness of a sub-pixel decays due to degradation, the brightness decay can be improved by appropriately increasing / compensating the digital value (grayscale value) of the sub-pixel data. For degraded sub-pixels, the more severe the brightness decay, the greater the compensation value of the sub-pixel data (the additional compensation current applied to the degraded sub-pixel) to maintain the degraded sub-pixel at the target brightness. In any case, the up-regulation space (compensation area) of the sub-pixel data is limited.

[0003] However, the red sub-pixel, the green sub-pixel, and the blue sub-pixel degrade at different rates. Figure 1 It is a schematic diagram of the characteristic curve of the degradation rate of different color sub-pixels of OLED. Figure 1 The horizontal axis represents the usage time (in hours), while the vertical axis represents the normalized luminance. Figure 1 From the characteristic curves shown, it can be seen that the degradation rate of the blue sub-pixel (characteristic curve B) is greater than the degradation rate of the red sub-pixel (characteristic curve R) and the degradation rate of the green sub-pixel (characteristic curve G). Compared with the red sub-pixel and the green sub-pixel, the compensation area (data upscaling space) of the blue sub-pixel may be saturated first. If the compensation area of ​​any color is saturated while the compensation areas of other colors are not saturated, the display module will have color shift. That is, the display module continues to degrade, but the compensation areas of some colors cannot be effectively compensated due to saturation.

[0004] It should be noted that the contents of the "Background Technology" section are used to help understand the present invention. Some (or all) of the contents disclosed in the "Background Technology" section may not be known to those skilled in the art. The contents disclosed in the "Background Technology" section do not mean that the contents have been known to those skilled in the art before the present invention is applied. Summary of the invention

[0005] The invention provides a processor and a pixel degradation compensation method thereof to compensate for sub-pixel degradation.

[0006] In an embodiment according to the present invention, the above-mentioned processor includes a processing circuit and a pixel degradation compensation circuit. The pixel degradation compensation circuit is coupled to the processing circuit to receive a sub-pixel data stream. The pixel degradation compensation circuit is used to compensate the sub-pixel data stream to generate a compensated sub-pixel data stream for the display module. The pixel degradation compensation circuit generates a current degradation value corresponding to the current sub-pixel data based on the current sub-pixel data in the sub-pixel data stream, wherein the current degradation value represents the degradation effect of the current sub-pixel data on the sub-pixel corresponding to the current sub-pixel data in the display module. The pixel degradation compensation circuit selectively adjusts the current degradation value to generate an adjusted degradation value. The pixel degradation compensation circuit adds the adjusted degradation value to the total degradation value corresponding to the current sub-pixel data. The pixel degradation compensation circuit compensates the current sub-pixel data based on the total degradation value corresponding to the current sub-pixel data to generate the compensated current sub-pixel data in the compensated sub-pixel data stream for the display module.

[0007] In an embodiment according to the present invention, the above-mentioned pixel degradation compensation method includes: generating a current degradation value corresponding to the current sub-pixel data based on the current sub-pixel data in the sub-pixel data stream, wherein the current degradation value represents the degradation effect of the current sub-pixel data on the sub-pixel corresponding to the current sub-pixel data in the display module; selectively adjusting the current degradation value to generate an adjusted degradation value; adding the adjusted degradation value to the total degradation value corresponding to the current sub-pixel data; and compensating the current sub-pixel data based on the total degradation value corresponding to the current sub-pixel data to generate the compensated current sub-pixel data in the compensated sub-pixel data stream for the display module.

[0008] Based on the above, the pixel degradation compensation circuit described in the embodiments of the present invention can compensate the sub-pixel data stream of the processing circuit to generate a compensated sub-pixel data stream to the display module. In an embodiment, the pixel degradation compensation circuit can apply "dynamic decay factor accumulation speed" to compensate the sub-pixel degradation of the display module to overcome the technical issue of color shift. In detail, after the pixel degradation compensation circuit generates the current degradation value based on the current sub-pixel data, the pixel degradation compensation circuit can determine whether to adjust the current degradation value to be added to the total degradation value based on the margin (margin, also known as "surplus amount" or "margin") of the compensation value in the compensation area (and / or based on the margin of the total degradation value in the total degradation value range) so as to slow down the degradation value accumulation speed before the compensation area is saturated (and / or before the total degradation value range is saturated). Based on this, the pixel degradation compensation circuit can slow down the time course of saturation of the compensation area (and / or the total degradation value range) to avoid the occurrence of color shift. In addition, the pixel degradation compensation circuit can slow down the accumulation speed of the total degradation value (reduce the additional compensation current for the sub-pixel) as appropriate to extend the life of the sub-pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of the characteristic curve of the degradation rate of different color sub-pixels of OLED.

[0010] Figure 2 It is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention.

[0011] Figure 3 It is a flowchart of a pixel degradation compensation method according to an embodiment of the present invention.

[0012] Figure 4 FIG. 1 is a circuit block diagram of a processing circuit and a pixel degradation compensation circuit according to an embodiment of the present invention.

[0013] Figure 5 It is a flowchart of a pixel degradation compensation method according to another embodiment of the present invention.

[0014] Figure 6 FIG. 4 is a schematic diagram illustrating remapping of an original data stream to a sub-pixel data stream according to an embodiment of the present invention.

[0015] Figure 7 FIG. 4 is a schematic diagram of a margin of a total degradation range according to an embodiment of the present invention.

[0016] Figure 8FIG. 4 is a circuit block diagram of a processing circuit and a pixel degradation compensation circuit according to another embodiment of the present invention.

[0017] Fig. 9 It is a flowchart of a pixel degradation compensation method according to another embodiment of the present invention.

[0018] Fig.10 FIG. 4 is a schematic diagram of a margin of a compensation area according to an embodiment of the present invention.

[0019] Fig.11 It is a flowchart of a pixel degradation compensation method according to another embodiment of the present invention.

[0020] Fig.12 FIG. 4 is a schematic diagram of locally adjusting the accumulated acceleration weight of a sub-pixel array according to an embodiment of the present invention.

[0021] Fig.13 is a flowchart of a pixel degradation compensation method according to another embodiment of the present invention.

[0022] Description of Reference Numerals

[0023] 10: Display module

[0024] 200: Processor

[0025] 210: Processing circuit

[0026] 211: Image processing circuit

[0027] 212: Remap Circuit

[0028] 220: Pixel degradation compensation circuit

[0029] 221: Degradation value generation circuit

[0030] 222: Multiplication Circuit

[0031] 223: Degradation value accumulation circuit

[0032] 224, 227: Accumulated speed adjustment circuit

[0033] 225: Compensation value circuit

[0034] 226: Compensation Circuit

[0035] B, G, R: characteristic curve

[0036] CR: Compensation area

[0037] CV4: Compensation value

[0038] D1: Raw data stream

[0039] D2: Sub-pixel data streaming

[0040] D3: Compensated sub-pixel data stream

[0041] DF41: Current degradation value

[0042] DF42: Adjusted degradation value

[0043] IR: Image area

[0044] S310~S340, S510~S560, S910~S960, S1110~S1170, S1310~S1370: Steps

[0045] TDF: Total Degradation Value

[0046] TDF4: Total degradation value

[0047] W: Accumulated acceleration weight DETAILED DESCRIPTION

[0048] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0049] The term "coupled (or connected)" used in the entire specification of this application (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire specification of this application (including the claims) are used to name the components (element) or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components. In addition, wherever possible, components / components / steps with the same number in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same number or the same terminology in different embodiments can refer to the relevant descriptions of each other.

[0050] Figure 2 It is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention. Figure 2The display device shown includes a display module 10 and a processor 200. Based on actual conditions, the display module 10 may include an organic light-emitting diode (OLED) display panel or other display panels. Based on decay factors (DF) such as usage time, temperature, material, and driving current, different sub-pixels of the display module 10 may suffer different degradation effects. In the case where the brightness of a sub-pixel decays due to degradation, the actual brightness of the degraded sub-pixel may be lower than the target brightness.

[0051] exist Figure 2 In the illustrated embodiment, the processor 200 includes a processing circuit 210 and a pixel degradation compensation circuit 220. According to different designs, in some embodiments, the processor 200, the processing circuit 210 and (or) the pixel degradation compensation circuit 220 may be implemented as a hardware circuit. In other embodiments, the processor 200, the processing circuit 210 and (or) the pixel degradation compensation circuit 220 may be implemented as firmware, software (i.e., program) or a combination of the two. In still other embodiments, the processor 200, the processing circuit 210 and (or) the pixel degradation compensation circuit 220 may be implemented as a combination of hardware, firmware, and software.

[0052] In terms of hardware, the processor 200, the processing circuit 210 and / or the pixel degradation compensation circuit 220 may be implemented as a logic circuit on an integrated circuit. For example, the functions of the processor 200, the processing circuit 210 and / or the pixel degradation compensation circuit 220 may be implemented in various logic blocks, modules and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs) and / or other processing units. The functions of the processor 200, the processing circuit 210 and / or the pixel degradation compensation circuit 220 may be implemented as hardware circuits, such as various logic blocks, modules and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0053] In software form and / or firmware form, the above-mentioned processor 200, processing circuit 210 and (or) pixel degradation compensation circuit 220 related functions can be implemented as programming codes. For example, the processor 200, processing circuit 210 and (or) pixel degradation compensation circuit 220 are implemented using general programming languages ​​(such as C, C++ or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and (or) a storage device. An electronic device (such as a computer, a CPU, a controller, a processor, a microcontroller or a microprocessor) can read and execute the programming code from the non-transitory machine-readable storage medium to implement the processor 200, the processing circuit 210 and (or) the pixel degradation compensation circuit 220 related functions.

[0054] The pixel degradation compensation circuit 220 is coupled to the processing circuit 210 to receive the sub-pixel data stream D2. The pixel degradation compensation circuit 220 can compensate the sub-pixel data stream D2 to generate a compensated sub-pixel data stream D3 for the display module 10. The pixel degradation compensation circuit 220 can apply the "Dynamic Decay Factor Accumulate Speed" technology to compensate for the sub-pixel degradation of the display module 10 to overcome the technical issue of color shift. The following will illustrate a specific example of the "Dynamic Decay Factor Accumulate Speed" technology.

[0055] Figure 3 It is a schematic flowchart of a pixel degradation compensation method according to an embodiment of the present invention. Please refer to Figure 2 and Figure 3 . In step S310, the pixel degradation compensation circuit 220 can generate a current degradation value corresponding to the current sub-pixel data based on the current sub-pixel data in the sub-pixel data stream D2. Wherein, the current degradation value represents the degradation effect of the current sub-pixel data (driving current) on a certain sub-pixel corresponding to the current sub-pixel data in the display module 10. The algorithm of the degradation value is not limited in this embodiment. For example, the pixel degradation compensation circuit 220 can use a known algorithm or other algorithms in step S310 to calculate the current degradation value corresponding to the current sub-pixel data based on at least one of many attenuation factors such as sub-pixel data (driving current), usage time, temperature, etc.

[0056] The driving value range (total gray scale range) of the display module 10 can be divided into an image area and a compensation area. For example, assuming that the driving value range of the display module 10 is from 0 to N, the gray scale range from 0 to n can be defined as the image area, and the gray scale range from n + 1 to N can be defined as the compensation area, where n and N are integers determined according to the actual design, and 0 < n < N. In step S320, the pixel degradation compensation circuit 220 can selectively adjust the current degradation value to generate an adjusted degradation value. This operation can be performed dynamically. For example (but not limited to), when there is sufficient margin in the compensation area (and / or sufficient margin in the total degradation value range), the pixel degradation compensation circuit 220 can decide not to adjust the current degradation value, that is, directly use the current degradation value as the adjusted degradation value. When there is little margin in the compensation area (and / or little margin in the total degradation value range), the pixel degradation compensation circuit 220 can generate the adjusted degradation value that is less than the current degradation value.

[0057] In step S330, the pixel degradation compensation circuit 220 may add the adjusted degradation value to the total degradation value corresponding to the current sub-pixel data. The pixel degradation compensation circuit 220 may save the total degradation value corresponding to each sub-pixel of the display module 10. For example, assuming that the display module 10 has x*y pixels and each pixel has three sub-pixels of different colors, the pixel degradation compensation circuit 220 may save x*y*3 total degradation values ​​in a total degradation value lookup table (LUT). Each total degradation value represents the current degradation degree of a corresponding sub-pixel.

[0058] In step S340, based on the total degradation value corresponding to the current sub-pixel data, the pixel degradation compensation circuit 220 can compensate the current sub-pixel data to generate the compensated current sub-pixel data in the compensated sub-pixel data stream D3 to the display module 10. For example, a compensation value lookup table prepared in advance based on an actual design can be configured in the pixel degradation compensation circuit 220. The pixel degradation compensation circuit 220 can look up the compensation value lookup table based on the total degradation value corresponding to the current sub-pixel data to obtain the compensation value corresponding to the total degradation value. The pixel degradation compensation circuit 220 can use this compensation value to compensate the current sub-pixel data to generate the compensated current sub-pixel data. Therefore, in the case where the brightness of the sub-pixel is attenuated due to degradation, the degraded sub-pixel can be maintained at the target brightness by appropriately raising / compensating the digital value (grayscale value) of the sub-pixel data.

[0059] In summary, the pixel degradation compensation circuit 220 described in this embodiment can compensate the sub-pixel data stream D2 of the processing circuit 210 to generate a compensated sub-pixel data stream D3 for the display module 10. After the pixel degradation compensation circuit 220 generates the current degradation value based on the current sub-pixel data, the pixel degradation compensation circuit 220 can determine whether to adjust the current degradation value to be added to the total degradation value based on the margin of the compensation value in the compensation area (and / or based on the margin of the total degradation value in the total degradation value range) so as to slow down the degradation value accumulation speed before the compensation area is saturated (and / or before the total degradation value range is saturated). Therefore, the pixel degradation compensation circuit 220 can apply the "dynamic attenuation factor accumulation speed" technology to compensate for the sub-pixel degradation of the display module. Based on this, the pixel degradation compensation circuit 220 can slow down the time course of saturation of the compensation area (and / or the total degradation value range) to avoid the occurrence of color shift. In addition, the pixel degradation compensation circuit 220 can slow down the accumulation speed of the total degradation value (reduce the increase of the additional compensation current for the sub-pixel) as appropriate to extend the life of the sub-pixel.

[0060] Figure 4 FIG. 2 is a circuit block diagram of a processing circuit 210 and a pixel degradation compensation circuit 220 according to an embodiment of the present invention. Figure 4 The illustrated processing circuit 210 and pixel degradation compensation circuit 220 can be used as Figure 2 one of many implementation examples of the illustrated processing circuit 210 and pixel degradation compensation circuit 220. Figure 4 For the illustrated display module 10, processing circuit 210 and pixel degradation compensation circuit 220, reference can be made to Figure 2 and Figure 3 for the relevant description, so it will not be elaborated here. In Figure 4 the illustrated embodiment, the processing circuit 210 includes an image processing circuit 211 and a remapping circuit 212, and the pixel degradation compensation circuit 220 includes a degradation value generation circuit 221, a multiplication circuit 222, a degradation value accumulation circuit 223, an accumulation speed adjustment circuit 224, a compensation value circuit 225, and a compensation circuit 226.

[0061] Figure 5 is a flowchart showing a pixel degradation compensation method according to another embodiment of the present invention. Please refer to Figure 4 and Figure 5 . In step S510, the output data (original data stream D1) of the image processing circuit 211 is input to the remapping circuit 212. The remapping circuit 212 is coupled to the image processing circuit 211 to receive the original data stream D1. In step S520, the remapping circuit 212 remaps the original data stream D1 to a sub-pixel data stream D2.

[0062] Figure 6 is illustrated according to an embodiment of the present invention, which is a schematic diagram of remapping the original data stream D1 to the sub-pixel data stream D2. Figure 6 The vertical axis of represents the gray level. Figure 6 The left part of shows the value range (total gray level range) of the original data stream D1. In Figure 6 the illustrated embodiment, the value range of the original data stream D1 is assumed to be from 0 to M, where M is an integer determined according to the actual design. Figure 6 The right part of shows the driving value range (total gray level range) of the display module 10, that is, the value range of the compensated sub-pixel data stream D3. The driving value range of the display module 10 can be divided into an image area IR and a compensation area CR. For example, assuming the driving value range of the display module 10 is from 0 to N, then the gray level range from 0 to n can be defined as the image area IR, and the gray level range from n + 1 to N can be defined as the compensation area CR, where n and N are integers determined according to the actual design, and 0 < n < N. The remapping circuit 212 remaps the original data stream D1 to the sub-pixel data stream D2, where each sub-pixel data in the sub-pixel data stream D2 belongs to the image area IR.

[0063] Please refer to Figure 4 and Figure 5 . The degradation value generating circuit 221 is coupled to the processing circuit 210 to receive the sub-pixel data stream D2. The degradation value generating circuit 221 can generate a current degradation value DF41 corresponding to the current sub-pixel data based on the current sub-pixel data in the sub-pixel data stream D2. The current degradation value DF41 represents the degradation effect of the current sub-pixel data (driving current) on a corresponding sub-pixel in the display module 10. This embodiment does not limit the algorithm of the degradation value. For example, the degradation value generating circuit 221 can use a known algorithm or other algorithms to calculate the current degradation value DF41 corresponding to the current sub-pixel data based on at least one of the attenuation factors such as sub-pixel data (driving current), usage time, temperature, etc.

[0064] The multiplication circuit 222 is coupled to the degradation value generation circuit 221 to receive the current degradation value DF41. The multiplication circuit 222 can adjust the current degradation value DF41 based on the cumulative speed weight W to generate an adjusted degradation value DF42 corresponding to the current sub-pixel data. For example (but not limited to this), when the total degradation value range has sufficient margin, the cumulative speed weight W is "1", so the multiplication circuit 222 directly uses the current degradation value DF41 as the adjusted degradation value DF42. When the margin of the total degradation value range is very small, the cumulative speed weight W is less than 1, so the multiplication circuit 222 can generate an adjusted degradation value DF42 that is less than the current degradation value DF41.

[0065] The degradation value accumulation circuit 223 is coupled to the multiplication circuit 222 to receive the adjusted degradation value DF42. The degradation value accumulation circuit 223 can accumulate the adjusted degradation value DF42 corresponding to the current sub-pixel data to the total degradation value TDF4 corresponding to the current sub-pixel data. The degradation value accumulation circuit 223 can save the total degradation value TDF4 corresponding to each sub-pixel of the display module 10. For example, assuming that the display module 10 has x*y pixels and each pixel has three sub-pixels of different colors, the degradation value accumulation circuit 223 can save x*y*3 total degradation values ​​in the total degradation value lookup table. Among them, each total degradation value represents the current degradation degree of a corresponding sub-pixel.

[0066] The cumulative speed adjustment circuit 224 is coupled to the degradation value accumulation circuit 223 to receive the total degradation value TDF4. In any case, the total degradation value range of the total degradation value TDF4 is limited. For example, the memory used to store the total degradation value lookup table is limited, resulting in that the limited value range of the total degradation value TDF4 may be saturated. For another example, the number of bits of the total degradation value TDF4 is limited, resulting in that the limited value range of the total degradation value TDF4 may be saturated. In step S530, the cumulative speed adjustment circuit 224 of the pixel degradation compensation circuit 220 can check the margin of the total degradation value TDF4 corresponding to each sub-pixel data in an image frame of the sub-pixel data stream D2 in the total degradation value range to obtain a check result. In step S540, the cumulative speed adjustment circuit 224 can adjust the cumulative speed weight W corresponding to the current sub-pixel data based on the check result of the total degradation value TDF4.

[0067] In one embodiment, in response to the inspection result indicating that the margin of the total degradation value TDF4 corresponding to any sub-pixel data in the image frame in the total degradation value domain is greater than the first threshold, the cumulative speed adjustment circuit 224 can adjust the cumulative speed weight W to a first weight value. The first threshold can be determined according to the actual design. In response to the inspection result indicating that the margin of the total degradation value TDF4 corresponding to any sub-pixel data in the image frame in the total degradation value domain is less than the first threshold, the cumulative speed adjustment circuit 224 can adjust the cumulative speed weight W to a second weight value less than the first weight value. The first weight value and the second weight value can be determined according to the actual design. For example, the first weight value is 1, and the second weight value is a positive number less than 1.

[0068] In another embodiment, in response to the inspection result indicating that the margin of the total degradation value TDF4 corresponding to any sub-pixel data in the image frame in the total degradation value domain is less than the first threshold and greater than the second threshold, the cumulative speed adjustment circuit 224 can adjust the cumulative speed weight W to the second weight value. The first threshold and the second threshold can be determined according to the actual design, wherein the first threshold is greater than the second threshold. In response to the inspection result indicating that the margin of the total degradation value TDF4 corresponding to any sub-pixel data in the image frame in the total degradation value domain is less than the second threshold, the cumulative speed adjustment circuit 224 can adjust the cumulative speed weight W to a third weight value less than the second weight value. The second weight value and the third weight value can be determined according to the actual design.

[0069] For example, Figure 7 FIG. 4 is a schematic diagram of a total degradation range according to an embodiment of the present invention. Figure 7The horizontal axis represents the total degradation value (TDF). The cumulative speed adjustment circuit 224 can decide whether to adjust the cumulative speed weight W to the multiplication circuit 222 based on the margin of the total degradation value TDF4 in the total degradation value range. For example, if the margin of the total degradation value TDF4 of all sub-pixels in the total degradation value range exceeds 30%, indicating that there is sufficient margin in the total degradation value range, the cumulative speed adjustment circuit 224 can set the cumulative speed weight W to "1". If the margin of the total degradation value TDF4 of any sub-pixel in the total degradation value range is less than 30% but greater than 10%, the cumulative speed adjustment circuit 224 can set the cumulative speed weight W to "0.9". If the margin of the total degradation value TDF4 of any sub-pixel in the total degradation value range is less than 10%, the cumulative speed adjustment circuit 224 can set the cumulative speed weight W to "0.8".

[0070] Please refer to Figure 4 and Figure 5 . In the "global" implementation example, the same cumulative acceleration weight W applies to the degradation value corresponding to each sub-pixel data in the same image frame. In step S550, the multiplication circuit 222 of the pixel degradation compensation circuit 220 adjusts the current degradation value DF41 based on the cumulative acceleration weight W to generate an adjusted degradation value DF42 corresponding to the current sub-pixel data. In step S550, the degradation value accumulation circuit 223 can accumulate the adjusted degradation value DF42 corresponding to the current sub-pixel data to the total degradation value TDF4 corresponding to the current sub-pixel data. Therefore, before the total degradation value domain of any total degradation value TDF4 is saturated, the cumulative speed adjustment circuit 224 can slow down the degradation value accumulation speed.

[0071] The compensation value circuit 225 is coupled to the degradation value accumulation circuit 223 to receive the total degradation value TDF4. In step S560, the compensation value circuit 225 generates a compensation value CV4 corresponding to the current sub-pixel data based on the total degradation value TDF4. The present embodiment does not limit the algorithm of the compensation value. For example, the compensation value circuit 225 can use a known algorithm or other algorithms to convert the total degradation value TDF4 into the compensation value CV4. For another example, the compensation value circuit 225 can obtain the compensation value CV4 from the lookup table based on the total degradation value TDF4. The compensation circuit 226 is coupled to the processing circuit 210 to receive the sub-pixel data stream D2. The compensation circuit 226 is coupled to the compensation value circuit 225 to receive the compensation value CV4. In step S560, the compensation circuit 226 compensates the current sub-pixel data in the sub-pixel data stream D2 based on the compensation value CV4 to generate compensated current sub-pixel data for the display module 10. For example, the compensation circuit 226 may add the compensation value CV4 to the current sub-pixel data in the compensation sub-pixel data stream D2 to generate compensated current sub-pixel data for the display module 10 .

[0072] Figure 8 FIG. 2 is a circuit block diagram of a processing circuit 210 and a pixel degradation compensation circuit 220 according to another embodiment of the present invention. Figure 8 The processing circuit 210 and the pixel degradation compensation circuit 220 can be used as Figure 2 The processing circuit 210 and the pixel degradation compensation circuit 220 are shown as one of many implementation examples. Figure 8 The display module 10, the processing circuit 210 and the pixel degradation compensation circuit 220 can refer to Figure 2 and Figure 3 The relevant instructions are not repeated here. Figure 8 In the illustrated embodiment, the processing circuit 210 includes an image processing circuit 211 and a remapping circuit 212, and the pixel degradation compensation circuit 220 includes a degradation value generating circuit 221, a multiplication circuit 222, a degradation value accumulation circuit 223, a compensation value circuit 225, a compensation circuit 226 and an accumulation speed adjustment circuit 227. Figure 8 The image processing circuit 211 and the remapping circuit 212 can refer to Figure 4 and Figure 6 Related instructions: Figure 8 The degradation value generating circuit 221, the multiplication circuit 222, the degradation value accumulating circuit 223, the compensation value circuit 225 and the compensation circuit 226 can refer to Figure 4 and Figure 6 The relevant instructions are not repeated here.

[0073] The compensation value circuit 225 generates a compensation value CV4 corresponding to the current sub-pixel data based on the total degradation value TDF4. The cumulative speed adjustment circuit 227 adjusts the cumulative speed weight W to the multiplication circuit 222 based on the compensation value CV4. The compensation circuit 226 compensates the current sub-pixel data in the sub-pixel data stream D2 based on the compensation value CV4 to generate compensated current sub-pixel data for the display module 10. For example, the compensation circuit 226 can add the compensation value CV4 to the current sub-pixel data in the compensated sub-pixel data stream D2 to generate compensated current sub-pixel data for the display module 10. That is, the compensated sub-pixel data stream D3 will use the compensation area CR to apply additional compensation current to the degraded sub-pixel. In any case, the adjustment space (compensation area CR) of the compensated current sub-pixel data is limited.

[0074] Fig. 9 It is a flowchart of a pixel degradation compensation method according to another embodiment of the present invention. Fig. 9 The steps S910 and S920 shown in FIG. Figure 5 The relevant description of step S510 and step S520 is shown, Fig. 9The steps S940, S950 and S960 shown in FIG. Figure 5 The relevant descriptions of steps S540, S550 and S560 are not repeated here. Figure 8 and Fig. 9 . The accumulated speed adjustment circuit 227 is coupled to the compensation value circuit 225 to receive the compensation value CV4. In step S930, the accumulated speed adjustment circuit 227 of the pixel degradation compensation circuit 220 may check the margin of the compensation value CV4 corresponding to each sub-pixel data in an image frame of the sub-pixel data stream D2 in the compensation area CR to obtain a check result. In step S940, the accumulated speed adjustment circuit 227 may adjust the accumulated speed weight W corresponding to the current sub-pixel data based on the check result of the compensation value CV4 (the margin of the compensation area CR). The multiplication circuit 222 adjusts the current degradation value DF41 based on the accumulated speed weight W to generate an adjusted degradation value DF42 corresponding to the current sub-pixel data.

[0075] In one embodiment, in response to the inspection result indicating that the margin of the compensation value CV4 corresponding to any sub-pixel data in the image frame in the compensation area CR is greater than the first threshold, the cumulative acceleration adjustment circuit 227 adjusts the cumulative acceleration weight W to a first weight value. The first threshold can be determined according to the actual design. In response to the inspection result indicating that the margin of the compensation value CV4 corresponding to any sub-pixel data in the image frame in the compensation area CR is less than the first threshold, the cumulative acceleration adjustment circuit 227 adjusts the cumulative acceleration weight W to a second weight value less than the first weight value. The first weight value and the second weight value can be determined according to the actual design. For example, the first weight value is 1, and the second weight value is a positive number less than 1.

[0076] In another embodiment, in response to the inspection result indicating that the margin of the compensation value CV4 corresponding to any sub-pixel data in the image frame in the compensation area CR is less than the first threshold and greater than the second threshold, the cumulative acceleration adjustment circuit 227 adjusts the cumulative acceleration weight W to the second weight value. The first threshold and the second threshold can be determined according to the actual design, wherein the first threshold is greater than the second threshold. In response to the inspection result indicating that the margin of the compensation value CV4 corresponding to any sub-pixel data in the image frame in the compensation area CR is less than the second threshold, the cumulative acceleration adjustment circuit 227 adjusts the cumulative acceleration weight W to a third weight value less than the second weight value. The second weight value and the third weight value can be determined according to the actual design.

[0077] For example, Fig.10 FIG. 4 is a schematic diagram showing a margin of a compensation region CR according to an embodiment of the present invention. Fig.10The horizontal axis represents the margin of the compensation region CR. The cumulative acceleration adjustment circuit 227 can decide whether to adjust the cumulative acceleration weight W to the multiplication circuit 222 based on the margin of the compensation value CV4 in the compensation region CR. For example, if the margin of the compensation value CV4 of all sub-pixels in the compensation region CR exceeds 30%, indicating that the compensation region CR has sufficient margin, the cumulative acceleration adjustment circuit 227 can set the cumulative acceleration weight W to "1". If the margin of the compensation value CV4 of any sub-pixel in the compensation region CR is less than 30% but greater than 10%, the cumulative acceleration adjustment circuit 227 can set the cumulative acceleration weight W to "0.9". If the margin of the compensation value CV4 of any sub-pixel in the compensation region CR is less than 10%, the cumulative acceleration adjustment circuit 227 can set the cumulative acceleration weight W to "0.8". In the "global" implementation example, the same cumulative acceleration weight W applies to the degradation value corresponding to each sub-pixel data in the same image frame.

[0078] Fig.11 It is a flowchart of a pixel degradation compensation method according to another embodiment of the present invention. Fig.11 The steps S1110, S1120, S1130, S1140, S1160 and S1170 shown in FIG. Figure 5 The relevant descriptions of steps S510, S520, S530, S540, S550 and step S560 are not repeated here. Figure 4 and Fig.11 In step S1130, the accumulated speed adjustment circuit 224 may check the margin of the total degradation value TDF4 corresponding to the current sub-pixel data of the sub-pixel data stream D2 in the total degradation value domain to obtain a check result. In step S1140, the accumulated speed adjustment circuit 224 may adjust the accumulated speed weight W corresponding to the current sub-pixel data based on the check result of the total degradation value TDF4. The multiplication circuit 222 adjusts the current degradation value DF41 based on the accumulated speed weight W to generate an adjusted degradation value DF42 corresponding to the current sub-pixel data.

[0079] In the "Local" implementation example, the accumulated acceleration weight W corresponding to different sub-pixel data in the same image frame may be different. In one embodiment, in response to the inspection result indicating that the margin of the total degradation value TDF4 corresponding to the current sub-pixel data in the total degradation value domain is greater than the first threshold, the accumulated acceleration adjustment circuit 224 can adjust the accumulated acceleration weight W corresponding to the current sub-pixel data to a first weight value. The first threshold can be determined according to the actual design. In response to the inspection result indicating that the margin of the total degradation value TDF4 corresponding to the current sub-pixel data in the total degradation value domain is less than the first threshold, the accumulated acceleration adjustment circuit 224 can adjust the accumulated acceleration weight W corresponding to the current sub-pixel data to a second weight value less than the first weight value. The first weight value and the second weight value can be determined according to the actual design. For example, the first weight value is 1, and the second weight value is a positive number less than 1. In response to the accumulated acceleration weight W corresponding to the current sub-pixel data being adjusted to the second weight value, the accumulated acceleration weight W corresponding to at least one neighboring sub-pixel data near the current sub-pixel data in the image frame is adjusted to a third weight value that is less than the first weight value and greater than the second weight value.

[0080] Fig.12 FIG. 4 is a schematic diagram of locally adjusting the accumulated acceleration weight W of a sub-pixel array according to an embodiment of the present invention. Fig.12 A display panel (display module) having 9*9 sub-pixels is shown, where each number represents the accumulated acceleration weight W corresponding to the sub-pixel. Fig.12 In the illustrated embodiment, it is assumed that the margin of the total degradation value TDF4 corresponding to the sub-pixel in the 7th row and the 3rd column in the total degradation value range is less than a certain threshold value (determined by the actual design), so that the accumulated acceleration weight W corresponding to this sub-pixel is adjusted to "0.5". In addition, it is assumed that the margin of the total degradation value TDF4 corresponding to other sub-pixels in the total degradation value range is greater than a certain threshold value (determined by the actual design), so that the accumulated acceleration weight W corresponding to these sub-pixels can be maintained as "1".

[0081] Please refer to Fig.11 and Fig.12. In step S1150, based on the accumulated acceleration weight W "0.5" corresponding to the sub-pixel in the 7th row and the 3rd column and the accumulated acceleration weight W "1" corresponding to other sub-pixels, the accumulated acceleration adjustment circuit 224 can smooth the accumulated acceleration weight W of one or more neighboring sub-pixels near the sub-pixel in the 7th row and the 3rd column. For example, in response to the accumulated acceleration weight W corresponding to the sub-pixel data in the 7th row and the 3rd column being adjusted to "0.5", the accumulated acceleration weight W corresponding to at least one neighboring sub-pixel data near the current sub-pixel data in the image frame is adjusted to a third weight value (e.g., "0.7" or other positive value) that is less than "1" (the first weight value) and greater than "0.5" (the second weight value).

[0082] Fig.13 is a flowchart of a pixel degradation compensation method according to another embodiment of the present invention. Fig.13 The steps S1310, S1320, S1330, S1340, S1360 and S1370 shown in FIG. Fig. 9 The relevant descriptions of steps S910, S920, S930, S940, S950 and step S960 are shown, so they are not repeated here. Figure 8 and Fig.13 In step S1330, the accumulated speed adjustment circuit 227 may check the margin of the compensation value CV4 corresponding to the current sub-pixel data of the sub-pixel data stream D2 in the compensation region CR to obtain a check result. In step S1340, the accumulated speed adjustment circuit 227 may adjust the accumulated speed weight W corresponding to the current sub-pixel data based on the check result of the compensation value CV4 (the margin of the compensation region CR). The multiplication circuit 222 adjusts the current degradation value DF41 based on the accumulated speed weight W to generate an adjusted degradation value DF42 corresponding to the current sub-pixel data. Fig.13 The step S1350 shown can refer to Fig.11 Step S1150 and Fig.12 The relevant instructions are not repeated here.

[0083] In the "local" implementation example, the accumulated acceleration weights W corresponding to different sub-pixel data in the same image frame may be different. In one embodiment, in response to the inspection result indicating that the margin of the compensation value CV4 corresponding to the current sub-pixel data in the compensation area CR is greater than the first threshold, the accumulated acceleration adjustment circuit 227 can adjust the accumulated acceleration weight W corresponding to the current sub-pixel data to a first weight value. The first threshold can be determined according to the actual design. In response to the inspection result indicating that the margin of the compensation value CV4 corresponding to the current sub-pixel data in the compensation area CR is less than the first threshold, the accumulated acceleration adjustment circuit 227 can adjust the accumulated acceleration weight W corresponding to the current sub-pixel data to a second weight value less than the first weight value. The first weight value and the second weight value can be determined according to the actual design. For example, the first weight value is 1, and the second weight value is a positive number less than 1. In response to the accumulated acceleration weight W corresponding to the current sub-pixel data being adjusted to the second weight value, the accumulated acceleration weight W corresponding to at least one adjacent sub-pixel data near the current sub-pixel data in the image frame is adjusted to a third weight value less than the first weight value and greater than the second weight value. For example, see Fig.12 In response to the accumulated acceleration weight W corresponding to the sub-pixel data in the 7th row and the 3rd column being adjusted to "0.5", the accumulated acceleration weight W corresponding to at least one neighboring sub-pixel data near the current sub-pixel data in the image frame is adjusted to a third weight value (for example, "0.7" or other positive value) that is less than "1" (the first weight value) and greater than "0.5" (the second weight value).

[0084] In summary, the above embodiments apply "Dynamic Decay Factor Accumulate Speed" to overcome the technical issues of color shift in general compensation algorithms. If the accumulated speed weight W is "1" (the accumulated speed is 100%), the sub-pixel degradation will be compensated to return the brightness of the sub-pixel to the target brightness. The above embodiments can continuously check the margin of the total degradation value TDF4 in the total degradation value range, and / or continuously check the margin of the compensation area CR. Based on the inspection results, the accumulated speed weight W (the accumulated speed of the degradation value) can be adjusted to slow down the saturation of the compensation area CR (and / or slow down the saturation of the total degradation value range of the total degradation value TDF4). In addition, the pixel degradation compensation circuit can slow down the accumulated speed of the total degradation value (reduce the additional compensation current for the sub-pixel) as appropriate to extend the life of the sub-pixel.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A processor, characterized in that: The processor comprises: processing circuitry; and A pixel degradation compensation circuit is coupled to the processing circuit to receive a sub-pixel data stream, and is used to compensate the sub-pixel data stream to generate a compensated sub-pixel data stream for a display module, wherein the pixel degradation compensation circuit generates a current degradation value corresponding to the current sub-pixel data based on the current sub-pixel data in the sub-pixel data stream, and the current degradation value represents the degradation effect of the current sub-pixel data on the sub-pixel corresponding to the current sub-pixel data in the display module, the pixel degradation compensation circuit selectively adjusts the current degradation value to generate an adjusted degradation value, the pixel degradation compensation circuit accumulates the adjusted degradation value to the total degradation value corresponding to the current sub-pixel data, and the pixel degradation compensation circuit compensates the current sub-pixel data based on the total degradation value corresponding to the current sub-pixel data to generate the compensated current sub-pixel data in the compensated sub-pixel data stream for the display module.

2. The processor according to claim 1, characterized in that The driving range of the display module is divided into an image area and a compensation area, each sub-pixel data in the sub-pixel data stream belongs to the image area, and the processing circuit remaps the original data stream to the sub-pixel data stream.

3. The processor according to claim 1, wherein: The operation of generating the adjusted degradation value comprises: The pixel degradation compensation circuit checks the margin of the total degradation value corresponding to each sub-pixel data in an image frame of the sub-pixel data stream in the total degradation value range to obtain a check result; The pixel degradation compensation circuit adjusts the accumulated acceleration weight corresponding to the current sub-pixel data based on the inspection result; and The pixel degradation compensation circuit adjusts the current degradation value based on the accumulated acceleration weight to generate the adjusted degradation value corresponding to the current sub-pixel data.

4. The processor according to claim 3, characterized in that In response to the checking result indicating that the margin of the total degradation value corresponding to any sub-pixel data in the image frame in the total degradation value range is greater than a first threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight to a first weight value; as well as In response to the inspection result indicating that the margin of the total degradation value corresponding to any sub-pixel data in the image frame in the total degradation value range is less than the first threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight to a second weight value less than the first weight value.

5. The processor according to claim 4, characterized in that The first weight value is 1, and the second weight value is a positive number less than 1.

6. The processor according to claim 4, characterized in that In response to the checking result indicating that the margin of the total degradation value corresponding to any sub-pixel data in the image frame in the total degradation value range is less than the first threshold and greater than a second threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight to the second weight value; as well as In response to the inspection result indicating that the margin of the total degradation value corresponding to any sub-pixel data in the image frame in the total degradation value range is less than the second threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight to a third weight value less than the second weight value.

7. The processor according to claim 4, characterized in that The same accumulated acceleration weight is applied to the degradation value corresponding to each sub-pixel data in the image frame.

8. The processor according to claim 3, characterized in that In response to the checking result indicating that the margin of the total degradation value corresponding to the current sub-pixel data in the total degradation value range is greater than a first threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight corresponding to the current sub-pixel data to a first weight value; as well as In response to the inspection result indicating that the margin of the total degradation value corresponding to the current sub-pixel data in the total degradation value range is less than the first threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight corresponding to the current sub-pixel data to a second weight value less than the first weight value.

9. The processor according to claim 8, characterized in that In response to the accumulated acceleration weight corresponding to the current sub-pixel data being adjusted to the second weight value, the accumulated acceleration weight corresponding to at least one neighboring sub-pixel data near the current sub-pixel data in the image frame is adjusted to a third weight value that is less than the first weight value and greater than the second weight value.

10. The processor according to claim 1, wherein: The operation of generating the compensated current sub-pixel data in the compensated sub-pixel data stream includes: The pixel degradation compensation circuit generates a compensation value based on the total degradation value corresponding to the current sub-pixel data; and The pixel degradation compensation circuit compensates the current sub-pixel data based on the compensation value to generate the compensated current sub-pixel data for the display module.

11. The processor according to claim 10, characterized in that The driving value range of the display module is divided into an image area and a compensation area, each sub-pixel data in the sub-pixel data stream belongs to the image area, and the operation of generating the adjusted degradation value includes: The pixel degradation compensation circuit checks the margin of the compensation value corresponding to each sub-pixel data in an image frame of the sub-pixel data stream in the compensation area to obtain a check result; The pixel degradation compensation circuit adjusts the accumulated acceleration weight corresponding to the current sub-pixel data based on the inspection result; and The pixel degradation compensation circuit adjusts the current degradation value based on the accumulated acceleration weight to generate the adjusted degradation value corresponding to the current sub-pixel data.

12. The processor according to claim 11, characterized in that In response to the checking result indicating that the margin of the compensation value corresponding to any sub-pixel data in the image frame in the compensation area is greater than a first threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight to a first weight value; as well as In response to the inspection result indicating that the margin of the compensation value corresponding to any sub-pixel data in the image frame in the compensation area is less than the first threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight to a second weight value less than the first weight value.

13. The processor according to claim 12, characterized in that The first weight value is 1, and the second weight value is a positive number less than 1.

14. The processor according to claim 12, characterized in that In response to the checking result indicating that the margin of the compensation value corresponding to any sub-pixel data in the image frame in the compensation area is less than the first threshold and greater than a second threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight to the second weight value; as well as In response to the inspection result indicating that the margin of the compensation value corresponding to any sub-pixel data in the image frame in the compensation area is less than the second threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight to a third weight value less than the second weight value.

15. The processor according to claim 12, wherein: The same accumulated acceleration weight is applied to the degradation value corresponding to each sub-pixel data in the image frame.

16. The processor according to claim 11, characterized in that In response to the checking result indicating that the margin of the compensation value corresponding to the current sub-pixel data in the compensation area is greater than a first threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight corresponding to the current sub-pixel data to a first weight value; as well as In response to the inspection result indicating that the margin of the compensation value corresponding to the current sub-pixel data in the compensation area is less than the first threshold, the pixel degradation compensation circuit adjusts the accumulated acceleration weight corresponding to the current sub-pixel data to a second weight value less than the first weight value.

17. The processor according to claim 16, characterized in that In response to the accumulated acceleration weight corresponding to the current sub-pixel data being adjusted to the second weight value, the accumulated acceleration weight corresponding to at least one neighboring sub-pixel data near the current sub-pixel data in the image frame is adjusted to a third weight value that is less than the first weight value and greater than the second weight value.

18. The processor according to claim 1, wherein: The processing circuit comprises: image processing circuit; and A remapping circuit is coupled to the image processing circuit to receive an original data stream, wherein the driving value range of the display module is divided into an image area and a compensation area, each sub-pixel data in the sub-pixel data stream belongs to the image area, and the remapping circuit remaps the original data stream to the sub-pixel data stream.

19. The processor according to claim 1, wherein: The pixel degradation compensation circuit comprises: a degradation value generating circuit, coupled to the processing circuit to receive the sub-pixel data stream, wherein the degradation value generating circuit generates the current degradation value corresponding to the current sub-pixel data based on the current sub-pixel data in the sub-pixel data stream; a multiplication circuit coupled to the degradation value generation circuit to receive the current degradation value, wherein the multiplication circuit adjusts the current degradation value based on an accumulated acceleration weight to generate the adjusted degradation value corresponding to the current sub-pixel data; a degradation value accumulation circuit, coupled to the multiplication circuit to receive the adjusted degradation value, wherein the degradation value accumulation circuit accumulates the adjusted degradation value corresponding to the current sub-pixel data to the total degradation value corresponding to the current sub-pixel data; an accumulated speed adjustment circuit coupled to the degradation value accumulation circuit to receive the total degradation value, wherein the accumulated speed adjustment circuit adjusts the accumulated speed weight to the multiplication circuit based on the total degradation value; a compensation value circuit coupled to the degradation value accumulation circuit to receive the total degradation value, wherein the compensation value circuit generates a compensation value corresponding to the current sub-pixel data based on the total degradation value; and A compensation circuit is coupled to the processing circuit to receive the sub-pixel data stream, and is coupled to the compensation value circuit to receive the compensation value, wherein the compensation circuit compensates the current sub-pixel data based on the compensation value to generate the compensated current sub-pixel data for the display module.

20. The processor according to claim 1, wherein: The pixel degradation compensation circuit comprises: a degradation value generating circuit, coupled to the processing circuit to receive the sub-pixel data stream, wherein the degradation value generating circuit generates the current degradation value corresponding to the current sub-pixel data based on the current sub-pixel data in the sub-pixel data stream; a multiplication circuit coupled to the degradation value generation circuit to receive the current degradation value, wherein the multiplication circuit adjusts the current degradation value based on an accumulated acceleration weight to generate the adjusted degradation value corresponding to the current sub-pixel data; a degradation value accumulation circuit, coupled to the multiplication circuit to receive the adjusted degradation value, wherein the degradation value accumulation circuit accumulates the adjusted degradation value corresponding to the current sub-pixel data to the total degradation value corresponding to the current sub-pixel data; a compensation value circuit, coupled to the degradation value accumulation circuit to receive the total degradation value, wherein the compensation value circuit generates a compensation value corresponding to the current sub-pixel data based on the total degradation value; an accumulated acceleration adjustment circuit coupled to the compensation value circuit to receive the compensation value, wherein the accumulated acceleration adjustment circuit adjusts the accumulated acceleration weight to the multiplication circuit based on the compensation value; and A compensation circuit is coupled to the processing circuit to receive the sub-pixel data stream, and is coupled to the compensation value circuit to receive the compensation value, wherein the compensation circuit compensates the current sub-pixel data based on the compensation value to generate the compensated current sub-pixel data for the display module.

21. A pixel degradation compensation method, characterized in that: The pixel degradation compensation method comprises: Generating a current degradation value corresponding to the current sub-pixel data based on the current sub-pixel data in the sub-pixel data stream, wherein the current degradation value indicates the degradation effect of the current sub-pixel data on the sub-pixel corresponding to the current sub-pixel data in the display module; selectively adjusting the current degradation value to generate an adjusted degradation value; Adding the adjusted degradation value to the total degradation value corresponding to the current sub-pixel data; and The current sub-pixel data is compensated based on the total degradation value corresponding to the current sub-pixel data to generate compensated current sub-pixel data in a compensated sub-pixel data stream for the display module.

22. The pixel degradation compensation method according to claim 21, characterized in that: The driving range of the display module is divided into an image area and a compensation area, each sub-pixel data in the sub-pixel data stream belongs to the image area, and the pixel degradation compensation method further includes: The original data stream is remapped to the sub-pixel data stream.

23. The pixel degradation compensation method according to claim 21, characterized in that: The operation of generating the adjusted degradation value comprises: Checking a margin of the total degradation value corresponding to each sub-pixel data in an image frame of the sub-pixel data stream in a total degradation value range to obtain a check result; Adjusting the accumulated acceleration weight corresponding to the current sub-pixel data based on the checking result; and The current degradation value is adjusted based on the accumulated acceleration weight to generate the adjusted degradation value corresponding to the current sub-pixel data.

24. The pixel degradation compensation method according to claim 23, characterized in that: The pixel degradation compensation method further includes: In response to the checking result indicating that the margin of the total degradation value corresponding to any sub-pixel data in the image frame in the total degradation value range is greater than a first threshold, adjusting the accumulated acceleration weight to a first weight value; and In response to the checking result indicating that the margin of the total degradation value corresponding to any sub-pixel data in the image frame in the total degradation value range is smaller than the first threshold, the accumulated acceleration weight is adjusted to a second weight value smaller than the first weight value.

25. The pixel degradation compensation method according to claim 24, characterized in that: The first weight value is 1, and the second weight value is a positive number less than 1.

26. The pixel degradation compensation method according to claim 24, characterized in that: The pixel degradation compensation method further includes: In response to the checking result indicating that the margin of the total degradation value corresponding to any sub-pixel data in the image frame in the total degradation value range is less than the first threshold and greater than a second threshold, adjusting the accumulated acceleration weight to the second weight value; and In response to the checking result indicating that the margin of the total degradation value corresponding to any sub-pixel data in the image frame in the total degradation value range is smaller than the second threshold, the accumulated acceleration weight is adjusted to a third weight value smaller than the second weight value.

27. The pixel degradation compensation method according to claim 24, characterized in that: The same accumulated acceleration weight is applied to the degradation value corresponding to each sub-pixel data in the image frame.

28. The pixel degradation compensation method according to claim 23, characterized in that: The pixel degradation compensation method further includes: In response to the checking result indicating that the margin of the total degradation value corresponding to the current sub-pixel data in the total degradation value range is greater than a first threshold, adjusting the accumulated acceleration weight corresponding to the current sub-pixel data to a first weight value; and In response to the inspection result indicating that the margin of the total degradation value corresponding to the current sub-pixel data in the total degradation value range is less than the first threshold, the accumulated acceleration weight corresponding to the current sub-pixel data is adjusted to a second weight value less than the first weight value.

29. The pixel degradation compensation method according to claim 28, characterized in that: The pixel degradation compensation method further includes: In response to the accumulated acceleration weight corresponding to the current sub-pixel data being adjusted to the second weight value, the accumulated acceleration weight corresponding to at least one neighboring sub-pixel data near the current sub-pixel data in the image frame is adjusted to a third weight value that is smaller than the first weight value and larger than the second weight value.

30. The pixel degradation compensation method according to claim 21, characterized in that: The operation of generating the compensated current sub-pixel data in the compensated sub-pixel data stream includes: generating a compensation value based on the total degradation value corresponding to the current sub-pixel data; and The current sub-pixel data is compensated based on the compensation value to generate the compensated current sub-pixel data for the display module.

31. The pixel degradation compensation method according to claim 30, characterized in that: The driving value range of the display module is divided into an image area and a compensation area, each sub-pixel data in the sub-pixel data stream belongs to the image area, and the operation of generating the adjusted degradation value includes: Checking a margin of the compensation value corresponding to each sub-pixel data in an image frame of the sub-pixel data stream in the compensation area to obtain a check result; Adjusting the accumulated acceleration weight corresponding to the current sub-pixel data based on the checking result; and The current degradation value is adjusted based on the accumulated acceleration weight to generate the adjusted degradation value corresponding to the current sub-pixel data.

32. The pixel degradation compensation method according to claim 31, characterized in that: The pixel degradation compensation method further includes: In response to the checking result indicating that the margin of the compensation value corresponding to any sub-pixel data in the image frame in the compensation area is greater than a first threshold, adjusting the accumulated acceleration weight to a first weight value; and In response to the checking result indicating that the margin of the compensation value corresponding to any sub-pixel data in the image frame in the compensation area is smaller than the first threshold, the accumulated acceleration weight is adjusted to a second weight value smaller than the first weight value.

33. The pixel degradation compensation method according to claim 32, characterized in that: The first weight value is 1, and the second weight value is a positive number less than 1.

34. The pixel degradation compensation method according to claim 32, characterized in that: The pixel degradation compensation method further includes: In response to the checking result indicating that the margin of the compensation value corresponding to any sub-pixel data in the image frame in the compensation area is less than the first threshold and greater than a second threshold, adjusting the accumulated acceleration weight to the second weight value; and In response to the checking result indicating that the margin of the compensation value corresponding to any sub-pixel data in the image frame in the compensation area is smaller than the second threshold, the accumulated acceleration weight is adjusted to a third weight value smaller than the second weight value.

35. The pixel degradation compensation method according to claim 32, characterized in that: The same accumulated acceleration weight is applied to the degradation value corresponding to each sub-pixel data in the image frame.

36. The pixel degradation compensation method according to claim 31, characterized in that: The pixel degradation compensation method further includes: In response to the checking result indicating that the margin of the compensation value corresponding to the current sub-pixel data in the compensation area is greater than a first threshold, adjusting the accumulated acceleration weight corresponding to the current sub-pixel data to a first weight value; and In response to the checking result indicating that the margin of the compensation value corresponding to the current sub-pixel data in the compensation area is smaller than the first threshold, the accumulated acceleration weight corresponding to the current sub-pixel data is adjusted to a second weight value smaller than the first weight value.

37. The pixel degradation compensation method according to claim 36, characterized in that: The pixel degradation compensation method further includes: In response to the accumulated acceleration weight corresponding to the current sub-pixel data being adjusted to the second weight value, the accumulated acceleration weight corresponding to at least one neighboring sub-pixel data near the current sub-pixel data in the image frame is adjusted to a third weight value that is smaller than the first weight value and larger than the second weight value.

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