Phase interpolator

Abstract

The invention discloses a phase interpolator. In order to improve linearity, a core circuit of the phase interpolator is characterized in that a device working voltage is connected to a first end of a fifth PMOS tube, a second end of the fifth PMOS tube is connected with a first end of a first resistor, a second end of the first resistor is connected with a first node, a first end of a second resistor is connected to the device working voltage, and a second end of the second resistor is connected with the first node. The grid electrode of the fifth PMOS tube is connected with an anti-phase starting signal; the second node is connected to the first end of a third resistor, the second end of the third resistor is grounded, the second node is further connected to the first end of a fourth resistor, the second end of the fourth resistor is connected to the first end of a fifth NMOS tube, the second end of the fifth NMOS tube is grounded, and a starting signal is connected to the grid electrode of the fifth NMOS tube; a first circuit is connected between a first node and a second node, and the first circuit receives a first input clock and a second input clock and outputs a core clock. The invention has the advantages of low jitter, high linearity and low duty cycle distortion.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a phase interpolator. Background Art

[0002] As a key integrated circuit component, the Register Clock Driver (RCD) chip provides the necessary buffering and enhancement for the address signals, command signals, and control signals from the memory controller. This process ensures that the signal maintains a high degree of integrity and timeliness during transmission to the Dynamic Random Access Memory (DRAM) particles, effectively avoiding signal attenuation and distortion, especially in high-density memory configurations. Complementing this is the Data Buffer (DB) chip, whose main responsibility is to relay and buffer the data signal flow from the memory controller to the DRAM or vice versa, further enhancing the reliability and efficiency of data transmission.

[0003] The combination of RCD and DB chips constitutes a collaborative chip system that fully implements full buffering of all key signals in memory operations, including address, command, control signals and data signals. This design not only optimizes signal integrity, but also significantly improves the overall performance and stability of the memory system.

[0004] In actual applications, if the memory module only integrates the RCD chip, the module is specifically called a Registered Dual In-line Memory Module (RDIMM). RDIMM is particularly suitable for server and workstation environments that require high-capacity memory configurations by increasing signal strength to reduce signal conflicts and improve system compatibility.

[0005] When the memory module integrates both RCD and DB chips, it is called Load Reduced Dual In-line Memory Module (LRDIMM). The design concept of LRDIMM is to effectively reduce the load of the memory bus through the DB chip, so that the system can support more DRAM components to run simultaneously without worrying about signal interference or power supply bottlenecks. This is a crucial technological advancement for high-performance computing platforms that pursue extreme memory expansion capabilities and reduce system energy consumption.

[0006] Figure 1It is the core circuit diagram of the traditional phase interpolator (PI). It includes P-channel Metal Oxide Semiconductor (PMOS) tubes P1, PMOS tubes P2, PMOS tubes P3 and PMOS tubes P4, and N-channel Metal Oxide Semiconductor (NMOS) tubes N1, NMOS tubes N2, NMOS tubes N3 and NMOS tubes N4. The input is the first input clock CLK_IN1 and the second input clock CLK_IN2, and the selection signal SEL and inverting the select signal Under the control of , the clock signal CLK_OUT is output.

[0007] The disadvantages of the traditional core circuit are high power consumption and narrow coverage, resulting in poor linearity. In addition, the buffer after the core circuit uses a DC buffer, which eventually distorts the duty cycle of the output clock. Summary of the invention

[0008] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows: A phase interpolator comprises a core circuit and a buffer, wherein the core circuit receives a first input clock and a second input clock, and outputs a core clock to the buffer; the output end of the buffer leads to an output clock; and the core circuit has the following circuit connection relationship: a device operating voltage is connected to the first end of a fifth PMOS tube, the second end of the fifth PMOS tube is connected to the first end of a first resistor, the second end of the first resistor is connected to a first node, the first end of the second resistor is connected to the device operating voltage, the second end of the second resistor is connected to the first node, and the gate of the fifth PMOS tube is connected to an inverted enable signal; the second node is connected to the first end of a third resistor, the second end of the third resistor is grounded, the second node is also connected to the first end of a fourth resistor, the second end of the fourth resistor is connected to the first end of a fifth NMOS tube, the second end of the fifth NMOS tube is grounded, and the gate of the fifth NMOS tube is connected to an enable signal; and a first circuit is connected between the first node and the second node, the first circuit receives the first input clock and the second input clock, and outputs a core clock.

[0009] Furthermore, the buffer is an AC buffer.

[0010] Furthermore, the input of the buffer is a core clock; the core clock is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the inverter and the first end of the buffer resistor, the second end of the buffer resistor is connected to the first end of the transmission gate, the second end of the transmission gate is connected to the output end of the inverter, and the output end of the inverter leads to the output clock.

[0011] Furthermore, the first circuit has the following circuit connection relationship: the first end of the first PMOS tube is connected to the first node, the second end of the first PMOS tube is connected to the first end of the third PMOS tube, the second end of the third PMOS tube is connected to the output node, the output node is connected to the first end of the first NMOS tube, the second end of the first NMOS tube is connected to the first end of the third NMOS tube, and the second end of the third NMOS tube is connected to the second node.

[0012] Furthermore, the first circuit has the following circuit connection relationship: the gate of the third NMOS tube and the gate of the first PMOS tube are commonly connected to the second input clock; the selection signal is connected to the gate of the first NMOS tube, and the inverted selection signal is connected to the gate of the third PMOS tube.

[0013] Furthermore, the first circuit has the following circuit connection relationship: the first end of the second PMOS tube is connected to the first node, the second end of the second PMOS tube is connected to the first end of the fourth PMOS tube, the second end of the fourth PMOS tube is connected to the output node, the output node is connected to the first end of the second NMOS tube, the second end of the second NMOS tube is connected to the first end of the fourth NMOS tube, and the second end of the fourth NMOS tube is connected to the second node.

[0014] Furthermore, the gate of the fourth NMOS tube and the gate of the second PMOS tube are commonly connected to the first input clock; the selection signal is connected to the gate of the fourth PMOS tube, and the inverted selection signal is connected to the gate of the second NMOS tube.

[0015] Furthermore, the output node outputs a core clock.

[0016] Furthermore, the phase interpolator includes a plurality of core circuits, and each core circuit is powered by a separate LDO power tube.

[0017] The technical solution of the present invention has the following beneficial technical effects: The present invention can be applied to the clock signal transmission path of the 5th generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) protocol. By achieving a combination of high linearity and low energy consumption, the clock jitter phenomenon inside the chip is significantly reduced, and the duty cycle distortion is reduced, ensuring the continuous stability and high reliability of the output data stream.

[0018] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is the core circuit diagram of the traditional phase interpolator; Figure 2 It is the block diagram of the phase interpolator; Figure 3 It is a signal logic schematic diagram of the present invention; Figure 4 It is the core circuit diagram of the phase interpolator of the present invention; Figure 5 is a system block diagram of the phase interpolator of the present invention; Figure 6 1 is a circuit diagram of a buffer according to the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0022] Figure 2 The reference clock is the input of the clock phase mixing module, and the reference clock can be the output clock from the phase-locked loop.

[0023] According to the reference clock, the clock phase mixing module outputs multiple clocks with different phases. For example, the clock phase mixing module outputs 8 clocks with different phases, and the phase difference between adjacent clocks is 45°. Then, through a multiplexer, specifically, an eight-to-two multiplexer, two adjacent clocks are selected as input signals of the core circuit.

[0024] Then, the multiplexer and the core circuit are controlled respectively through the thermometer code, and finally the core clock is output.

[0025] Figure 3 It is a signal logic schematic diagram of the present invention. In the figure, VDD is the device operating voltage (Voltage Drain-to-Drain, VDD), and T is the time.

[0026] The inventors have found through analysis that the factors affecting the linearity t1 of the phase interpolator are mainly: the phase difference between the two input clocks and the short-circuit time of the input clock and the slope of the core clock x .

[0027] Specifically, when the instantaneous current flowing through the phase interpolator is I 1. The average current consumed is I 2. The parasitic capacitance of the phase interpolator is CL , then the slope of the core clock x satisfy: .

[0028] The slope of the core clock x The smaller it is, the better the linearity of the core clock. Indicates a very short time interval. The present invention considers improving the linearity of the core clock from the perspective of the device operating voltage.

[0029] Figure 4 It is the core circuit diagram of the phase interpolator of the present invention. By adding the first resistor R1, the first resistor R2, the first resistor R3 and the first resistor R4, VDD and ground both ends by limiting access VDD The amplitude of the core clock is reduced by x , to improve linearity and reduce jitter, wherein the resistance of the first resistor R1 is equal to the resistance of the second resistor R2.

[0030] In the core circuit of the phase interpolator, the device operating voltage is connected to the first end of the fifth PMOS tube P5, the second end of the fifth PMOS tube P5 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the first node. In addition, the first end of the second resistor R2 is connected to the device operating voltage, and the second end of the second resistor R2 is connected to the first node. The gate of the fifth PMOS tube P5 is connected to the inverting enable signal.

[0031] A first end of the first PMOS tube P1 is connected to a first node, a second end of the first PMOS tube P1 is connected to a first end of a third PMOS tube P3, a second end of the third PMOS tube P3 is connected to an output node, the output node is connected to a first end of the first NMOS tube N1, a second end of the first NMOS tube N1 is connected to a first end of the third NMOS tube N3, and a second end of the third NMOS tube N3 is connected to a second node.

[0032] In addition, the gate of the third NMOS transistor N3 and the gate of the first PMOS transistor P1 are commonly connected to the second input clock CLK_IN2. SEL Connect to the gate of the first NMOS tube N1, invert the selection signal Connected to the gate of the third PMOS tube P3.

[0033] A first end of the second PMOS tube P2 is connected to the first node, a second end of the second PMOS tube P2 is connected to a first end of the fourth PMOS tube P4, a second end of the fourth PMOS tube P4 is connected to an output node, the output node is connected to a first end of the second NMOS tube N2, a second end of the second NMOS tube N2 is connected to a first end of the fourth NMOS tube N4, and a second end of the fourth NMOS tube N4 is connected to the second node.

[0034] In addition, the gate of the fourth NMOS transistor N4 and the gate of the second PMOS transistor P2 are commonly connected to the first input clock CLK_IN1. SEL Connect to the gate of the fourth PMOS tube P4, invert the selection signal Connected to the gate of the second NMOS tube N2.

[0035] The output node outputs a core clock.

[0036] In the present invention, the circuit between the first node and the second node is a first circuit, and the first circuit receives a first input clock CLK_IN1 and a second input clock CLK_IN2 and outputs a core clock.

[0037] Further, the second node is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is grounded. The second node is also connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the first end of the fifth NMOS transistor N5, and the second end of the fifth NMOS transistor N5 is grounded. The gate of the fifth NMOS transistor N5 is connected to the enable signal.

[0038] In the present invention, the enable signal and the inverted enable signal are respectively used to control switches of different lines, in order to cover different frequencies, such as 1.4 GHz to 3.2 GHz.

[0039] In addition, the solution of adding resistance has the following advantages: to cause the same change in output current, the input change amplitude needs to be larger than the gate-source voltage, and the larger the negative feedback resistance, the more obvious this phenomenon is. Therefore, compared with the transconductance of the common-gate amplifier, the equivalent transconductance of the common-gate pair with source negative feedback is reduced, and the equivalent transconductance of the common-gate pair with source negative feedback decreases as the negative feedback resistance increases, which can reduce jitter.

[0040] Figure 5 The system block diagram of the phase interpolator of the present invention is shown in FIG. The VDD of the phase interpolator can be provided by a low dropout linear regulator (LDO). The core circuit is Figure 4The core circuit shown in FIG. 1 outputs a core clock.

[0041] The logic control circuit is common technical knowledge in this field, and generally includes a decoder, etc. The present invention is not limited to a specific form. The core clock is generally also affected by the parasitic capacitor C0, and the core clock is finally used as the input of the buffer, and the buffer outputs the output clock.

[0042] A general phase interpolator includes several core circuits, such as eight core circuits, which receive the thermometer code output by the logic control circuit. The outputs of the several core circuits are connected together to output a core clock.

[0043] Preferably, in order to stably supply power to the core circuit, an LDO power tube is allocated to each core circuit to improve the power supply capacity and ensure system stability.

[0044] Furthermore, the selection signal SEL It is a bit in the thermometer code output by the logic control circuit.

[0045] Figure 6 : is a circuit diagram of a buffer of the present invention. The input of the buffer is a core clock, the core clock is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the first end of the inverter and the first end of the buffer resistor, the second end of the buffer resistor is connected to the first end of the transmission gate, the second end of the transmission gate is connected to the output end of the inverter, and the output end of the inverter leads to the output clock. In other words, the output end of the buffer leads to the output clock.

[0046] Due to the use of an AC type buffer, the present invention can have smaller duty cycle distortion compared to a conventionally used DC type buffer.

[0047] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0048] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A phase interpolator, comprising a core circuit and a buffer, characterized in that: The core circuit receives a first input clock and a second input clock, and outputs a core clock to the buffer; The output end of the buffer leads to an output clock; and, The core circuit has the following circuit connection relationship: The device operating voltage is connected to the first end of the fifth PMOS tube, the second end of the fifth PMOS tube is connected to the first end of the first resistor, the second end of the first resistor is connected to the first node, the first end of the second resistor is connected to the device operating voltage, the second end of the second resistor is connected to the first node, and the gate of the fifth PMOS tube is connected to the inverted enable signal; The second node is connected to the first end of the third resistor, the second end of the third resistor is grounded, the second node is also connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the fifth NMOS transistor, the second end of the fifth NMOS transistor is grounded, and the gate of the fifth NMOS transistor is connected to the enable signal; as well as, A first circuit is connected between the first node and the second node, and the first circuit receives a first input clock and a second input clock and outputs a core clock.

2. The phase interpolator according to claim 1, characterized in that: The buffer is an AC type buffer.

3. The phase interpolator according to claim 2, characterized in that: The input of the buffer is a core clock; The core clock is connected to the first end of the first capacitor, the second end of the first capacitor is connected to the first end of the inverter and the first end of the buffer resistor, the second end of the buffer resistor is connected to the first end of the transmission gate, the second end of the transmission gate is connected to the output end of the inverter, and the output end of the inverter leads to the output clock.

4. The phase interpolator according to claim 3, characterized in that: The first circuit has the following circuit connection relationship: The first end of the first PMOS tube is connected to the first node, the second end of the first PMOS tube is connected to the first end of the third PMOS tube, the second end of the third PMOS tube is connected to the output node, the output node is connected to the first end of the first NMOS tube, the second end of the first NMOS tube is connected to the first end of the third NMOS tube, and the second end of the third NMOS tube is connected to the second node.

5. The phase interpolator according to claim 4, characterized in that: The first circuit has the following circuit connection relationship: The gate of the third NMOS tube and the gate of the first PMOS tube are commonly connected to the second input clock; The selection signal is connected to the gate of the first NMOS tube, and the inverted selection signal is connected to the gate of the third PMOS tube.

6. The phase interpolator according to claim 5, characterized in that: The first circuit has the following circuit connection relationship: The first end of the second PMOS tube is connected to the first node, the second end of the second PMOS tube is connected to the first end of the fourth PMOS tube, the second end of the fourth PMOS tube is connected to the output node, the output node is connected to the first end of the second NMOS tube, the second end of the second NMOS tube is connected to the first end of the fourth NMOS tube, and the second end of the fourth NMOS tube is connected to the second node.

7. The phase interpolator according to claim 6, characterized in that: The gate of the fourth NMOS tube and the gate of the second PMOS tube are commonly connected to the first input clock; The selection signal is connected to the gate of the fourth PMOS tube, and the inverted selection signal is connected to the gate of the second NMOS tube.

8. The phase interpolator according to claim 7, characterized in that: The output node outputs a core clock.

9. The phase interpolator according to claim 8, characterized in that: The phase interpolator includes multiple core circuits, and each core circuit is powered by a separate LDO power tube.

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