Chip spacing control method and device based on membrane rupture

Abstract

The invention relates to the technical field of chip transfer packaging, and provides a chip spacing control method and device based on film rupture, and the method comprises the steps: S1, generating a first position matrix, and constructing a target matrix of a chip according to the first position matrix; s2, constructing a first deformation vector set of the chip; s3, generating a second deformation vector set, and obtaining a unit deformation vector, corresponding to the pinhole, of each chip according to a quadratic spline interpolation method and the second deformation vector set; s4, iterating the objective function, and adjusting pinhole coordinates when the objective function is iterated; s5, adjusting the number of pinholes, comparing the number of pinholes with the number of chips, determining to adjust the target matrix according to a comparison result, and skipping to the step S2 or executing the step S6; and S6, controlling a needle head to puncture the back membrane based on the adjusted needle hole coordinates. According to the invention, the chip spacing is optimized to solve the problems of non-uniform chip spacing after wafer expansion and low transfer precision in the subsequent transfer process.

Description

Technical Field

[0001] The present invention relates to the technical field of chip transfer packaging, and in particular to a chip spacing control method and device based on film breaking. Background Art

[0002] In daily operations, after the wafer is cut, the chip spacing is still very small. In order to facilitate subsequent processes, it is necessary to stretch the blue film or UV film on the back to disperse the chips. This process is called crystal expansion. Existing crystal expansion machines use a liftable and heatable top film platform to first preheat the back film (blue film or UV film) to soften it, then stretch the back film and fix the crystal expansion ring to complete the crystal expansion. However, due to uneven heating of the back film and uneven distribution of film stress during the rise of the top film platform, the chip spacing is uneven after crystal expansion, and the transfer accuracy of the subsequent transfer process is reduced.

[0003] Therefore, there is an urgent need for a method to adjust the chip distribution on the wafer expansion ring to solve the problem of uneven chip spacing after wafer expansion and reduced transfer accuracy in subsequent transfer processes. Summary of the invention

[0004] In view of the above-mentioned defects, the purpose of the present invention is to propose a chip spacing control method and device based on film breaking, aiming to optimize the chip spacing to solve the problems of uneven chip spacing after crystal expansion and low transfer accuracy in subsequent transfer processes.

[0005] To achieve this object, the present invention adopts the following technical solutions:

[0006] A chip spacing control method based on film breaking, the chip spacing control method comprising the steps of:

[0007] S1: Generate a first position matrix based on the position coordinates of each chip before membrane rupture, and construct a target matrix of the chip according to the first position matrix;

[0008] S2: constructing a first deformation vector set of the chip according to the first position matrix and the target matrix;

[0009] S3: generating a second deformation vector set based on the position coordinates of each chip after the membrane is broken and the first position matrix, and obtaining a unit deformation vector corresponding to each chip and the pinhole according to the quadratic spline interpolation method and the second deformation vector set;

[0010] S4: iterating the objective function based on all the unit deformation vectors and the first deformation vector set, and adjusting the pinhole coordinates when iterating the objective function;

[0011] S5: adjusting the number of pinholes based on the value of the objective function and the preset expected value, and comparing the number of pinholes with the number of chips, determining to adjust the target matrix according to the comparison result and jumping to step S2 or executing step S6;

[0012] S6: Based on the adjusted pinhole coordinates, the needle is controlled to pierce the back film.

[0013] Preferably, step S1 comprises:

[0014] Taking the center of the wafer expansion ring as the coordinate origin, calculate the position coordinates of each chip before breaking the film;

[0015] Marking the position coordinates of each chip to generate a first position matrix;

[0016] The average chip spacing in the X-axis direction and the Y-axis direction is calculated according to the first position matrix, and the coordinate origin is taken as the matrix center, and the target matrix of the chip is constructed according to the average chip spacing.

[0017] Furthermore, after step S3, it is also included to determine whether the needle needs to be replaced, including:

[0018] Obtain the deformation vector corresponding to the first chip on the X-axis in the second deformation vector set;

[0019] If the length corresponding to the deformation vector of the first chip on the X-axis is greater than the average chip spacing in the X-axis direction or the Y-axis direction, replace the wafer expansion ring and the needle with a smaller diameter, and start again from step S1;

[0020] If the length corresponding to the deformation vector of the first chip on the X-axis is smaller than the average chip spacing in the X-axis direction or the Y-axis direction and larger than one fifth of the average chip spacing in the X-axis direction or the Y-axis direction, execute step S4;

[0021] If the length corresponding to the deformation vector of the first chip on the X-axis is not greater than one-fifth of the average chip spacing in the X-axis direction or the Y-axis direction, replace the wafer expansion ring and the needle with a smaller diameter, and restart from step S1.

[0022] Preferably, the unit deformation vector corresponding to each chip and the pinhole is obtained according to the quadratic spline interpolation method and the second deformation vector set, including:

[0023] Obtain the position coordinates of each chip before membrane rupture and the deformation vector of each chip in the second deformation vector set, and use the quadratic spline interpolation method to calculate the coefficient of the spline in the interval between every two chips to satisfy the relationship:

[0024]

[0025] Where Δx bij represents the deformation vector of the chip in the i-th row and j-th column in the second deformation vector set, x 1ij represents the X-axis position coordinate of the chip in row i and column j before membrane rupture, a i 、b iand c i Represents the coefficient of the spline in every two-chip interval.

[0026] Furthermore, the unit deformation vector corresponding to each chip and the pinhole obtained according to the quadratic spline interpolation method and the second deformation vector set also includes:

[0027] Get the distance between the chip and the pinhole;

[0028] The displacement of the chip after the film is broken is calculated based on the coefficient of the spline in each interval between two chips and the distance between the chip and the pinhole, satisfying the relationship:

[0029] Δx=a i d 2 +b i d+c i ;

[0030] Among them, Δx represents the displacement of the chip after the membrane is broken, a i 、b i and c i represents the coefficient of the spline in the interval between every two chips, and d represents the distance between the chip and the pinhole;

[0031] The displacement of the chip after the membrane is broken and the direction of the pinhole pointing to the chip form a unit deformation vector.

[0032] Preferably, based on all unit deformation vectors and the first deformation vector set, optimizing the pinhole coordinates while iterating a preset objective function comprises:

[0033] All unit deformation vectors are superimposed to obtain the total deformation vector;

[0034] The average distance between all chips and the target matrix is ​​calculated based on the total deformation vector and the first deformation vector set, satisfying the relationship:

[0035]

[0036] Wherein, f represents the objective function, C represents the total deformation vector, n represents the number of chips, and ΔA represents the first deformation vector set;

[0037] Gradually adjust the coordinates of the pinhole until the objective function f no longer changes, and record the adjusted pinhole coordinates.

[0038] Preferably, in step S5, adjusting the number of pinholes based on the value of the objective function and the preset expected value includes:

[0039] Set expectations;

[0040] If the value of the objective function is not less than the expected value, the number of pinholes is increased;

[0041] If the value of the objective function is less than the expected value, the number of pinholes remains unchanged.

[0042] Further, comparing the number of pinholes with the number of chips, and determining to adjust the target matrix according to the comparison result and jumping to step S2 or executing step S6 include:

[0043] If the number of pinholes is less than one percent of the number of chips, execute step S6;

[0044] If the number of pinholes is not less than 1% of the number of chips, the chip spacing of the target matrix is ​​increased and the process starts again from step S2.

[0045] A chip spacing control device based on film breaking, comprising:

[0046] The visual module is used to obtain chip images and send them to the computing module;

[0047] A computing module is used to receive the chip image from the visual module, calculate the coordinates of all chips with the center of the wafer expansion ring as the coordinate origin, generate a first position matrix based on the position coordinates of each chip before film breaking, and construct a target matrix of the chip according to the first position coordinates;

[0048] Constructing a first deformation vector set of the chip according to the first position matrix and the target matrix;

[0049] Generate a second deformation vector set based on the position coordinates of each chip after the membrane is broken and the first position matrix, and obtain a unit deformation vector corresponding to each chip and the pinhole according to the quadratic spline interpolation method and the second deformation vector set;

[0050] Iterating the objective function based on all the unit deformation vectors and the first deformation vector set, and adjusting the pinhole coordinates when iterating the objective function;

[0051] The number of pinholes is adjusted based on the value of the objective function and the preset expected value, and the number of pinholes is compared with the number of chips, and the target matrix is ​​adjusted according to the comparison result and the subsequent steps are re-executed or the adjusted pinhole coordinates are sent to the mobile module;

[0052] The moving module is used to receive the pinhole coordinates sent by the computing module and control the needle to puncture the back film based on the adjusted pinhole coordinates.

[0053] One of the above technical solutions has the following advantages or beneficial effects:

[0054] The present invention adopts quadratic spline interpolation method to smooth the new position of the chip, which can capture the nonlinear characteristics of membrane deformation, improve the calculation accuracy of unit deformation vector, and help to achieve more accurate spacing control; by iteratively optimizing the objective function, the pinhole coordinates can be continuously adjusted to find the optimal puncture position, ensuring that the chip spacing can gradually approach the ideal state and reduce the error caused by static settings; based on the evaluation of the objective function, the number of pinholes can be flexibly adjusted to avoid the problem that the requirement of controlling the chip spacing cannot be met due to the number of pinholes or the solution time of the pinhole position is greatly extended, and too many pinholes may destroy the internal stress on the crystal expansion ring, resulting in changes in the overall mechanical properties of the crystal expansion ring and inability to be used in subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0056] Figure 1 is a flow chart of a chip spacing control method based on film breaking provided by an embodiment of the present invention;

[0057] Figure 2 is a schematic structural diagram of a chip spacing control device based on film breaking provided by an embodiment of the present invention;

[0058] Figure 3 1 is a schematic diagram of the structure of a device for applying the chip spacing control method based on film breaking provided by an embodiment of the present invention;

[0059] Among them, there are a wafer expansion ring platform 1, a visual module 2, a light source 21, an image acquisition unit 22, a calculation module 3, a moving module 4, a wafer expansion ring 5, a chip 51, a back film 52, and a needle 6. DETAILED DESCRIPTION

[0060] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0061] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0062] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0063] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0064] The present invention can be applied to a chip spacing control device, such as Figure 3 As shown, it includes a wafer expansion ring platform 1 for placing a wafer expansion ring 5 after film expansion, a visual module 2, a computing module 3 and a moving module 4;

[0065] The visual module 2 includes a light source 21 and an image acquisition unit 22, wherein the light source 21 is used to emit light that can be clearly reflected by the chip 51, and the image acquisition unit 22 is used to photograph the chip on the wafer, and is arranged above the wafer;

[0066] The calculation module 3 is connected to the visual module 2, and the calculation module 3 is used to calculate the coordinates of the chip 51 and control the moving module 4 to achieve the film breaking point;

[0067] The moving module 4 is used to realize camera shooting and needle 6 movement.

[0068] like Figure 1 As shown, a preferred embodiment of the present invention provides a chip spacing control method based on film breaking, and the chip spacing control method comprises the steps of:

[0069] S1: Generate a first position matrix based on the position coordinates of each chip before membrane rupture, and construct a target matrix of the chip according to the first position coordinates;

[0070] In this embodiment, the wafer expansion ring 5 is placed on the wafer expansion ring platform 1, the light source 21 is started, the wafer expansion ring 5 is photographed using the image acquisition unit 22, the image is transmitted to the computing module 3, and the actual position coordinates (x 1ij ,y 1ij ), where i represents the number of chip rows and j represents the number of chip columns. The actual position coordinates of all chips are marked as matrix A1. The first position matrix records the actual position of each chip before the membrane is broken. The target matrix sets the ideal position of the chip, aiming to minimize the interference between adjacent chips. Therefore, the target matrix is ​​calculated based on the ideal chip spacing and layout design. By setting the target spacing, the position of each chip in the target state can be calculated. Let the coordinates of each chip in the target matrix be (x 2ij ,y 2ij ).

[0071] S2: constructing a first deformation vector set of the chip according to the first position matrix and the target matrix;

[0072] The first deformation vector set is calculated by the difference between the first position matrix and the target matrix. Each deformation vector represents the offset between the actual position of the chip and its target position. The deformation vector (Δx ij , Δy ij ), the first deformation vector set is recorded as ΔA, and the deformation vector can help determine how the chip needs to be adjusted in actual operation to reach the target position.

[0073] S3: generating a second deformation vector set based on the position coordinates of each chip after the membrane is broken and the first position matrix, and obtaining a unit deformation vector corresponding to each chip and the pinhole according to the quadratic spline interpolation method and the second deformation vector set;

[0074] Send instructions to the mobile module 4 to control the needle 6 to fall at the coordinate origin and pierce the back film 52 (blue film or UV film). After the film is pierced, the chip moves due to the deformation of the film. The position coordinates of the chip after the film is pierced are recorded. Combined with the first position matrix, the deformation vector (Δx bij , Δy bij), and record the second set of deformation vectors as ΔB. The new position of the chip is smoothed using quadratic spline interpolation to calculate the unit deformation vector. Quadratic spline interpolation is a mathematical method used to construct a smooth curve between known data points, which can capture the nonlinear characteristics of membrane deformation. By interpolating the new position, the influence of the membrane on the chip position can be more accurately described.

[0075] S4: iterating the objective function based on all the unit deformation vectors and the first deformation vector set, and adjusting the pinhole coordinates when iterating the objective function;

[0076] First, an objective function needs to be defined to measure the difference between the deformation vector formed by all the pinholes acting together on each chip and the first deformation vector set. During the iteration process, the value of the objective function will become smaller and smaller. The smaller the value of the objective function, the closer the actual position of the chip is to the target position. This step optimizes the value of the objective function through an iterative algorithm and continuously adjusts the coordinates of the pinholes. Each iteration will be updated according to the current deformation vector and target position to find the optimal pinhole position, thereby achieving an ideal distribution of chips.

[0077] S5: adjusting the number of pinholes based on the value of the objective function and the preset expected value, and comparing the number of pinholes with the number of chips, determining to adjust the target matrix according to the comparison result and jumping to step S2 or executing step S6;

[0078] Subsequently, an expected value is set in combination with the subsequent process flow. The expected value is used to evaluate the current objective function value. If the objective function value fails to meet expectations, it needs to be adjusted by changing the number of pinholes. If the number of pinholes is too large, the time for solving the pinhole positions will be greatly prolonged, and too many pinholes may destroy the internal stress on the expansion ring 5, causing changes in the overall mechanical properties of the expansion ring 5, making it unusable for subsequent processes. Therefore, it is necessary to determine the adjustment of the target matrix based on the comparison results and jump to step S2 or execute step S6.

[0079] S6: Based on the adjusted pinhole coordinates, the needle is controlled to pierce the back film.

[0080] According to the adjusted pinhole coordinates, the movement path and puncture force of the needle are controlled. By precisely controlling the position and movement of the needle, the puncture process of the membrane can be ensured to be as uniform as possible, thereby reducing the inconsistency of chip spacing. Through effective puncture operations, the membrane can be deformed in a controllable manner, ultimately achieving the ideal arrangement of the chips on the carrier.

[0081] The present invention adopts the quadratic spline interpolation method to smooth the new chip position, which can capture the nonlinear characteristics of membrane deformation, improve the calculation accuracy of unit deformation vector, and help to achieve more accurate spacing control; by iteratively optimizing the objective function, the pinhole coordinates can be continuously adjusted to find the optimal puncture position, ensuring that the chip spacing can gradually approach the ideal state and reduce the error caused by static settings; based on the evaluation of the objective function, the number of pinholes can be flexibly adjusted to avoid the problem that the requirement of controlling the chip spacing cannot be met due to the number of pinholes or the solution time of the pinhole position is greatly extended, and too many pinholes may destroy the internal stress on the crystal expansion ring 5, resulting in changes in the overall mechanical properties of the crystal expansion ring 5 and inability to be used in subsequent processes.

[0082] Preferably, step S1 comprises:

[0083] Taking the center of the wafer expansion ring 5 as the coordinate origin, calculate the position coordinates of each chip before breaking the film;

[0084] Marking the position coordinates of each chip to generate a first position matrix;

[0085] The average chip spacing in the X-axis direction and the Y-axis direction is calculated according to the first position matrix, and the coordinate origin is taken as the matrix center, and the target matrix of the chip is constructed according to the average chip spacing.

[0086] Specifically, the center of the circle of the expansion ring 5 is defined as the coordinate origin (0,0). The expansion ring 5 is usually located at the center of the wafer, which can provide a stable reference point, making subsequent calculations and positioning more consistent. The image of the chip is obtained through the visual module 2, and the calculation module 3 calculates the coordinates of the chip. The coordinates of each chip recorded are recorded in the form of (x, y), indicating its distance relative to the origin. The position coordinates of all chips are organized into a matrix (first position matrix) for subsequent calculations and analysis. The x-coordinates and y-coordinates of all chips in the first position matrix are calculated respectively to obtain the average chip spacing on the X-axis and Y-axis. Then, with the coordinate origin as the center, a target matrix is ​​constructed according to the calculated average chip spacing. Each position in the target matrix represents the position where the chip should be in an ideal state. By calculating the average spacing, the accidental error of the position measurement of a single chip can be eliminated, and the chip spacing can be better controlled to make the chip spacing more uniform.

[0087] Furthermore, after step S3, it is also included to determine whether the needle needs to be replaced, including:

[0088] Obtain the deformation vector corresponding to the first chip on the X-axis in the second deformation vector set;

[0089] If the length corresponding to the deformation vector of the first chip on the X-axis is greater than the average chip spacing in the X-axis direction or the Y-axis direction, replace the wafer expansion ring 5 and replace the needle with a smaller diameter, and start again from step S1;

[0090] If the length corresponding to the deformation vector of the first chip on the X-axis is smaller than the average chip spacing in the X-axis direction or the Y-axis direction and larger than one fifth of the average chip spacing in the X-axis direction or the Y-axis direction, execute step S4;

[0091] If the length corresponding to the deformation vector of the first chip on the X-axis is not greater than one fifth of the average chip spacing in the X-axis direction or the Y-axis direction, replace the wafer expansion ring 5 and the needle with a smaller diameter, and restart from step S1.

[0092] Specifically, the deformation vector of the first chip on the x-axis in the second deformation vector set is Δx b11 , Δx b11 It is usually the maximum value in the second deformation vector set. If the length corresponding to the deformation vector of the first chip on the X-axis is greater than the average chip spacing in the X-axis direction or the Y-axis direction, it is considered that the diameter of the needle 6 is too large and the chip spacing cannot be controlled. The needle 6 with a smaller diameter should be replaced, the wafer expansion ring 5 should be replaced, and the execution should be restarted from step S1.

[0093] If the length corresponding to the deformation vector of the first chip on the X-axis is smaller than the average chip spacing in the X-axis direction or the Y-axis direction and larger than one fifth of the average chip spacing in the X-axis direction or the Y-axis direction, it is considered that the diameter of the needle is moderate, and the next step S4 can be executed;

[0094] If the length corresponding to the deformation vector of the first chip on the X-axis is not greater than one-fifth of the average chip spacing in the X-axis direction or the Y-axis direction, it is considered that the diameter of the needle 6 is too small, the number of pinholes required to control the chip spacing is too large, it is difficult to calculate the pinhole position and the calculation time is too long, and a needle 6 with a larger diameter should be replaced, the crystal expansion ring 5 should be replaced, and the execution should be restarted from step S1; by comparing the deformation vector with the average chip spacing, the suitability of the needle diameter can be accurately judged, thereby ensuring the accuracy and stability of chip processing, quickly identifying and replacing inappropriate needles and crystal expansion rings 5, and avoiding processing errors and time waste due to improper tools.

[0095] Preferably, the unit deformation vector corresponding to each chip and the pinhole is obtained according to the quadratic spline interpolation method and the second deformation vector set, including:

[0096] Obtain the position coordinates of each chip before membrane rupture and the deformation vector of each chip in the second deformation vector set, and use the quadratic spline interpolation method to calculate the coefficient of the spline in the interval between every two chips to satisfy the relationship:

[0097]

[0098] Where Δx bij represents the X-axis deformation vector of the chip in the i-th row and j-th column in the second deformation vector set, x 1ij represents the X-axis position coordinate of the chip in row i and column j before membrane rupture, a i 、b i and c i Represents the coefficient of the spline in every two-chip interval.

[0099] Specifically, since the film deformation after a single film break is usually expressed as a ray rotating about the pinhole, in the second deformation vector set ΔB, all the back film deformation vectors along the positive direction of the x-axis are taken as the starting point to construct a unit deformation vector, and Δx is taken from the deformation vectors of each chip on the x-axis. bij and x in the actual position coordinates before membrane rupture 1ij , using the equation The coefficients of the spline in the interval between every two chips are calculated, and the quadratic spline is fitted to the membrane rupture deformation vector in the positive direction of the x-axis. The unit deformation vector is the deformation field formed by rotating the quadratic spline around the pinhole position. Through interpolation, the smooth change of the deformation vector between chips is obtained to avoid mutation or discontinuity and ensure the physical meaning of the data.

[0100] Furthermore, the unit deformation vector corresponding to each chip and the pinhole obtained according to the quadratic spline interpolation method and the second deformation vector set also includes:

[0101] Get the distance between the chip and the pinhole;

[0102] The displacement of the chip after the film is broken is calculated based on the coefficient of the spline in each interval between two chips and the distance between the chip and the pinhole, satisfying the relationship:

[0103] Δx=a i d 2 +b i d+c i ;

[0104] Among them, Δx represents the displacement of the chip after the membrane is broken, a i 、b i and c i represents the coefficient of the spline in the interval between every two chips, and d represents the distance between the chip and the pinhole;

[0105] The displacement of the chip after the membrane is broken and the direction of the pinhole pointing to the chip form a unit deformation vector.

[0106] Specifically, the calculated displacement of the chip after membrane rupture is the length of a unit deformation vector. The unit deformation vector is defined as a vector with a certain magnitude in a specific direction, and its composition includes two parts: displacement information reflecting the degree of movement of the chip and direction information reflecting the deformation. The direction information is the direction in which the pinhole points to the chip. By substituting the value of the distance d, the corresponding displacement Δx can be obtained. A smooth displacement change can be generated between each chip, rather than a simple linear interpolation, thereby more realistically reflecting the actual deformation after membrane rupture.

[0107] Preferably, based on all unit deformation vectors and the first deformation vector set, optimizing the pinhole coordinates while iterating a preset objective function comprises:

[0108] All unit deformation vectors are superimposed to obtain the total deformation vector;

[0109] The average distance between all chips and the target matrix is ​​calculated based on the total deformation vector and the first deformation vector set, satisfying the relationship:

[0110]

[0111] Wherein, f represents the objective function, C represents the total deformation vector, n represents the number of chips, and ΔA represents the first deformation vector set;

[0112] Gradually adjust the coordinates of the pinhole until the objective function f no longer changes, and record the adjusted pinhole coordinates.

[0113] Specifically, the objective function f is used to measure the difference between the total deformation vector C formed by all the pinholes acting together on each chip and the first position matrix. The physical meaning of the objective function f is the average distance between all the chips and the target matrix. By superimposing all the unit deformation vectors, a comprehensive deformation state can be obtained to obtain the total deformation vector. By calculating the difference between the total deformation vector and the first position matrix, the deviation of the current chip position can be determined. The smaller the deviation of the chip position, the closer the current deformation is to the ideal state, and the smaller the value of the objective function f. When iterating the objective function, it is first initialized and the pinhole position is moved to a circle with the coordinate origin (the center of the expansion ring 5) as the center and the radius of the expansion ring 5 as the radius. Then 100 iterations are performed, and the pinhole coordinates are jumped while iterating. When the value of the objective function f remains unchanged, the pinhole coordinates at this time are recorded. This step can effectively find an optimal position by gradually adjusting the position of the pinhole and monitoring the changes in the objective function. The objective function will be recalculated after each adjustment until a convergence state is reached (that is, the value of the objective function changes slightly, indicating that it is close to the optimal solution).

[0114] Preferably, in step S5, adjusting the number of pinholes based on the value of the objective function and the preset expected value includes:

[0115] Set expectations;

[0116] If the value of the objective function is not less than the expected value, the number of pinholes is increased;

[0117] If the value of the objective function is less than the expected value, the number of pinholes remains unchanged.

[0118] Specifically, the expected value is set in combination with the subsequent process flow, and can be expressed as the maximum average distance between all chips and the target matrix that is acceptable. When the objective function value reaches or exceeds the expected value, the number of pinholes is increased to meet the requirement of controlling the chip spacing; otherwise, the current number of pinholes is maintained to prevent instability caused by over-adjustment. It is automatically optimized under different conditions to ensure its responsiveness and stability, while solving the problem of insufficient performance due to fixed parameters.

[0119] Further, comparing the number of pinholes with the number of chips, and determining to adjust the target matrix according to the comparison result and jumping to step S2 or executing step S6 include:

[0120] If the number of pinholes is less than one percent of the number of chips, execute step S6;

[0121] If the number of pinholes is not less than 1% of the number of chips, the chip spacing of the target matrix is ​​increased and the process starts again from step S2.

[0122] Specifically, if the number of pinholes is less than one percent of the number of chips, the number of pinholes is normal, and the next step S6 is executed. If the number of pinholes is not less than one percent of the number of chips, the number of pinholes is too large, which greatly prolongs the time for solving the pinhole positions, and too many pinholes may destroy the internal stress on the wafer expansion ring 5, causing the overall mechanical properties of the wafer expansion ring 5 to change and cannot be used for subsequent processes. In this embodiment, the spacing of the target matrix of chips can be adjusted from 0.40 mm to 0.41 mm, and then execution starts from step S2 to make the distribution of chips more uniform.

[0123] like Figure 2 As shown, another embodiment of the present invention is a chip spacing control device based on film breaking, comprising:

[0124] The visual module is used to obtain chip images and send them to the computing module;

[0125] A computing module is used to receive the chip image from the visual module, calculate the coordinates of all chips with the center of the wafer expansion ring as the coordinate origin, generate a first position matrix based on the position coordinates of each chip before film breaking, and construct a target matrix of the chip according to the first position coordinates;

[0126] Constructing a first deformation vector set of the chip according to the first position matrix and the target matrix;

[0127] Generate a second deformation vector set based on the position coordinates of each chip after the membrane is broken and the first position matrix, and obtain a unit deformation vector corresponding to each chip and the pinhole according to the quadratic spline interpolation method and the second deformation vector set;

[0128] Iterating the objective function based on all the unit deformation vectors and the first deformation vector set, and adjusting the pinhole coordinates when iterating the objective function;

[0129] The number of pinholes is adjusted based on the value of the objective function and the preset expected value, and the number of pinholes is compared with the number of chips, and the target matrix is ​​adjusted according to the comparison result and the subsequent steps are re-executed or the adjusted pinhole coordinates are sent to the mobile module;

[0130] The moving module is used to receive the pinhole coordinates sent by the computing module and control the needle to puncture the back film based on the adjusted pinhole coordinates.

[0131] Specifically, the chip spacing control device based on film breaking provided in this embodiment can also be implemented as follows: Figure 3 The chip spacing control device shown in the figure, the chip spacing control device based on film breaking provided in this embodiment realizes a chip spacing control method based on film breaking and an implementation process, please refer to the above embodiments, which will not be described one by one here.

[0132] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0133] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A chip spacing control method based on film breaking, characterized in that: The chip spacing control method comprises the steps of: S1: Generate a first position matrix based on the position coordinates of each chip before membrane rupture, and construct a target matrix of the chip according to the first position matrix; S2: constructing a first deformation vector set of the chip according to the first position matrix and the target matrix; S3: generating a second deformation vector set based on the position coordinates of each chip after the membrane is broken and the first position matrix, and obtaining a unit deformation vector corresponding to each chip and the pinhole according to the quadratic spline interpolation method and the second deformation vector set; S4: iterating the objective function based on all the unit deformation vectors and the first deformation vector set, and adjusting the pinhole coordinates when iterating the objective function; S5: adjusting the number of pinholes based on the value of the objective function and the preset expected value, and comparing the number of pinholes with the number of chips, determining to adjust the target matrix according to the comparison result and jumping to step S2 or executing step S6; S6: Based on the adjusted pinhole coordinates, the needle is controlled to pierce the back film.

2. The chip spacing control method according to claim 1, characterized in that: Step S1 includes: Taking the center of the wafer expansion ring as the coordinate origin, calculate the position coordinates of each chip before breaking the film; Marking the position coordinates of each chip to generate a first position matrix; The average chip spacing in the X-axis direction and the Y-axis direction is calculated according to the first position matrix, and the coordinate origin is taken as the matrix center, and the target matrix of the chip is constructed according to the average chip spacing.

3. The chip spacing control method according to claim 2, characterized in that: After step S3, it is also necessary to determine whether the needle needs to be replaced, including: Obtain the deformation vector corresponding to the first chip on the X-axis in the second deformation vector set; If the length corresponding to the deformation vector of the first chip on the X-axis is greater than the average chip spacing in the X-axis direction or the Y-axis direction, replace the wafer expansion ring and the needle with a smaller diameter, and start again from step S1; If the length corresponding to the deformation vector of the first chip on the X-axis is smaller than the average chip spacing in the X-axis direction or the Y-axis direction and larger than one fifth of the average chip spacing in the X-axis direction or the Y-axis direction, execute step S4; If the length corresponding to the deformation vector of the first chip on the X-axis is not greater than one-fifth of the average chip spacing in the X-axis direction or the Y-axis direction, replace the wafer expansion ring and the needle with a smaller diameter, and restart from step S1.

4. The chip spacing control method according to claim 1, characterized in that: According to the quadratic spline interpolation method and the second deformation vector set, the unit deformation vector corresponding to each chip and the pinhole includes: Obtain the position coordinates of each chip before membrane rupture and the deformation vector of each chip in the second deformation vector set, and use the quadratic spline interpolation method to calculate the coefficient of the spline in the interval between every two chips to satisfy the relationship: Where Δx bij represents the deformation vector of the chip in the i-th row and j-th column in the second deformation vector set, x 1ij represents the X-axis position coordinate of the chip in row i and column j before membrane rupture, a i 、b i and c i Represents the coefficient of the spline in every two-chip interval.

5. The chip spacing control method according to claim 4, characterized in that: The unit deformation vector corresponding to each chip and the pinhole obtained by the quadratic spline interpolation method and the second deformation vector set also includes: Get the distance between the chip and the pinhole; The displacement of the chip after the film is broken is calculated based on the coefficient of the spline in each interval between two chips and the distance between the chip and the pinhole, satisfying the relationship: Δx=a i d 2 +b i d+c i ; Among them, Δx represents the displacement of the chip after the membrane is broken, a i 、b i and c i represents the coefficient of the spline in the interval between every two chips, and d represents the distance between the chip and the pinhole; The displacement of the chip after the membrane is broken and the direction of the pinhole pointing to the chip form a unit deformation vector.

6. The chip spacing control method according to claim 1, characterized in that: Based on all the unit deformation vectors and the first deformation vector set, optimizing the pinhole coordinates while iterating the preset objective function includes: All unit deformation vectors are superimposed to obtain the total deformation vector; The average distance between all chips and the target matrix is ​​calculated based on the total deformation vector and the first deformation vector set, satisfying the relationship: Wherein, f represents the objective function, C represents the total deformation vector, n represents the number of chips, and ΔA represents the first deformation vector set; Gradually adjust the coordinates of the pinhole until the objective function f no longer changes, and record the adjusted pinhole coordinates.

7. The chip spacing control method according to claim 1, characterized in that: In step S5, adjusting the number of pinholes based on the value of the objective function and the preset expected value includes: Set expectations; If the value of the objective function is not less than the expected value, the number of pinholes is increased; If the value of the objective function is less than the expected value, the number of pinholes remains unchanged.

8. The chip spacing control method according to claim 7, characterized in that: Comparing the number of pinholes with the number of chips, and determining to adjust the target matrix according to the comparison result and jumping to step S2 or executing step S6 include: If the number of pinholes is less than one percent of the number of chips, execute step S6; If the number of pinholes is not less than 1% of the number of chips, the chip spacing of the target matrix is ​​increased and the process starts again from step S2.

9. A chip spacing control device based on film breaking, characterized in that: include: The visual module is used to obtain chip images and send them to the computing module; A computing module is used to receive the chip image from the visual module, calculate the coordinates of all chips with the center of the wafer expansion ring as the coordinate origin, generate a first position matrix based on the position coordinates of each chip before film breaking, and construct a target matrix of the chip according to the first position coordinates; Constructing a first deformation vector set of the chip according to the first position matrix and the target matrix; Generate a second deformation vector set based on the position coordinates of each chip after the membrane is broken and the first position matrix, and obtain a unit deformation vector corresponding to each chip and the pinhole according to the quadratic spline interpolation method and the second deformation vector set; Iterating the objective function based on all the unit deformation vectors and the first deformation vector set, and adjusting the pinhole coordinates when iterating the objective function; The number of pinholes is adjusted based on the value of the objective function and the preset expected value, and the number of pinholes is compared with the number of chips, and the target matrix is ​​adjusted according to the comparison result and the subsequent steps are re-executed or the adjusted pinhole coordinates are sent to the mobile module; The moving module is used to receive the pinhole coordinates sent by the computing module and control the needle to puncture the back film based on the adjusted pinhole coordinates.

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