Chip, chip stack package and electronic device

Abstract

The invention provides a chip, a chip stack package and an electronic device, relates to the technical field of through silicon vias, and can avoid the interference of a material difficult to etch on the fabrication of a through silicon via (TSV). The chip comprises a silicon substrate, a first etching stop layer, a first metal connecting disc, a second metal connecting disc, one or more first silicon through holes and one or more first vertical connecting structures. Wherein the first etching stop layer is located in the subsequent process. The first metal connecting disc is located above the first etching stop layer, the second metal connecting disc is located below the first etching stop layer, and the first metal connecting disc and the second metal connecting disc are connected through a plurality of first metal via holes penetrating through the first etching stop layer. One or more first silicon through holes penetrate through the silicon substrate and are connected with the first metal connecting disc. The one or more first vertical connection structures are electrically connected with the second metal connection disc and lead to the side far away from the silicon substrate.

Description

Technical Field

[0001] The present application relates to the technical field of through silicon vias, and in particular to a chip, a chip stacking package and an electronic device. Background Art

[0002] TSV (through silicon via) is an important part of advanced packaging technology. Due to the existence of TSV, it is possible to stack multiple chips in the vertical direction. The vertical communication between chips brings advantages such as high-density integration, high electrical properties, and multiple functional integration. Currently, more and more CPUs (central processing units), GPUs (graphics processing units) and memories are beginning to use TSV technology to meet the needs of high-performance computing, artificial intelligence, etc.

[0003] One of the key points of the TSV process is the through-hole formation process. TSV through-hole processing technology mainly uses dry etching to form high aspect ratio through-holes on the wafer. In order to smoothly carry out the TSV through-hole etching process, when designing the chip, the TSV area should be free of metal, high K (high dielectric constant), and ion implants to ensure the clearance of the TSV area. However, in advanced process manufacturing, some difficult-to-etch film layers such as AlN cannot achieve such a large area of ​​clearance in the TSV area using the current 2D (dimensional) process.

[0004] Therefore, when the clearance effect of the TSV area cannot be ensured, how to produce a reliable TSV structure under the interference of difficult-to-etch materials has become an urgent problem to be solved. Summary of the invention

[0005] The present application provides a chip, a chip stacking package and an electronic device, which can avoid the interference of difficult-to-etch materials on TSV and ensure the reliability of TSV.

[0006] The present application provides a chip, which includes a silicon substrate, a first etch stop layer, a first metal connection pad, a second metal connection pad, one or more first through silicon vias, and one or more first vertical connection structures. The first etch stop layer is located in a back-end process. The first metal connection pad is located below the first etch stop layer (on the side close to the silicon substrate), the second metal connection pad is located above the first etch stop layer (on the side away from the silicon substrate), and the first metal connection pad and the second metal connection pad are connected by multiple first metal vias that penetrate the first etch stop layer. One or more first through silicon vias penetrate the silicon substrate and are connected to the first metal connection pad. Multiple first vertical connection structures are located on the side of the second metal connection pad away from the through silicon vias, and one or more first vertical connection structures are electrically connected to the second metal connection pad and lead to the side away from the silicon substrate.

[0007] In the above chip, by respectively setting the first metal connection pad and the second metal connection pad above and below the first etch stop layer, and connecting the two metal connection pads through a plurality of first metal vias to form an intermediate connection structure, in this case, there is no need to perform large-area clearance of the first etch stop layer in the TSV region, and it is only necessary to divide the TSV into two sections, namely the first silicon through hole and the first vertical connection structure, and connect the first silicon through hole and the first vertical connection structure through the intermediate connection structure, thereby forming a new TSV structure that runs through the entire chip. In this way, the interference of the first etch stop layer in the production of TSV due to the inability to perform large-area clearance can be avoided, and the reliability of the TSV structure can also be guaranteed.

[0008] In some possible implementations, the first etch stop layer includes at least one of metal nitride and metal oxide.

[0009] In some possible implementations, the first etch stop layer includes AlN.

[0010] In some possible implementations, the chip includes: a first metal routing layer, a second metal routing layer, and a first via layer located in a back-end process, and the second metal routing layer is connected to the first metal routing layer through multiple vias in the first via layer. The first connection pad is arranged on the same layer as the first metal routing layer, and the second metal connection pad is arranged on the same layer as the second metal routing layer; and multiple first metal vias are arranged on the same layer as multiple vias in the first via layer. In this way, the first metal connection pad and the first metal routing layer are manufactured through the same manufacturing process, the second metal connection pad and the second metal routing layer are manufactured through the same manufacturing process, and the first metal via and the metal via in the first via layer are manufactured through the same manufacturing process, thereby achieving the purpose of simplifying the process, reducing the difficulty of manufacturing, and saving manufacturing costs.

[0011] In some possible implementations, the apertures of the plurality of first metal vias are the same as the apertures of the plurality of vias in the first via layer.

[0012] In some possible implementations, the first metal connection plate and the second metal connection plate are mesh structures.

[0013] In some possible implementations, the chip includes a plurality of metal routing layers in a back-end process, and the first metal routing layer is one of the plurality of metal routing layers that is closest to the silicon substrate.

[0014] In some possible implementations, the first vertical connection structure includes a metal via manufactured using a through-hole process.

[0015] In some possible implementations, the first vertical connection structure includes a metal via fabricated using a via last process.

[0016] In some possible implementations, the first through silicon via includes a through silicon via manufactured using a through silicon via process.

[0017] In some possible implementations, the first through silicon via includes a through silicon via manufactured using a through via last process.

[0018] In some possible implementations, the chip further includes: a second etch stop layer and a third metal connection pad. The second etch stop layer is located above the second metal connection pad (i.e., on a side away from the first etch stop layer); the third metal connection pad is located on a side of the second etch stop layer away from the second metal connection pad, and the third metal connection pad and the second metal connection pad are connected through a plurality of second metal vias penetrating the second etch stop layer; a plurality of first vertical connection structures are located above the third metal connection pad (i.e., on a side away from the silicon substrate), and the plurality of first vertical connection structures are connected to the third metal connection pad.

[0019] In some possible implementations, the chip further includes: a third etch stop layer and a fourth metal connection pad. The third etch stop layer is located on a side of the third metal connection pad away from the second etch stop layer. The fourth metal connection pad is located above the third etch stop layer (away from the side of the third metal connection pad), and the fourth metal connection pad and the third metal connection pad are connected through a plurality of third metal vias penetrating the third etch stop layer. A plurality of first vertical connection structures are located above the fourth metal connection pad (i.e., away from the side of the silicon substrate), and the plurality of first vertical connection structures are connected to the fourth metal connection pad.

[0020] In some possible implementations, the first vertical connection structure includes a second through silicon via, and the second through silicon via may be manufactured using a through silicon via process.

[0021] The present application also provides a chip stacking package, which includes a first chip and a second chip stacked in a stacked arrangement, wherein the first chip is a chip provided in any of the aforementioned possible implementation methods, and the first chip is electrically connected to the second chip via a first through silicon via or a first vertical connection structure.

[0022] The present application also provides an electronic device, which includes a circuit board and a chip stack package provided in any of the possible implementation methods described above, wherein the chip stack package is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of TSV in a chip provided in an embodiment of the present application;

[0025] Figure 3 for Figure 2 A partial enlarged schematic diagram of

[0026] Figure 4 A schematic diagram of the structure of a metal connection pad in a chip provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the structure of TSV in a chip provided in an embodiment of the present application;

[0028] Figure 6 for Figure 5 A partial enlarged schematic diagram of

[0029] Figure 7 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0030] Figure 8 A schematic diagram of the structure of TSV in a chip provided in an embodiment of the present application;

[0031] Fig. 9 for Figure 8 A partial enlarged schematic diagram of

[0032] Fig.10 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0033] Fig.11 A schematic diagram of a TSV manufacturing process in a chip provided in an embodiment of the present application;

[0034] Fig.12 A schematic diagram of a TSV manufacturing process in a chip provided in an embodiment of the present application;

[0035] Fig.13A schematic diagram of a TSV manufacturing process in a chip provided in an embodiment of the present application;

[0036] Fig.14 A schematic diagram of a TSV manufacturing process in a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or it can be indirect through an intermediate medium, or it can be the internal connection of two elements. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.

[0039] An embodiment of the present application provides an electronic device, which may be a headset, a mobile phone, a tablet computer, a personal computer (PC), etc. The present application does not limit the configuration form of the electronic device.

[0040] The electronic device is provided with a circuit board and a three-dimensional stacked chip package electrically connected to the circuit board. The three-dimensional stacked chip package includes a plurality of stacked chips, and the stacked plurality of chips are electrically interconnected in a vertical direction through TSV.

[0041] As shown, an embodiment of the present application provides a three-dimensional stacked chip package, which may include a first chip and a second chip, wherein the second chip is stacked above the first chip; wherein the first chip has a film layer formed of a difficult-to-etch material, such as an etch stop layer, and it is difficult for the existing process to etch the etch stop layer over such a large area as the TSV region. The present application adopts a new TSV structure in the first chip, thereby eliminating the need to etch the etch stop layer over a large area, avoiding the interference of the etch stop layer on the production of TSV, and also ensuring the reliability of the TSV structure.

[0042] First, the chip manufacturing process is briefly described.

[0043] Indicative, reference Figure 1 As shown, the chip manufacturing process includes the front end of line (FEOL) and the back end of line (BEOL). The active area (active area) of multiple transistors T is divided and prepared on the substrate through the front end process (FEOL), and then the source area S (source), drain area D (drain), and gate area G (gate) of each transistor T are completed in the active area. In other words, the front end process (FEOL) is to realize the manufacture of transistors on the substrate. Among them, the transistor T can be a fin field effect transistor (fin field effect transistor, FinFET), a gate-all-around field effect transistor (gate-all-around field effect transistor, GAA), etc., but is not limited to this.

[0044] The back-end process (BEOL) corresponding to the front-end process (FEOL) is to establish several metal routing layers (M1, M2, M3...), and adjacent metal routing layers are connected by metal vias (V1, V2, V3...).

[0045] A contact hole CT (contact) is provided in the front-end process (FEOL) and the back-end process (BEOL). The contact hole CT includes a metal via V0 and a contact metal M0 at the bottom. The contact hole CT is connected to the source region S, the drain region D or the gate region G of the transistor T through the contact metal M0, and is connected to the metal routing layer (M1) through the metal via V0.

[0046] As shown, in the back-end process (BEOL), the metal via V1 at the bottom needs to have a smaller aperture. In order to meet the process manufacturing requirements, before manufacturing the metal via V1, an etch stop layer ESL1 needs to be manufactured on the surface of the metal wiring layer M1 to meet the manufacturing requirements of the metal via V1. The etch stop layer can also be called an etch barrier layer, and its English name is etch stop layer.

[0047] It is understandable that the etch stop layer ESL1 is made of a material that is difficult to etch. With the current process level, it can be used to etch a small area of ​​the via region, but it is difficult to etch a large area of ​​the TSV region.

[0048] Taking the AlN layer as an example, when the etch stop layer ESL1 is formed, it is difficult to clear such a large area of ​​the AlN layer in the TSV region during TSV fabrication, which will affect the reliability of the TSV structure.

[0049] Based on this, the embodiment of the present application provides a chip, which adopts a new TSV structure. It is not necessary to clear a large area of ​​the etch stop layer in the TSV area. Instead, metal connection pads are respectively provided on the upper and lower sides of the etch stop layer, and the two metal connection pads are electrically connected through metal vias to form an intermediate connection structure. The position of the TSV in the AlN layer is divided into an upper and lower structure, and the two structures are connected through the intermediate connection structure to form a new TSV structure that runs through the chip, avoiding the interference of the etch stop layer on the production of TSV, and also ensuring the reliability of TSV.

[0050] The specific structure of the novel TSV provided in the embodiment of the present application is described below in conjunction with a chip.

[0051] Schematically, the present application embodiment provides a chip, such as Figure 2 As shown, the chip includes a silicon substrate 10 and a first etch stop layer 21 disposed on the silicon substrate 10. The first etch stop layer 21 is located in the back end of line (BEOL) process of the chip.

[0052] The silicon substrate 10 may include a silicon substrate and a device layer manufactured on the surface of the silicon substrate through a front-end-of-line (FEOL) process. The device layer may include a plurality of field effect transistors (such as FinFET, GAA, etc.).

[0053] The present application does not limit the specific position of the first etch stop layer 21 in the back-end process (BEOL). Of course, other etch stop layers may also be included in the back-end process (BEOL). Figure 1 The etching stop layer ESL1 in FIG. 1 is taken as an example for explanation.

[0054] In some possible implementations, the first etch stop layer 21 may be made of one or more difficult-to-etch materials such as metal nitrides and metal oxides, wherein the metal nitrides may include materials such as AlN, and the metal oxides may include materials such as Al2O3. In the following embodiments, the first etch stop layer 21 is described using an AlN layer as an example.

[0055] On this basis, if Figure 2 As shown, in the chip provided in the embodiment of the present application, the TSV structure is divided into two sections: a first through silicon via TSV1 and a first vertical connection structure 30. The first through silicon via TSV1 is located below the first etch stop layer 21 and penetrates the silicon substrate 10, and the first vertical connection structure 30 is located above the first etch stop layer 21. The setting form of the first vertical connection structure 30 can be set as needed, and the first vertical connection structure 30 can be a metal through hole or other forms. For details, please refer to the relevant description below.

[0056] like Figure 2 and Figure 3 ( Figure 2 As shown in the enlarged schematic diagram of A1 in FIG, the chip also includes an intermediate connection structure A1, which is connected between the first through silicon via TSV1 and the first vertical connection structure 30, thereby forming a TSV structure that runs through the entire chip. Among them, the intermediate connection structure A1 includes a first metal connection pad P1 and a second metal connection pad P2. The first metal connection pad P1 is located below the first etch stop layer 21 (i.e., the side close to the silicon substrate 10), and the second metal connection pad P2 is located above the first etch stop layer 21 (i.e., the side away from the silicon substrate 10), and the first metal connection pad P1 and the second metal connection pad P2 are electrically connected through a plurality of first metal vias 31 that penetrate the first etch stop layer 21.

[0057] In this case, refer to Figure 2 As shown, the top end of the first through silicon via TSV1 (i.e., the end close to the intermediate connection structure A1) is electrically connected to the first metal connection pad P1, and the bottom end of the first through silicon via TSV1 (i.e., the end away from the intermediate connection structure A1) can be connected to the redistribution layer (RDL) on the back side of the silicon substrate 10. The bottom end of the first vertical connection structure 30 (i.e., the end close to the intermediate connection structure A1) is electrically connected to the second metal connection pad P2, and the top end of the first vertical connection structure 30 (i.e., the end away from the intermediate connection structure A1) can be electrically connected to the redistribution layer (RDL) on the front side of the chip. Figure 2 The redistribution layers (RDL) on the front and back sides of the chip are not used.

[0058] It should be noted that, in the chip provided in the embodiment of the present application, the number of the first through silicon via TSV1 connected to the first metal connection pad P1 may be one or more; the number of the first vertical connection structure 30 connected to the second metal connection pad P2 may be multiple or one; the number of the first through silicon vias TSV1 may be the same as or different from the number of the first vertical connection structures 30; the projection of the first through silicon via TSV1 may overlap with the projection of the first vertical connection structure 30 or may not overlap; the present application does not impose any restrictions on this, and it can be set as needed in practice.

[0059] In summary, in the chip provided in the embodiment of the present application, two metal connection pads (P1, P2) are arranged above and below the first etch stop layer 21, and the two metal connection pads (P1, P2) are connected through a plurality of first metal vias 31 to form an intermediate connection structure A1. In this case, it is not necessary to perform a large-area clearance of the first etch stop layer 21 in the TSV region. It is only necessary to divide the TSV into two sections, namely the first silicon through hole TSV1 and the first vertical connection structure 30. The first silicon through hole TSV1 is located below the intermediate connection structure A1, and the first vertical connection structure 30 is located above the intermediate connection structure A1. The first silicon through hole TSV1 and the first vertical connection structure 30 are connected through the intermediate connection structure A1, thereby forming a TSV structure that runs through the entire chip. In this way, the interference of the first etch stop layer 21 in the production of TSV due to the inability to perform a large-area clearance can be avoided, and the reliability of the TSV structure can also be guaranteed.

[0060] It should be noted that Figure 2 and Figure 3 The example of the second metal connection pad P2 being in direct contact with the first etch stop layer 21 is used for illustration only, but the present application is not limited thereto. In some possible implementations, other film layers may be provided between the second metal connection pad P2 and the first etch stop layer 21, such as a dielectric layer made of oxide material, etc.; in practice, they may be provided according to the requirements of the chip. Similarly, the first metal connection pad P1 may be in direct contact with the first etch stop layer 21, or other film layers may be provided therebetween, and the present application does not limit this.

[0061] It can be understood that the first through silicon via TSV1 and the first vertical connection structure 30 are electrically connected through the intermediate connection structure A1, the bottom of the first through silicon via TSV1 can be electrically connected to other chips in the vertical direction through the redistribution layer (RDL) on the back of the chip, and the top of the first vertical connection structure 30 can be electrically connected to other chips in the vertical direction through the redistribution layer (RDL) on the front of the chip. The stacked chips can be connected by hybrid bonding, bump connection, etc., and this application does not limit this.

[0062] It can also be understood that, in the chip provided in the embodiment of the present application, since the first through silicon via TSV1 and the first vertical connection structure 30 are connected through the intermediate connection structure A1, the first through silicon via TSV1 and the first vertical connection structure 30 may not completely overlap in the direction perpendicular to the chip, and the relative positions of the two may have a certain offset without affecting the electrical connection of the entire TSV structure.

[0063] In addition, an electrical connection structure formed in two stacked chips may use multiple TSV structures. For example, nine TSVs arranged in a 3×3 array may be provided in the chip as a whole as an electrical connection structure to be electrically connected to another chip.

[0064] Therefore, in the chip provided in the embodiment of the present application, a plurality of TSVs forming an electrical connection structure can be divided into two sections. In this case, Figure 2 As shown, the intermediate connection structure A1 can be connected to multiple first silicon through vias TSV1 and multiple first vertical connection structures 30, that is, the first metal connection pad P1 is connected to the multiple first silicon through vias TSV1 located below it, and the second metal connection pad P2 is connected to the multiple first vertical connection structures 30 located above it.

[0065] The chip provided in the embodiment of the present application is further described below in conjunction with the specific positions of the first etch stop layer 21 and the intermediate connection structure A1 in the back-end-of-line (BEOL) process.

[0066] refer to Figure 1 As shown, among the multiple metal routing layers in the back-end process (BEOL), the first metal routing layer M1 is located in the lowest layer (i.e., the first layer), the second metal routing layer M2 is located in the second lowest layer (i.e., the second layer), the third metal routing layer M3 is located in the third layer, and the fourth metal routing layer M4 is located in the fourth layer. The first metal routing layer M1 is connected to the second metal routing layer M2 through a plurality of metal vias V1 located in the first via layer. The second metal routing layer M2 is connected to the third metal routing layer M3 through a plurality of metal vias V2 located in the second via layer. The third metal routing layer M3 is connected to the fourth metal routing layer M4 through a plurality of metal vias V3 located in the third via layer.

[0067] refer to Figure 1 , Figure 2 , Figure 3As shown, in some possible implementations, the first etch stop layer 21 is an etch stop layer ESL1 on the surface of the first metal wiring layer M1. In this case, in order to simplify the process and reduce the difficulty of manufacturing, the first metal connection pad P1 can be arranged in the same layer as the first metal wiring layer M1, that is, the first metal connection pad P1 and the first metal wiring layer M1 are manufactured by the same manufacturing process, and the first metal connection pad P1 and the first metal wiring layer M1 have the same material.

[0068] Similarly, in some possible implementations, the second metal connection pad P2 can be disposed in the same layer as the second metal wiring layer M2, that is, the second metal connection pad P2 and the second metal wiring layer M2 are manufactured by the same manufacturing process. Of course, in this case, a dielectric layer, such as an oxide layer, can be disposed between the second metal connection pad P2 and the first etch stop layer 21. Figure 2 and Figure 3 Not shown in FIG.

[0069] Similarly, in some possible implementations, multiple first metal vias 31 connected between two metal connecting plates (P1, P2) can be arranged in the same layer as multiple metal vias V1 in the first via layer, that is, multiple first metal vias 31 and multiple metal vias V1 can be manufactured through the same manufacturing process.

[0070] In order to ensure the process window of the first metal via 31 during the processing, in some possible implementation methods, the aperture of the first metal via 31 can be set to be the same or approximately the same as the aperture of the metal via V1 in the first via layer, thereby ensuring that the first metal via 31 has excellent electrical properties and reliability.

[0071] For example, in some embodiments, the aperture of the first metal via 31 is the same as the aperture of the metal via V1 in the first via layer, and the aperture of the first metal via 31 and the aperture of the metal via V1 in the first via layer are in the range of 20 nm to 400 nm.

[0072] In addition, compared with the width of the signal line in the metal routing layer, the outer diameter of the metal connection pad (P1, P2) is much larger than the width of the signal line. Therefore, in order to ensure the process window of the metal connection pad (P1, P2) during the processing, Figure 4 As shown, in some possible implementations, the metal connection plates (P1, P2) may be set to a mesh structure to ensure the feasibility and stability of process processing.

[0073] Schematically, taking the first metal connection plate P1 as an example, Figure 4 As shown, in some possible implementations, the grid line width in the first metal connection pad P1 may be set to be the same as the signal line width in the first metal routing layer M1.

[0074] Similarly, in some possible implementations, the second metal connection pad P2 may also be a mesh structure, and the width of the metal line in the mesh structure may be the same as or close to the width of the signal line in the second metal routing layer M2.

[0075] The above embodiment is only for describing an etch stop layer, but the present application is not limited thereto.

[0076] In some possible implementations, such as Figure 5 As shown, a second etch stop layer 22 may be further disposed above the first etch stop layer 21 , that is, the first etch stop layer 21 and the second etch stop layer 22 are disposed simultaneously in the back end of line (BEOL) process.

[0077] The second etch stop layer 22 is similar to the first etch stop layer 21, and also uses a material that is difficult to etch. The second etch stop layer 22 and the first etch stop layer 21 can use the same material or different materials, and this application does not limit this. For the material of the second etch stop layer 22, reference can be made to the relevant description of the first etch stop layer 21 above, and it will not be repeated here.

[0078] Illustratively, in some possible implementations, the second etch stop layer 22 may be an AlN layer.

[0079] In this case, in order to avoid a large area clearance of the second etch stop layer 22 in the TSV region, refer to Figure 5 and Figure 6 ( Figure 5 ), a third metal connection pad P3 can be added to the intermediate connection structure A1, that is, the intermediate connection structure A1 further includes a third metal connection pad P3 on the basis of the aforementioned first metal connection pad P1 and second metal connection pad P2. Among them, the third metal connection pad P3 is located above the second etch stop layer 22, and the third metal connection pad P3 and the second metal connection pad P2 are connected through a plurality of second metal vias 32 that penetrate the second etch stop layer 22. The first vertical connection structure 30 is located above the third metal connection pad P3, and the bottom end of the first vertical connection structure 30 is connected to the third metal connection pad P3, and the top end of the first vertical connection structure 30 is electrically connected to the redistribution layer (RDL) on the front side of the chip. In this way, there is no need to clear the second etch stop layer 22 in the TSV area over a large area, which avoids interference with the production of TSV due to the inability to clear the second etch stop layer 22 over a large area, and can also ensure the reliability of the TSV structure.

[0080] It should be noted that Figure 5 and Figure 6The example of the third metal connection pad P3 directly contacting the second etch stop layer 22 is used for illustration only, but the present application is not limited thereto. In some possible implementations, other film layers may be provided between the third metal connection pad P3 and the second etch stop layer 22, such as a dielectric layer made of an oxide material, etc. In practice, such a layer may be provided according to the requirements of the chip.

[0081] On this basis, combined with Figure 5 , Figure 6 , Figure 7 As shown, in some possible implementations, the second etch stop layer 22 can be an etch stop layer ESL2 on the surface of the second metal wiring layer M2. In this case, in order to simplify the process and reduce the difficulty of manufacturing, the third metal connection pad P3 can be arranged in the same layer as the third metal wiring layer M3, that is, the third metal connection pad P3 and the third metal wiring layer M3 are manufactured by the same manufacturing process. The multiple second metal vias 32 connected between the second metal connection pad P2 and the third metal connection pad P3 can be arranged in the same layer as the multiple metal vias V2 in the second via layer, that is, the multiple second metal vias 32 and the multiple metal vias V2 are manufactured by the same manufacturing process.

[0082] As shown, the third metal connection plate P3 may adopt a mesh structure, and the details may refer to the related description of the first metal connection plate P1 in the foregoing text, which will not be repeated here.

[0083] Schematically, the aperture of the second metal via 32 may be the same as the aperture of the plurality of metal vias V2 in the second via layer. For details, please refer to the related description of the first metal via 31 in the foregoing text, which will not be repeated here.

[0084] On this basis, reference Figure 8 As shown, in some possible implementations, a third etch stop layer 23 may be further provided above the second etch stop layer 22. That is, the first etch stop layer 21, the second etch stop layer 22, and the third etch stop layer 23 are provided simultaneously in the back end of line (BEOL).

[0085] The third etch stop layer 23 is similar to the first etch stop layer 21, and also uses a material that is difficult to etch. The third etch stop layer 23 and the first etch stop layer 21 can use the same material or different materials, and this application does not limit this. For the material of the third etch stop layer 23, reference can be made to the relevant description of the first etch stop layer 21 above, and it will not be repeated here.

[0086] Illustratively, in some possible implementations, the third etch stop layer 23 may be an AlN layer.

[0087] In this case, in order to avoid a large area clearance of the third etch stop layer 23 in the TSV region, refer to Figure 8 and Fig. 9 ( Figure 8 ), a fourth metal connection pad P4 can be added to the intermediate connection structure A1, that is, in the intermediate connection structure A1, a fourth metal connection pad P4 is further provided on the basis of the aforementioned first metal connection pad P1, first metal connection pad P2, and third metal connection pad P3. Among them, the fourth metal connection pad P4 is located above the third etch stop layer 23, and the fourth metal connection pad P4 and the third metal connection pad P3 are connected through a plurality of third metal vias 33 penetrating the third etch stop layer 23. The first vertical connection structure 30 is located above the fourth metal connection pad P4, and the bottom end of the first vertical connection structure 30 is connected to the fourth metal connection pad P4, and the top end of the first vertical connection structure 30 is electrically connected to the redistribution layer (RDL) on the front side of the chip. In this way, there is no need to clear a large area of ​​the third etch stop layer 23 in the TSV area, which avoids interference with the production of TSV due to the inability to clear a large area of ​​the third etch stop layer 23, and can also ensure the reliability of the TSV structure.

[0088] It should be noted that Figure 8 and Fig. 9 The fourth metal connection pad P4 is directly in contact with the third etch stop layer 23 as an example for illustration, but the present application is not limited thereto. In some possible implementations, other film layers may be provided between the fourth metal connection pad P4 and the third etch stop layer 23, such as a dielectric layer made of an oxide material, etc. In practice, such a layer may be provided according to the requirements of the chip.

[0089] On this basis, combined with Figure 8 , Fig. 9 , Fig.10 As shown, in some possible implementations, the third etch stop layer 23 can be an etch stop layer ESL3 on the surface of the third metal wiring layer M3. In this case, in order to simplify the process and reduce the difficulty of manufacturing, the fourth metal connection pad P4 can be arranged in the same layer as the fourth metal wiring layer M4, that is, the fourth metal connection pad P4 and the fourth metal wiring layer M4 are manufactured by the same manufacturing process. The multiple third metal vias 33 connected between the fourth metal connection pad P4 and the third metal connection pad P3 can be arranged in the same layer as the multiple metal vias V3 in the third via layer, that is, the multiple third metal vias 33 and the multiple metal vias V3 are manufactured by the same manufacturing process.

[0090] As shown, the fourth metal connection plate P4 may adopt a mesh structure, and the details may refer to the related description of the first metal connection plate P1 in the foregoing text, which will not be repeated here.

[0091] Schematically, the aperture of the third metal via 33 may be the same as the aperture of the plurality of metal vias V3 in the third via layer. For details, please refer to the related description of the first metal via 31 in the foregoing text, which will not be repeated here.

[0092] Of course, more difficult-to-etch film layers can be set in the chip in the back-end process (BEOL). As mentioned above, metal connection pads can be added above the film layer and connected to the metal connection pads below through metal vias. This article will not go into details.

[0093] In addition, the present application does not limit the manufacturing method of the first through silicon via TSV1 and the first vertical connection structure 30 , and they can be manufactured as needed in practice.

[0094] For the first through silicon via TSV1:

[0095] In some possible implementations, the first through silicon via TSV1 may be manufactured using a via-middle process.

[0096] In some possible implementations, the first through silicon via TSV1 may also be manufactured using a via-last process.

[0097] For the first vertical connection structure 30:

[0098] In some possible implementations, the first vertical connection structure 30 may include a metal via structure located in the back-end of the line (BEOL). In this case, the first vertical connection structure 30 may be manufactured using a via-middle process or a via-last process.

[0099] In some possible implementations, the first vertical connection structure 30 may include a TSV (also referred to as a second through silicon via) located in the back end of line (BEOL), that is, the structure of the TSV is similar to that of the first through silicon via TSV1, and both are manufactured using a through silicon via process. Of course, in this case, the first vertical connection structure 30 may be manufactured using a via-middle or via-last process.

[0100] In some possible implementations, the first vertical connection structure 30 may be a vertical interconnect structure formed by multiple layers of interconnection routing in a back-end-of-line (BEOL) process.

[0101] For illustration, several specific manufacturing methods of the first through silicon via TSV1 and the first vertical connection structure 30 are provided below.

[0102] Production method 1

[0103] In this production method 1, reference Fig.11 As shown, the first through silicon via TSV1 is a TSV manufactured by a via-middle process, and the first vertical connection structure 30 is a TSV manufactured by a via-middle process.

[0104] Specifically, refer to Fig.11 As shown in (a), the first through silicon via TSV1 can be manufactured by a via-middle process, that is, the first through silicon via TSV1 is manufactured after forming a device layer on the silicon substrate 10 and before manufacturing the intermediate connection structure A1. Fig.11 As shown in (b), before the end of the back-end process (BEOL), a via-middle process is used to manufacture TSV as the first vertical connection structure 30. In this case, the top of the first vertical connection structure 30 is led out through one or more layers of interconnection routing located in the back-end process (BEOL) and connected to the redistribution layer on the front side of the chip. Fig.11 As shown in (c), the silicon substrate 10 is thinned from the back to expose the first through silicon via TSV1, and other related manufacturing is performed, such as manufacturing a redistribution layer connected to the first through silicon via TSV1 on the silicon substrate 10.

[0105] Production method 2

[0106] In the second production method, refer to Fig.12 As shown, the first through silicon via TSV1 is a TSV manufactured by a via-last process, and the first vertical connection structure 30 is a TSV manufactured by a via-last process.

[0107] Specifically, refer to Fig.12 As shown in (a), the intermediate connection structure A1 is fabricated in the back-end process (BEOL) of the chip, but the first through silicon via TSV1 and the first vertical connection structure 30 are not fabricated. Fig.12 As shown in (b) and (c), after the BEOL process is completed, a via-last process is firstly adopted to firstly fabricate TSV as a first vertical connection structure 30 from the front side of the chip, and then fabricate a first through silicon via TSV1 from the back side of the chip.

[0108] Production method three

[0109] In the third production method, refer to Fig.13 As shown, the first through silicon via TSV1 is a TSV manufactured by a via-middle process, and the first vertical connection structure 30 is a TSV manufactured by a via-last process.

[0110] Production method 4

[0111] In the fourth production method, refer to Fig.14 As shown, the first vertical connection structure 30 is a TSV manufactured by a via-middle process, and the first through silicon via TSV1 is a TSV manufactured by a via-last process.

[0112] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: include: Silicon substrate; A first etch stop layer, wherein the first etch stop layer is located in a back-end process; a first metal connection pad and a second metal connection pad, wherein the first metal connection pad is located on a side of the first etch stop layer close to the silicon substrate, and the second metal connection pad is located on a side of the first etch stop layer away from the silicon substrate, and the first metal connection pad and the second metal connection pad are connected via a plurality of first metal vias penetrating the first etch stop layer; One or more first through silicon vias, wherein the one or more first through silicon vias penetrate the silicon substrate and are connected to the first metal connection pad; One or more first vertical connection structures are electrically connected to the second metal connection pad and lead to a side away from the silicon substrate.

2. The chip according to claim 1, characterized in that: The first etch stop layer includes at least one of metal nitride and metal oxide.

3. The chip according to claim 1 or 2, characterized in that: The first etch stop layer includes AlN.

4. The chip according to any one of claims 1 to 3, characterized in that: The chip comprises: a first metal routing layer, a second metal routing layer and a first via layer located in the back-end process, wherein the second metal routing layer is connected to the first metal routing layer through a plurality of vias in the first via layer; The first connection pad is arranged in the same layer as the first metal wiring layer, the second metal connection pad is arranged in the same layer as the second metal wiring layer; the plurality of first metal vias are arranged in the same layer as the plurality of vias in the first via layer.

5. The chip according to claim 4, characterized in that: The apertures of the plurality of first metal vias are the same as the apertures of the plurality of vias in the first via layer.

6. The chip according to any one of claims 1 to 5, characterized in that: The first metal connection plate and the second metal connection plate are mesh structures.

7. The chip according to any one of claims 4 to 6, characterized in that: The chip includes a plurality of metal routing layers in the back-end process, and the first metal routing layer is the one of the plurality of metal routing layers that is closest to the silicon substrate.

8. The chip according to any one of claims 1 to 7, characterized in that: The first vertical connection structure includes a metal via fabricated by a middle via process or a last via process.

9. The chip according to any one of claims 1 to 8, characterized in that: The first through silicon via includes a through silicon via manufactured by a middle through via process or a last through via process.

10. The chip according to any one of claims 1 to 9, characterized in that: The chip further comprises: a second etch stop layer and a third metal connection pad; The second etch stop layer is located on a side of the second metal connection pad away from the first etch stop layer; The third metal connection pad is located on a side of the second etch stop layer away from the second metal connection pad, and the third metal connection pad is connected to the second metal connection pad through a plurality of second metal vias penetrating the second etch stop layer; The plurality of first vertical connection structures are located on a side of the third metal connection pad away from the silicon substrate, and the plurality of first vertical connection structures are connected to the third metal connection pad.

11. The chip according to claim 10, characterized in that: The chip further comprises: a third etch stop layer and a fourth metal connection pad; The third etch stop layer is located on a side of the third metal connection pad away from the second etch stop layer; The fourth metal connection pad is located on a side of the third etch stop layer away from the third metal connection pad, and the fourth metal connection pad is connected to the third metal connection pad through a plurality of third metal vias penetrating the third etch stop layer; The plurality of first vertical connection structures are located on a side of the fourth metal connection pad away from the silicon substrate, and the plurality of first vertical connection structures are connected to the fourth metal connection pad.

12. The chip according to any one of claims 1 to 11, characterized in that: The first vertical connection structure includes a second through silicon via.

13. A chip stacking package, characterized in that: comprising a first chip and a second chip which are stacked; The first chip is the chip according to any one of claims 1 to 12, and the first chip is electrically connected to the second chip through the first through silicon via or the first vertical connection structure.

14. An electronic device, characterized in that: The invention comprises a circuit board and the chip stack package as claimed in claim 13, wherein the chip stack package is electrically connected to the circuit board.

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